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Update project tt_um_mroblesh (mroblesh1/tt09-ece-110) #434

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merged 1 commit into from
Nov 10, 2024
Merged

Update project tt_um_mroblesh (mroblesh1/tt09-ece-110) #434

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4 changes: 2 additions & 2 deletions projects/tt_um_mroblesh/commit_id.json
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
{
"app": "Tiny Tapeout tt09 a48b1c74",
"repo": "https://github.com/mroblesh1/tt09-ece-110",
"commit": "d980085c8d4f4adffdf0a9a7cb3ecae34cd11f4c",
"workflow_url": "https://github.com/mroblesh1/tt09-ece-110/actions/runs/11747325830",
"commit": "a2d2048cd7138c998131d10d961d846dd389e502",
"workflow_url": "https://github.com/mroblesh1/tt09-ece-110/actions/runs/11765046262",
"sort_id": 1731090701857,
"openlane_version": "OpenLane2 2.1.9",
"pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"
Expand Down
2 changes: 1 addition & 1 deletion projects/tt_um_mroblesh/info.yaml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ project:
# Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
source_files:
- "tt_um_mroblesh.v"
- "lif.v"
- "FrequencyDecoder.v"

# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
pinout:
Expand Down
192 changes: 97 additions & 95 deletions projects/tt_um_mroblesh/stats/metrics.csv
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,23 +1,23 @@
Metric,Value
design__lint_error__count,0
design__lint_timing_construct__count,0
design__lint_warning__count,0
design__lint_warning__count,1
design__inferred_latch__count,0
design__instance__count,309
design__instance__area,963.424
design__instance__count,607
design__instance__area,4428
design__instance_unmapped__count,0
synthesis__check_error__count,0
design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
design__max_fanout_violation__count__corner:nom_tt_025C_1v80,0
design__max_fanout_violation__count__corner:nom_tt_025C_1v80,4
design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
power__internal__total,0.0000769911493989639
power__switching__total,0.00005620262527372688
power__leakage__total,1.9621495539468015E-9
power__total,0.000133195731905289
clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.0038381243714055834
clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.0038381243714055834
timing__hold__ws__corner:nom_tt_025C_1v80,0.4927480785092014
timing__setup__ws__corner:nom_tt_025C_1v80,14.109485534848291
power__internal__total,0.00033499218989163637
power__switching__total,0.00011578486009966582
power__leakage__total,5.3335180716374E-9
power__total,0.000450782390544191
clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.006771722263491681
clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.006771722263491681
timing__hold__ws__corner:nom_tt_025C_1v80,0.3138015491830479
timing__setup__ws__corner:nom_tt_025C_1v80,13.11575951636019
timing__hold__tns__corner:nom_tt_025C_1v80,0.0
timing__setup__tns__corner:nom_tt_025C_1v80,0.0
timing__hold__wns__corner:nom_tt_025C_1v80,0
Expand All @@ -29,12 +29,12 @@ timing__setup_vio__count__corner:nom_tt_025C_1v80,0
timing__setup_r2r__ws__corner:nom_tt_025C_1v80,Infinity
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
design__max_slew_violation__count__corner:nom_ss_100C_1v60,0
design__max_fanout_violation__count__corner:nom_ss_100C_1v60,0
design__max_fanout_violation__count__corner:nom_ss_100C_1v60,4
design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.005689282539444282
clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.005689282539444282
timing__hold__ws__corner:nom_ss_100C_1v60,1.2003463007756352
timing__setup__ws__corner:nom_ss_100C_1v60,12.218042035043302
clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.01227673553121231
clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.01227673553121231
timing__hold__ws__corner:nom_ss_100C_1v60,0.91530330350201
timing__setup__ws__corner:nom_ss_100C_1v60,10.123326463643137
timing__hold__tns__corner:nom_ss_100C_1v60,0.0
timing__setup__tns__corner:nom_ss_100C_1v60,0.0
timing__hold__wns__corner:nom_ss_100C_1v60,0
Expand All @@ -46,12 +46,12 @@ timing__setup_vio__count__corner:nom_ss_100C_1v60,0
timing__setup_r2r__ws__corner:nom_ss_100C_1v60,Infinity
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,4
design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.00282775200148237
clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.00282775200148237
timing__hold__ws__corner:nom_ff_n40C_1v95,0.22587918286250808
timing__setup__ws__corner:nom_ff_n40C_1v95,14.70390428811443
clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.005485195786170596
clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.005485195786170596
timing__hold__ws__corner:nom_ff_n40C_1v95,0.11523610170042874
timing__setup__ws__corner:nom_ff_n40C_1v95,14.144431803938161
timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
timing__hold__wns__corner:nom_ff_n40C_1v95,0
Expand All @@ -63,12 +63,12 @@ timing__setup_vio__count__corner:nom_ff_n40C_1v95,0
timing__setup_r2r__ws__corner:nom_ff_n40C_1v95,Infinity
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
design__max_slew_violation__count,0
design__max_fanout_violation__count,0
design__max_fanout_violation__count,4
design__max_cap_violation__count,0
clock__skew__worst_hold,0.0063262175066854855
clock__skew__worst_setup,0.0026796760013851144
timing__hold__ws,0.22153723926827862
timing__setup__ws,12.184106513023638
clock__skew__worst_hold,0.014324930536118942
clock__skew__worst_setup,0.004609646128613346
timing__hold__ws,0.1126785363574181
timing__setup__ws,10.065258245099281
timing__hold__tns,0.0
timing__setup__tns,0.0
timing__hold__wns,0
Expand All @@ -86,12 +86,12 @@ flow__errors__count,0
design__io,45
design__die__area,17954.7
design__core__area,16493.3
design__instance__count__stdcell,309
design__instance__area__stdcell,963.424
design__instance__count__stdcell,607
design__instance__area__stdcell,4428
design__instance__count__macros,0
design__instance__area__macros,0
design__instance__utilization,0.058413
design__instance__utilization__stdcell,0.058413
design__instance__utilization,0.268472
design__instance__utilization__stdcell,0.268472
design__power_grid_violation__count__net:VPWR,0
design__power_grid_violation__count__net:VGND,0
design__power_grid_violation__count,0
Expand All @@ -100,44 +100,46 @@ timing__drv__floating__pins,0
design__instance__displacement__total,0
design__instance__displacement__mean,0
design__instance__displacement__max,0
route__wirelength__estimated,1519.16
route__wirelength__estimated,6265.13
design__violations,0
design__instance__count__setup_buffer,0
design__instance__count__hold_buffer,0
design__instance__count__hold_buffer,11
antenna__violating__nets,0
antenna__violating__pins,0
route__antenna_violation__count,0
route__net,102
route__net,394
route__net__special,2
route__drc_errors__iter:1,62
route__wirelength__iter:1,1683
route__drc_errors__iter:2,40
route__wirelength__iter:2,1621
route__drc_errors__iter:3,13
route__wirelength__iter:3,1609
route__drc_errors__iter:4,0
route__wirelength__iter:4,1621
route__drc_errors__iter:1,237
route__wirelength__iter:1,7271
route__drc_errors__iter:2,93
route__wirelength__iter:2,7166
route__drc_errors__iter:3,28
route__wirelength__iter:3,7134
route__drc_errors__iter:4,9
route__wirelength__iter:4,7111
route__drc_errors__iter:5,0
route__wirelength__iter:5,7097
route__drc_errors,0
route__wirelength,1621
route__vias,559
route__vias__singlecut,559
route__wirelength,7097
route__vias,2602
route__vias__singlecut,2602
route__vias__multicut,0
design__disconnected_pin__count,9
design__disconnected_pin__count,14
design__critical_disconnected_pin__count,0
route__wirelength__max,94.08
timing__unannotated_net__count__corner:nom_tt_025C_1v80,25
route__wirelength__max,154.85
timing__unannotated_net__count__corner:nom_tt_025C_1v80,52
timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
timing__unannotated_net__count__corner:nom_ss_100C_1v60,25
timing__unannotated_net__count__corner:nom_ss_100C_1v60,52
timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0
timing__unannotated_net__count__corner:nom_ff_n40C_1v95,25
timing__unannotated_net__count__corner:nom_ff_n40C_1v95,52
timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
design__max_slew_violation__count__corner:min_tt_025C_1v80,0
design__max_fanout_violation__count__corner:min_tt_025C_1v80,0
design__max_fanout_violation__count__corner:min_tt_025C_1v80,4
design__max_cap_violation__count__corner:min_tt_025C_1v80,0
clock__skew__worst_hold__corner:min_tt_025C_1v80,0.0036552983896547637
clock__skew__worst_setup__corner:min_tt_025C_1v80,0.0036552983896547637
timing__hold__ws__corner:min_tt_025C_1v80,0.48705318934332414
timing__setup__ws__corner:min_tt_025C_1v80,14.129926961755814
clock__skew__worst_hold__corner:min_tt_025C_1v80,0.0057682193987276175
clock__skew__worst_setup__corner:min_tt_025C_1v80,0.0057682193987276175
timing__hold__ws__corner:min_tt_025C_1v80,0.3099089961263207
timing__setup__ws__corner:min_tt_025C_1v80,13.144477878194985
timing__hold__tns__corner:min_tt_025C_1v80,0.0
timing__setup__tns__corner:min_tt_025C_1v80,0.0
timing__hold__wns__corner:min_tt_025C_1v80,0
Expand All @@ -148,15 +150,15 @@ timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
timing__setup_vio__count__corner:min_tt_025C_1v80,0
timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
timing__unannotated_net__count__corner:min_tt_025C_1v80,25
timing__unannotated_net__count__corner:min_tt_025C_1v80,52
timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
design__max_slew_violation__count__corner:min_ss_100C_1v60,0
design__max_fanout_violation__count__corner:min_ss_100C_1v60,0
design__max_fanout_violation__count__corner:min_ss_100C_1v60,4
design__max_cap_violation__count__corner:min_ss_100C_1v60,0
clock__skew__worst_hold__corner:min_ss_100C_1v60,0.005439426840685989
clock__skew__worst_setup__corner:min_ss_100C_1v60,0.005439426840685989
timing__hold__ws__corner:min_ss_100C_1v60,1.1893516508295199
timing__setup__ws__corner:min_ss_100C_1v60,12.25745140081839
clock__skew__worst_hold__corner:min_ss_100C_1v60,0.010592194088306476
clock__skew__worst_setup__corner:min_ss_100C_1v60,0.010592194088306476
timing__hold__ws__corner:min_ss_100C_1v60,0.9087360010587087
timing__setup__ws__corner:min_ss_100C_1v60,10.175691688392806
timing__hold__tns__corner:min_ss_100C_1v60,0.0
timing__setup__tns__corner:min_ss_100C_1v60,0.0
timing__hold__wns__corner:min_ss_100C_1v60,0
Expand All @@ -167,15 +169,15 @@ timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
timing__setup_vio__count__corner:min_ss_100C_1v60,0
timing__setup_r2r__ws__corner:min_ss_100C_1v60,Infinity
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
timing__unannotated_net__count__corner:min_ss_100C_1v60,25
timing__unannotated_net__count__corner:min_ss_100C_1v60,52
timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
design__max_slew_violation__count__corner:min_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:min_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:min_ff_n40C_1v95,4
design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.0026796760013851144
clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.0026796760013851144
timing__hold__ws__corner:min_ff_n40C_1v95,0.22153723926827862
timing__setup__ws__corner:min_ff_n40C_1v95,14.720175717223523
clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.004609646128613346
clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.004609646128613346
timing__hold__ws__corner:min_ff_n40C_1v95,0.1126785363574181
timing__setup__ws__corner:min_ff_n40C_1v95,14.163849161098806
timing__hold__tns__corner:min_ff_n40C_1v95,0.0
timing__setup__tns__corner:min_ff_n40C_1v95,0.0
timing__hold__wns__corner:min_ff_n40C_1v95,0
Expand All @@ -186,15 +188,15 @@ timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
timing__setup_vio__count__corner:min_ff_n40C_1v95,0
timing__setup_r2r__ws__corner:min_ff_n40C_1v95,Infinity
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
timing__unannotated_net__count__corner:min_ff_n40C_1v95,25
timing__unannotated_net__count__corner:min_ff_n40C_1v95,52
timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
design__max_slew_violation__count__corner:max_tt_025C_1v80,0
design__max_fanout_violation__count__corner:max_tt_025C_1v80,0
design__max_fanout_violation__count__corner:max_tt_025C_1v80,4
design__max_cap_violation__count__corner:max_tt_025C_1v80,0
clock__skew__worst_hold__corner:max_tt_025C_1v80,0.004340444793103827
clock__skew__worst_setup__corner:max_tt_025C_1v80,0.004340444793103827
timing__hold__ws__corner:max_tt_025C_1v80,0.4959499618027758
timing__setup__ws__corner:max_tt_025C_1v80,14.089897647426241
clock__skew__worst_hold__corner:max_tt_025C_1v80,0.008178236097592603
clock__skew__worst_setup__corner:max_tt_025C_1v80,0.008178236097592603
timing__hold__ws__corner:max_tt_025C_1v80,0.3172438512794044
timing__setup__ws__corner:max_tt_025C_1v80,13.08500367317298
timing__hold__tns__corner:max_tt_025C_1v80,0.0
timing__setup__tns__corner:max_tt_025C_1v80,0.0
timing__hold__wns__corner:max_tt_025C_1v80,0
Expand All @@ -205,15 +207,15 @@ timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
timing__setup_vio__count__corner:max_tt_025C_1v80,0
timing__setup_r2r__ws__corner:max_tt_025C_1v80,Infinity
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
timing__unannotated_net__count__corner:max_tt_025C_1v80,25
timing__unannotated_net__count__corner:max_tt_025C_1v80,52
timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
design__max_slew_violation__count__corner:max_ss_100C_1v60,0
design__max_fanout_violation__count__corner:max_ss_100C_1v60,0
design__max_fanout_violation__count__corner:max_ss_100C_1v60,4
design__max_cap_violation__count__corner:max_ss_100C_1v60,0
clock__skew__worst_hold__corner:max_ss_100C_1v60,0.0063262175066854855
clock__skew__worst_setup__corner:max_ss_100C_1v60,0.0063262175066854855
timing__hold__ws__corner:max_ss_100C_1v60,1.209396617083735
timing__setup__ws__corner:max_ss_100C_1v60,12.184106513023638
clock__skew__worst_hold__corner:max_ss_100C_1v60,0.014324930536118942
clock__skew__worst_setup__corner:max_ss_100C_1v60,0.014324930536118942
timing__hold__ws__corner:max_ss_100C_1v60,0.9215238277737618
timing__setup__ws__corner:max_ss_100C_1v60,10.065258245099281
timing__hold__tns__corner:max_ss_100C_1v60,0.0
timing__setup__tns__corner:max_ss_100C_1v60,0.0
timing__hold__wns__corner:max_ss_100C_1v60,0
Expand All @@ -224,15 +226,15 @@ timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
timing__setup_vio__count__corner:max_ss_100C_1v60,0
timing__setup_r2r__ws__corner:max_ss_100C_1v60,Infinity
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
timing__unannotated_net__count__corner:max_ss_100C_1v60,25
timing__unannotated_net__count__corner:max_ss_100C_1v60,52
timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:max_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:max_ff_n40C_1v95,4
design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.0032717440793747312
clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.0032717440793747312
timing__hold__ws__corner:max_ff_n40C_1v95,0.2291451260264151
timing__setup__ws__corner:max_ff_n40C_1v95,14.691577259478779
clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.007184031350922745
clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.007184031350922745
timing__hold__ws__corner:max_ff_n40C_1v95,0.11760126538783033
timing__setup__ws__corner:max_ff_n40C_1v95,14.123710600820521
timing__hold__tns__corner:max_ff_n40C_1v95,0.0
timing__setup__tns__corner:max_ff_n40C_1v95,0.0
timing__hold__wns__corner:max_ff_n40C_1v95,0
Expand All @@ -243,19 +245,19 @@ timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
timing__setup_vio__count__corner:max_ff_n40C_1v95,0
timing__setup_r2r__ws__corner:max_ff_n40C_1v95,Infinity
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0
timing__unannotated_net__count__corner:max_ff_n40C_1v95,25
timing__unannotated_net__count__corner:max_ff_n40C_1v95,52
timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0
timing__unannotated_net__count,25
timing__unannotated_net__count,52
timing__unannotated_net_filtered__count,0
design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79995
design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8
design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.000054767
design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.00005535
design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000233828
design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.00005535
design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79994
design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.79999
design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000632366
design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.000070633
design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000765523
design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.000070633
ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
ir__drop__avg,0.0000024099999999999997956517429342770952871433109976351261138916015625
ir__drop__worst,0.0000547999999999999970966800544314168064374825917184352874755859375
ir__drop__avg,0.0000073400000000000000278401433850827828564433730207383632659912109375
ir__drop__worst,0.000063200000000000004763377192684714600545703433454036712646484375
magic__drc_error__count,0
magic__illegal_overlap__count,0
design__lvs_device_difference__count,0
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