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feat: update project tt_um_tommythorn_cgates from tommythorn/tt09-tom…
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…mythorn-cgates

Commit: 110b100245e3de4e79b475b22670a77386a66c77
Workflow: https://github.com/tommythorn/tt09-tommythorn-cgates/actions/runs/11767981562
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@TinyTapeoutBot @urish
TinyTapeoutBot authored and urish committed Nov 10, 2024
1 parent 63e653d commit fb6d4d0
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Showing 6 changed files with 5,764 additions and 2,631 deletions.
4 changes: 2 additions & 2 deletions projects/tt_um_tommythorn_cgates/commit_id.json
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
{
"app": "Tiny Tapeout tt09 a48b1c74",
"repo": "https://github.com/tommythorn/tt09-tommythorn-cgates",
"commit": "978f02a525a2cf22e2b2f6c89158f84623b4c027",
"workflow_url": "https://github.com/tommythorn/tt09-tommythorn-cgates/actions/runs/11767531118",
"commit": "110b100245e3de4e79b475b22670a77386a66c77",
"workflow_url": "https://github.com/tommythorn/tt09-tommythorn-cgates/actions/runs/11767981562",
"sort_id": 1731264177424,
"openlane_version": "OpenLane2 2.1.9",
"pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"
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98 changes: 49 additions & 49 deletions projects/tt_um_tommythorn_cgates/stats/metrics.csv
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Original file line number Diff line number Diff line change
Expand Up @@ -3,21 +3,21 @@ design__lint_error__count,0
design__lint_timing_construct__count,0
design__lint_warning__count,22
design__inferred_latch__count,0
design__instance__count,558
design__instance__area,2538.68
design__instance__count,972
design__instance__area,5530.3
design__instance_unmapped__count,0
synthesis__check_error__count,0
design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
design__max_fanout_violation__count__corner:nom_tt_025C_1v80,0
design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
power__internal__total,0.000012812814020435326
power__switching__total,0.000014918720808054786
power__leakage__total,3.5352605287641836E-9
power__total,0.000027735070034395903
power__internal__total,1.8127543910395616E-7
power__switching__total,1.7587206002644962E-7
power__leakage__total,6.471078783931716E-9
power__total,3.636185681443749E-7
clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.0
clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.0
timing__hold__ws__corner:nom_tt_025C_1v80,8.398838307003098
timing__setup__ws__corner:nom_tt_025C_1v80,8.875251895733625
timing__hold__ws__corner:nom_tt_025C_1v80,800.2872617780511
timing__setup__ws__corner:nom_tt_025C_1v80,1198.2788576115615
timing__hold__tns__corner:nom_tt_025C_1v80,0.0
timing__setup__tns__corner:nom_tt_025C_1v80,0.0
timing__hold__wns__corner:nom_tt_025C_1v80,0
Expand All @@ -33,8 +33,8 @@ design__max_fanout_violation__count__corner:nom_ss_100C_1v60,0
design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.0
clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.0
timing__hold__ws__corner:nom_ss_100C_1v60,8.966400320454783
timing__setup__ws__corner:nom_ss_100C_1v60,6.2676514641233085
timing__hold__ws__corner:nom_ss_100C_1v60,800.7397354049799
timing__setup__ws__corner:nom_ss_100C_1v60,1196.9690715171275
timing__hold__tns__corner:nom_ss_100C_1v60,0.0
timing__setup__tns__corner:nom_ss_100C_1v60,0.0
timing__hold__wns__corner:nom_ss_100C_1v60,0
Expand All @@ -50,8 +50,8 @@ design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,0
design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.0
clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.0
timing__hold__ws__corner:nom_ff_n40C_1v95,8.171428209813062
timing__setup__ws__corner:nom_ff_n40C_1v95,9.897084321108037
timing__hold__ws__corner:nom_ff_n40C_1v95,800.1120703561674
timing__setup__ws__corner:nom_ff_n40C_1v95,1198.8159142481475
timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
timing__hold__wns__corner:nom_ff_n40C_1v95,0
Expand All @@ -67,8 +67,8 @@ design__max_fanout_violation__count,0
design__max_cap_violation__count,0
clock__skew__worst_hold,0.0
clock__skew__worst_setup,0.0
timing__hold__ws,8.167209362200168
timing__setup__ws,6.212600387756504
timing__hold__ws,800.1070681351661
timing__setup__ws,1196.9168892571374
timing__hold__tns,0.0
timing__setup__tns,0.0
timing__hold__wns,0
Expand All @@ -86,12 +86,12 @@ flow__errors__count,0
design__io,45
design__die__area,17954.7
design__core__area,16493.3
design__instance__count__stdcell,558
design__instance__area__stdcell,2538.68
design__instance__count__stdcell,972
design__instance__area__stdcell,5530.3
design__instance__count__macros,0
design__instance__area__macros,0
design__instance__utilization,0.153922
design__instance__utilization__stdcell,0.153922
design__instance__utilization,0.335306
design__instance__utilization__stdcell,0.335306
design__power_grid_violation__count__net:VPWR,0
design__power_grid_violation__count__net:VGND,0
design__power_grid_violation__count,0
Expand All @@ -100,31 +100,31 @@ timing__drv__floating__pins,0
design__instance__displacement__total,0
design__instance__displacement__mean,0
design__instance__displacement__max,0
route__wirelength__estimated,3531.87
route__wirelength__estimated,7925.89
design__violations,0
design__instance__count__setup_buffer,0
design__instance__count__hold_buffer,0
antenna__violating__nets,0
antenna__violating__pins,0
route__antenna_violation__count,0
route__net,352
route__net,766
route__net__special,2
route__drc_errors__iter:1,71
route__wirelength__iter:1,4112
route__drc_errors__iter:2,17
route__wirelength__iter:2,3947
route__drc_errors__iter:3,14
route__wirelength__iter:3,3922
route__drc_errors__iter:1,196
route__wirelength__iter:1,9097
route__drc_errors__iter:2,22
route__wirelength__iter:2,8903
route__drc_errors__iter:3,24
route__wirelength__iter:3,8836
route__drc_errors__iter:4,0
route__wirelength__iter:4,3924
route__wirelength__iter:4,8830
route__drc_errors,0
route__wirelength,3924
route__vias,1753
route__vias__singlecut,1753
route__wirelength,8830
route__vias,3950
route__vias__singlecut,3950
route__vias__multicut,0
design__disconnected_pin__count,16
design__critical_disconnected_pin__count,0
route__wirelength__max,106.76
route__wirelength__max,158.52
timing__unannotated_net__count__corner:nom_tt_025C_1v80,32
timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
timing__unannotated_net__count__corner:nom_ss_100C_1v60,32
Expand All @@ -136,8 +136,8 @@ design__max_fanout_violation__count__corner:min_tt_025C_1v80,0
design__max_cap_violation__count__corner:min_tt_025C_1v80,0
clock__skew__worst_hold__corner:min_tt_025C_1v80,0.0
clock__skew__worst_setup__corner:min_tt_025C_1v80,0.0
timing__hold__ws__corner:min_tt_025C_1v80,8.392934584880383
timing__setup__ws__corner:min_tt_025C_1v80,8.913450674288422
timing__hold__ws__corner:min_tt_025C_1v80,800.2804405675948
timing__setup__ws__corner:min_tt_025C_1v80,1198.3095530586145
timing__hold__tns__corner:min_tt_025C_1v80,0.0
timing__setup__tns__corner:min_tt_025C_1v80,0.0
timing__hold__wns__corner:min_tt_025C_1v80,0
Expand All @@ -155,8 +155,8 @@ design__max_fanout_violation__count__corner:min_ss_100C_1v60,0
design__max_cap_violation__count__corner:min_ss_100C_1v60,0
clock__skew__worst_hold__corner:min_ss_100C_1v60,0.0
clock__skew__worst_setup__corner:min_ss_100C_1v60,0.0
timing__hold__ws__corner:min_ss_100C_1v60,8.952451477978892
timing__setup__ws__corner:min_ss_100C_1v60,6.328385106180067
timing__hold__ws__corner:min_ss_100C_1v60,800.7296172761365
timing__setup__ws__corner:min_ss_100C_1v60,1197.0207990297538
timing__hold__tns__corner:min_ss_100C_1v60,0.0
timing__setup__tns__corner:min_ss_100C_1v60,0.0
timing__hold__wns__corner:min_ss_100C_1v60,0
Expand All @@ -174,8 +174,8 @@ design__max_fanout_violation__count__corner:min_ff_n40C_1v95,0
design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.0
clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.0
timing__hold__ws__corner:min_ff_n40C_1v95,8.167209362200168
timing__setup__ws__corner:min_ff_n40C_1v95,9.924274127839299
timing__hold__ws__corner:min_ff_n40C_1v95,800.1070681351661
timing__setup__ws__corner:min_ff_n40C_1v95,1198.8364915663572
timing__hold__tns__corner:min_ff_n40C_1v95,0.0
timing__setup__tns__corner:min_ff_n40C_1v95,0.0
timing__hold__wns__corner:min_ff_n40C_1v95,0
Expand All @@ -193,8 +193,8 @@ design__max_fanout_violation__count__corner:max_tt_025C_1v80,0
design__max_cap_violation__count__corner:max_tt_025C_1v80,0
clock__skew__worst_hold__corner:max_tt_025C_1v80,0.0
clock__skew__worst_setup__corner:max_tt_025C_1v80,0.0
timing__hold__ws__corner:max_tt_025C_1v80,8.402687672382946
timing__setup__ws__corner:max_tt_025C_1v80,8.843297899824352
timing__hold__ws__corner:max_tt_025C_1v80,800.2922639990524
timing__setup__ws__corner:max_tt_025C_1v80,1198.249299032918
timing__hold__tns__corner:max_tt_025C_1v80,0.0
timing__setup__tns__corner:max_tt_025C_1v80,0.0
timing__hold__wns__corner:max_tt_025C_1v80,0
Expand All @@ -212,8 +212,8 @@ design__max_fanout_violation__count__corner:max_ss_100C_1v60,0
design__max_cap_violation__count__corner:max_ss_100C_1v60,0
clock__skew__worst_hold__corner:max_ss_100C_1v60,0.0
clock__skew__worst_setup__corner:max_ss_100C_1v60,0.0
timing__hold__ws__corner:max_ss_100C_1v60,8.97613031531778
timing__setup__ws__corner:max_ss_100C_1v60,6.212600387756504
timing__hold__ws__corner:max_ss_100C_1v60,800.7479208575274
timing__setup__ws__corner:max_ss_100C_1v60,1196.9168892571374
timing__hold__tns__corner:max_ss_100C_1v60,0.0
timing__setup__tns__corner:max_ss_100C_1v60,0.0
timing__hold__wns__corner:max_ss_100C_1v60,0
Expand All @@ -231,8 +231,8 @@ design__max_fanout_violation__count__corner:max_ff_n40C_1v95,0
design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.0
clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.0
timing__hold__ws__corner:max_ff_n40C_1v95,8.174297026189828
timing__setup__ws__corner:max_ff_n40C_1v95,9.874988217757817
timing__hold__ws__corner:max_ff_n40C_1v95,800.1157083350773
timing__setup__ws__corner:max_ff_n40C_1v95,1198.795450616779
timing__hold__tns__corner:max_ff_n40C_1v95,0.0
timing__setup__tns__corner:max_ff_n40C_1v95,0.0
timing__hold__wns__corner:max_ff_n40C_1v95,0
Expand All @@ -249,13 +249,13 @@ timing__unannotated_net__count,32
timing__unannotated_net_filtered__count,0
design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.8
design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8
design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.00000405931
design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000486052
design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,5.0682E-7
design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000486052
design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,3.58977E-8
design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,4.1821E-8
design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,6.36015E-9
design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,4.1821E-8
ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
ir__drop__avg,5.120000000000000318881748263832864864752991707064211368560791015625E-7
ir__drop__worst,0.000004060000000000000091563041870745820460797403939068317413330078125
ir__drop__avg,6.10999999999999978703843430023756599922535315272398293018341064453125E-9
ir__drop__worst,3.589999999999999721078691207465372059459696174599230289459228515625E-8
magic__drc_error__count,0
magic__illegal_overlap__count,0
design__lvs_device_difference__count,0
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28 changes: 15 additions & 13 deletions projects/tt_um_tommythorn_cgates/stats/synthesis-stats.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -2,32 +2,34 @@

=== tt_um_tommythorn_cgates ===

Number of wires: 300
Number of wire bits: 335
Number of public wires: 155
Number of public wire bits: 190
Number of wires: 695
Number of wire bits: 730
Number of public wires: 353
Number of public wire bits: 388
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 316
sky130_fd_sc_hd__a211o_1 3
sky130_fd_sc_hd__and2_2 34
Number of cells: 711
sky130_fd_sc_hd__a211o_1 4
sky130_fd_sc_hd__a21oi_2 1
sky130_fd_sc_hd__and2_2 81
sky130_fd_sc_hd__and2b_2 2
sky130_fd_sc_hd__buf_2 8
sky130_fd_sc_hd__conb_1 16
sky130_fd_sc_hd__dlxtn_1 37
sky130_fd_sc_hd__inv_2 45
sky130_fd_sc_hd__dfrtp_2 6
sky130_fd_sc_hd__dlxtn_1 85
sky130_fd_sc_hd__inv_2 99
sky130_fd_sc_hd__nand2_2 1
sky130_fd_sc_hd__nand2b_2 1
sky130_fd_sc_hd__nor2_2 63
sky130_fd_sc_hd__o21a_1 71
sky130_fd_sc_hd__nor2_2 158
sky130_fd_sc_hd__o21a_1 166
sky130_fd_sc_hd__o21ai_2 1
sky130_fd_sc_hd__o22a_2 4
sky130_fd_sc_hd__o2bb2a_2 1
sky130_fd_sc_hd__xor2_2 29
sky130_fd_sc_hd__xor2_2 77

Area for cell type \sky130_fd_sc_hd__a211o_1 is unknown!
Area for cell type \sky130_fd_sc_hd__o21a_1 is unknown!

Chip area for module '\tt_um_tommythorn_cgates': 2038.204800
Chip area for module '\tt_um_tommythorn_cgates': 4855.907200

Binary file modified projects/tt_um_tommythorn_cgates/tt_um_tommythorn_cgates.gds
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26 changes: 13 additions & 13 deletions projects/tt_um_tommythorn_cgates/tt_um_tommythorn_cgates.lef
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Original file line number Diff line number Diff line change
Expand Up @@ -351,7 +351,7 @@ MACRO tt_um_tommythorn_cgates
PIN uo_out[2]
DIRECTION OUTPUT ;
USE SIGNAL ;
ANTENNADIFFAREA 0.795200 ;
ANTENNADIFFAREA 0.445500 ;
PORT
LAYER met4 ;
RECT 88.630 110.520 88.930 111.520 ;
Expand All @@ -360,7 +360,7 @@ MACRO tt_um_tommythorn_cgates
PIN uo_out[3]
DIRECTION OUTPUT ;
USE SIGNAL ;
ANTENNADIFFAREA 0.445500 ;
ANTENNADIFFAREA 0.795200 ;
PORT
LAYER met4 ;
RECT 85.870 110.520 86.170 111.520 ;
Expand All @@ -378,7 +378,7 @@ MACRO tt_um_tommythorn_cgates
PIN uo_out[5]
DIRECTION OUTPUT ;
USE SIGNAL ;
ANTENNADIFFAREA 0.445500 ;
ANTENNADIFFAREA 0.795200 ;
PORT
LAYER met4 ;
RECT 80.350 110.520 80.650 111.520 ;
Expand All @@ -387,7 +387,7 @@ MACRO tt_um_tommythorn_cgates
PIN uo_out[6]
DIRECTION OUTPUT ;
USE SIGNAL ;
ANTENNADIFFAREA 0.795200 ;
ANTENNADIFFAREA 0.445500 ;
PORT
LAYER met4 ;
RECT 77.590 110.520 77.890 111.520 ;
Expand All @@ -396,7 +396,7 @@ MACRO tt_um_tommythorn_cgates
PIN uo_out[7]
DIRECTION OUTPUT ;
USE SIGNAL ;
ANTENNADIFFAREA 0.445500 ;
ANTENNADIFFAREA 0.795200 ;
PORT
LAYER met4 ;
RECT 74.830 110.520 75.130 111.520 ;
Expand All @@ -410,7 +410,7 @@ MACRO tt_um_tommythorn_cgates
LAYER met1 ;
RECT 2.760 2.480 158.240 109.040 ;
LAYER met2 ;
RECT 18.310 2.535 147.560 110.685 ;
RECT 6.080 2.535 145.270 110.685 ;
LAYER met3 ;
RECT 18.290 2.555 145.295 110.665 ;
LAYER met4 ;
Expand Down Expand Up @@ -455,13 +455,13 @@ MACRO tt_um_tommythorn_cgates
RECT 136.250 110.120 137.910 110.665 ;
RECT 139.010 110.120 140.670 110.665 ;
RECT 30.655 109.440 141.385 110.120 ;
RECT 30.655 86.535 56.750 109.440 ;
RECT 59.150 86.535 60.050 109.440 ;
RECT 62.450 86.535 95.620 109.440 ;
RECT 98.020 86.535 98.920 109.440 ;
RECT 101.320 86.535 134.490 109.440 ;
RECT 136.890 86.535 137.790 109.440 ;
RECT 140.190 86.535 141.385 109.440 ;
RECT 30.655 94.015 56.750 109.440 ;
RECT 59.150 94.015 60.050 109.440 ;
RECT 62.450 94.015 95.620 109.440 ;
RECT 98.020 94.015 98.920 109.440 ;
RECT 101.320 94.015 134.490 109.440 ;
RECT 136.890 94.015 137.790 109.440 ;
RECT 140.190 94.015 141.385 109.440 ;
END
END tt_um_tommythorn_cgates
END LIBRARY
Expand Down
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