Skip to content

Commit

Permalink
feat: update project tt_um_idann from arheidar/tt09-chip-tapeout-110
Browse files Browse the repository at this point in the history 
Commit: 124977ae5fda013092afcb849c2eabcf17fbac0e
Workflow: https://github.com/arheidar/tt09-chip-tapeout-110/actions/runs/11767894939
  • Loading branch information
@TinyTapeoutBot @urish
TinyTapeoutBot authored and urish committed Nov 10, 2024
1 parent ba32fe4 commit 9fca9e6
Show file tree
Hide file tree
Showing 8 changed files with 2,368 additions and 2,343 deletions.
4 changes: 2 additions & 2 deletions projects/tt_um_idann/commit_id.json
View file
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
{
"app": "Tiny Tapeout tt09 a48b1c74",
"repo": "https://github.com/arheidar/tt09-chip-tapeout-110",
"commit": "a2fd2f306936b9595db6abdaab07be0927413c81",
"workflow_url": "https://github.com/arheidar/tt09-chip-tapeout-110/actions/runs/11766611744",
"commit": "124977ae5fda013092afcb849c2eabcf17fbac0e",
"workflow_url": "https://github.com/arheidar/tt09-chip-tapeout-110/actions/runs/11767894939",
"sort_id": 1731071060299,
"openlane_version": "OpenLane2 2.1.9",
"pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"
Expand Down
3 changes: 2 additions & 1 deletion projects/tt_um_idann/docs/info.md
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,11 +9,12 @@ You can also include images in this folder and reference them in the markdown. E

## How it works

The circuit takes in a 4-bit number, with each bit of the input representing an input neuron. It then completes the forward pass for the network, while also calculating the loss function (MSE).
The circuit takes in a 4-bit number, with each bit of the input representing an input neuron. It then completes the forward pass for the network, while also calculating the loss function (MSE). Network consists of 4 input neurons, 8 hidden neurons, and 1 output neuron.

## How to test

To physically test the circuit, input a 4 bit-number into ui_in[3:0]. Use ui_in[7] to start the forward pass. The final output calculation can be seen through the output pins {uio_out[1:0], uo_out[7:0]}. The current state can be seen through the output pins uio_out[7:5].

To simulate the circuit, change the input value of ui_un on line 30 of "test.py". Using the .vcd file, analyze the output of the circuit using any waveform viewer.

## External hardware
Expand Down
2 changes: 1 addition & 1 deletion projects/tt_um_idann/info.yaml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@ project:
title: "Forward Pass Network for Simple ANN" # Project title
author: "Arian Heidari" # Your name
discord: "" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
description: "ANN that takes in a 4-bit value, and completes a forward pass" # One line description of what your project does
description: "ANN that takes in a 4-bit value, and completes a forward pass." # One line description of what your project does
language: "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
clock_hz: 50000000 # Clock frequency in Hz (or 0 if not applicable)

Expand Down
144 changes: 72 additions & 72 deletions projects/tt_um_idann/stats/metrics.csv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,21 +3,21 @@ design__lint_error__count,0
design__lint_timing_construct__count,0
design__lint_warning__count,18
design__inferred_latch__count,0
design__instance__count,740
design__instance__area,4742.05
design__instance__count,738
design__instance__area,4626.94
design__instance_unmapped__count,0
synthesis__check_error__count,0
design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
design__max_fanout_violation__count__corner:nom_tt_025C_1v80,3
design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
power__internal__total,0.0003695183841045946
power__switching__total,0.00025278868270106614
power__leakage__total,5.7973239542263855E-9
power__total,0.0006223128875717521
clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.5516365298468481
clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.5950746730476367
timing__hold__ws__corner:nom_tt_025C_1v80,0.33351033989589884
timing__setup__ws__corner:nom_tt_025C_1v80,14.330844472293773
power__internal__total,0.00033429908216930926
power__switching__total,0.00024545806809328496
power__leakage__total,5.5672426668706976E-9
power__total,0.0005797627381980419
clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.5492713106482937
clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.5828624414759794
timing__hold__ws__corner:nom_tt_025C_1v80,0.35050485728138125
timing__setup__ws__corner:nom_tt_025C_1v80,14.482568443308514
timing__hold__tns__corner:nom_tt_025C_1v80,0.0
timing__setup__tns__corner:nom_tt_025C_1v80,0.0
timing__hold__wns__corner:nom_tt_025C_1v80,0
Expand All @@ -31,10 +31,10 @@ timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
design__max_slew_violation__count__corner:nom_ss_100C_1v60,0
design__max_fanout_violation__count__corner:nom_ss_100C_1v60,3
design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
clock__skew__worst_hold__corner:nom_ss_100C_1v60,1.0803591660404084
clock__skew__worst_setup__corner:nom_ss_100C_1v60,1.1576728792158362
timing__hold__ws__corner:nom_ss_100C_1v60,0.9340168902674405
timing__setup__ws__corner:nom_ss_100C_1v60,10.793180876763131
clock__skew__worst_hold__corner:nom_ss_100C_1v60,1.075564112661439
clock__skew__worst_setup__corner:nom_ss_100C_1v60,1.138935977766229
timing__hold__ws__corner:nom_ss_100C_1v60,0.9665056806227996
timing__setup__ws__corner:nom_ss_100C_1v60,10.48747518512692
timing__hold__tns__corner:nom_ss_100C_1v60,0.0
timing__setup__tns__corner:nom_ss_100C_1v60,0.0
timing__hold__wns__corner:nom_ss_100C_1v60,0
Expand All @@ -48,10 +48,10 @@ timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,3
design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.3562621132274306
clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.38633350390060217
timing__hold__ws__corner:nom_ff_n40C_1v95,0.11759649142868943
timing__setup__ws__corner:nom_ff_n40C_1v95,14.94622423685765
clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.3550269068108743
clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.3774830554981632
timing__hold__ws__corner:nom_ff_n40C_1v95,0.12911111434309377
timing__setup__ws__corner:nom_ff_n40C_1v95,14.945520799529355
timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
timing__hold__wns__corner:nom_ff_n40C_1v95,0
Expand All @@ -65,10 +65,10 @@ timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
design__max_slew_violation__count,0
design__max_fanout_violation__count,3
design__max_cap_violation__count,0
clock__skew__worst_hold,1.0840355586681276
clock__skew__worst_setup,0.38179060993323227
timing__hold__ws,0.11573109464995722
timing__setup__ws,10.709684109344092
clock__skew__worst_hold,1.0799856870043618
clock__skew__worst_setup,0.3748084448894712
timing__hold__ws,0.12658163764340058
timing__setup__ws,10.410396395150146
timing__hold__tns,0.0
timing__setup__tns,0.0
timing__hold__wns,0
Expand All @@ -86,12 +86,12 @@ flow__errors__count,0
design__io,45
design__die__area,17954.7
design__core__area,16493.3
design__instance__count__stdcell,740
design__instance__area__stdcell,4742.05
design__instance__count__stdcell,738
design__instance__area__stdcell,4626.94
design__instance__count__macros,0
design__instance__area__macros,0
design__instance__utilization,0.287513
design__instance__utilization__stdcell,0.287513
design__instance__utilization,0.280534
design__instance__utilization__stdcell,0.280534
design__power_grid_violation__count__net:VPWR,0
design__power_grid_violation__count__net:VGND,0
design__power_grid_violation__count,0
Expand All @@ -100,33 +100,33 @@ timing__drv__floating__pins,0
design__instance__displacement__total,0
design__instance__displacement__mean,0
design__instance__displacement__max,0
route__wirelength__estimated,9166.16
route__wirelength__estimated,9084.55
design__violations,0
design__instance__count__setup_buffer,0
design__instance__count__hold_buffer,21
design__instance__count__hold_buffer,19
antenna__violating__nets,0
antenna__violating__pins,0
route__antenna_violation__count,0
route__net,531
route__net,529
route__net__special,2
route__drc_errors__iter:1,195
route__wirelength__iter:1,9970
route__drc_errors__iter:2,70
route__wirelength__iter:2,9835
route__drc_errors__iter:1,253
route__wirelength__iter:1,10244
route__drc_errors__iter:2,96
route__wirelength__iter:2,10094
route__drc_errors__iter:3,54
route__wirelength__iter:3,9811
route__drc_errors__iter:4,1
route__wirelength__iter:4,9801
route__wirelength__iter:3,9992
route__drc_errors__iter:4,7
route__wirelength__iter:4,9985
route__drc_errors__iter:5,0
route__wirelength__iter:5,9799
route__wirelength__iter:5,9991
route__drc_errors,0
route__wirelength,9799
route__vias,3290
route__vias__singlecut,3290
route__wirelength,9991
route__vias,3326
route__vias__singlecut,3326
route__vias__multicut,0
design__disconnected_pin__count,12
design__critical_disconnected_pin__count,0
route__wirelength__max,150.61
route__wirelength__max,171.75
timing__unannotated_net__count__corner:nom_tt_025C_1v80,27
timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
timing__unannotated_net__count__corner:nom_ss_100C_1v60,27
Expand All @@ -136,10 +136,10 @@ timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
design__max_slew_violation__count__corner:min_tt_025C_1v80,0
design__max_fanout_violation__count__corner:min_tt_025C_1v80,3
design__max_cap_violation__count__corner:min_tt_025C_1v80,0
clock__skew__worst_hold__corner:min_tt_025C_1v80,0.5492721988267385
clock__skew__worst_setup__corner:min_tt_025C_1v80,0.5893828925063164
timing__hold__ws__corner:min_tt_025C_1v80,0.33086495590915665
timing__setup__ws__corner:min_tt_025C_1v80,14.333848291794153
clock__skew__worst_hold__corner:min_tt_025C_1v80,0.5468395335775306
clock__skew__worst_setup__corner:min_tt_025C_1v80,0.5791842169802177
timing__hold__ws__corner:min_tt_025C_1v80,0.3476172781349674
timing__setup__ws__corner:min_tt_025C_1v80,14.509995393684541
timing__hold__tns__corner:min_tt_025C_1v80,0.0
timing__setup__tns__corner:min_tt_025C_1v80,0.0
timing__hold__wns__corner:min_tt_025C_1v80,0
Expand All @@ -155,10 +155,10 @@ timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
design__max_slew_violation__count__corner:min_ss_100C_1v60,0
design__max_fanout_violation__count__corner:min_ss_100C_1v60,3
design__max_cap_violation__count__corner:min_ss_100C_1v60,0
clock__skew__worst_hold__corner:min_ss_100C_1v60,1.0764771601027134
clock__skew__worst_setup__corner:min_ss_100C_1v60,1.1490173582264587
timing__hold__ws__corner:min_ss_100C_1v60,0.9289167475926756
timing__setup__ws__corner:min_ss_100C_1v60,10.88117626800518
clock__skew__worst_hold__corner:min_ss_100C_1v60,1.0717560475792751
clock__skew__worst_setup__corner:min_ss_100C_1v60,1.1331165215734658
timing__hold__ws__corner:min_ss_100C_1v60,0.9602577893527167
timing__setup__ws__corner:min_ss_100C_1v60,10.545088656307028
timing__hold__tns__corner:min_ss_100C_1v60,0.0
timing__setup__tns__corner:min_ss_100C_1v60,0.0
timing__hold__wns__corner:min_ss_100C_1v60,0
Expand All @@ -174,10 +174,10 @@ timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
design__max_slew_violation__count__corner:min_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:min_ff_n40C_1v95,3
design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.35441739435311687
clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.38179060993323227
timing__hold__ws__corner:min_ff_n40C_1v95,0.11573109464995722
timing__setup__ws__corner:min_ff_n40C_1v95,14.948640082227561
clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.35322060165429897
clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.3748084448894712
timing__hold__ws__corner:min_ff_n40C_1v95,0.12658163764340058
timing__setup__ws__corner:min_ff_n40C_1v95,14.963692930510362
timing__hold__tns__corner:min_ff_n40C_1v95,0.0
timing__setup__tns__corner:min_ff_n40C_1v95,0.0
timing__hold__wns__corner:min_ff_n40C_1v95,0
Expand All @@ -193,10 +193,10 @@ timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
design__max_slew_violation__count__corner:max_tt_025C_1v80,0
design__max_fanout_violation__count__corner:max_tt_025C_1v80,3
design__max_cap_violation__count__corner:max_tt_025C_1v80,0
clock__skew__worst_hold__corner:max_tt_025C_1v80,0.5545624116886948
clock__skew__worst_setup__corner:max_tt_025C_1v80,0.5997356114814384
timing__hold__ws__corner:max_tt_025C_1v80,0.3362801243760685
timing__setup__ws__corner:max_tt_025C_1v80,14.326659375461784
clock__skew__worst_hold__corner:max_tt_025C_1v80,0.5525687841469917
clock__skew__worst_setup__corner:max_tt_025C_1v80,0.5866832741232874
timing__hold__ws__corner:max_tt_025C_1v80,0.3539905135880755
timing__setup__ws__corner:max_tt_025C_1v80,14.45236504711398
timing__hold__tns__corner:max_tt_025C_1v80,0.0
timing__setup__tns__corner:max_tt_025C_1v80,0.0
timing__hold__wns__corner:max_tt_025C_1v80,0
Expand All @@ -212,10 +212,10 @@ timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
design__max_slew_violation__count__corner:max_ss_100C_1v60,0
design__max_fanout_violation__count__corner:max_ss_100C_1v60,3
design__max_cap_violation__count__corner:max_ss_100C_1v60,0
clock__skew__worst_hold__corner:max_ss_100C_1v60,1.0840355586681276
clock__skew__worst_setup__corner:max_ss_100C_1v60,1.1656240746984718
timing__hold__ws__corner:max_ss_100C_1v60,0.9393460719586633
timing__setup__ws__corner:max_ss_100C_1v60,10.709684109344092
clock__skew__worst_hold__corner:max_ss_100C_1v60,1.0799856870043618
clock__skew__worst_setup__corner:max_ss_100C_1v60,1.1444087112985957
timing__hold__ws__corner:max_ss_100C_1v60,0.9721791424836955
timing__setup__ws__corner:max_ss_100C_1v60,10.410396395150146
timing__hold__tns__corner:max_ss_100C_1v60,0.0
timing__setup__tns__corner:max_ss_100C_1v60,0.0
timing__hold__wns__corner:max_ss_100C_1v60,0
Expand All @@ -231,10 +231,10 @@ timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:max_ff_n40C_1v95,3
design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.35895623600633225
clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.39183882247966323
timing__hold__ws__corner:max_ff_n40C_1v95,0.11951656669293084
timing__setup__ws__corner:max_ff_n40C_1v95,14.94362187401433
clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.35783582665376884
clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.38058196560329133
timing__hold__ws__corner:max_ff_n40C_1v95,0.13163925877511976
timing__setup__ws__corner:max_ff_n40C_1v95,14.926087455156702
timing__hold__tns__corner:max_ff_n40C_1v95,0.0
timing__setup__tns__corner:max_ff_n40C_1v95,0.0
timing__hold__wns__corner:max_ff_n40C_1v95,0
Expand All @@ -249,15 +249,15 @@ timing__unannotated_net__count__corner:max_ff_n40C_1v95,27
timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0
timing__unannotated_net__count,27
timing__unannotated_net_filtered__count,0
design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79992
design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79993
design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.79999
design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000773396
design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000733083
design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.0000109732
design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000733083
design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000685886
design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000678834
design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.0000100674
design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000678834
ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
ir__drop__avg,0.00001099999999999999971398746689832393030883395113050937652587890625
ir__drop__worst,0.000077299999999999995125600504852769745411933399736881256103515625
ir__drop__avg,0.000010099999999999999860593284661813839875321718864142894744873046875
ir__drop__worst,0.000068600000000000000495610497086573786873486824333667755126953125
magic__drc_error__count,0
magic__illegal_overlap__count,0
design__lvs_device_difference__count,0
Expand Down
76 changes: 37 additions & 39 deletions projects/tt_um_idann/stats/synthesis-stats.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2,59 +2,57 @@

=== tt_um_idann ===

Number of wires: 448
Number of wire bits: 483
Number of wires: 447
Number of wire bits: 482
Number of public wires: 57
Number of public wire bits: 92
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 464
sky130_fd_sc_hd__a2111o_2 1
sky130_fd_sc_hd__a211o_2 3
Number of cells: 463
sky130_fd_sc_hd__a211o_2 1
sky130_fd_sc_hd__a21bo_2 5
sky130_fd_sc_hd__a21boi_2 5
sky130_fd_sc_hd__a21o_2 11
sky130_fd_sc_hd__a21oi_2 17
sky130_fd_sc_hd__a21boi_2 3
sky130_fd_sc_hd__a21o_2 12
sky130_fd_sc_hd__a21oi_2 18
sky130_fd_sc_hd__a221o_2 1
sky130_fd_sc_hd__a22o_2 2
sky130_fd_sc_hd__a2bb2o_2 3
sky130_fd_sc_hd__a311oi_2 1
sky130_fd_sc_hd__a31o_2 3
sky130_fd_sc_hd__a32o_2 1
sky130_fd_sc_hd__and2_2 37
sky130_fd_sc_hd__and2b_2 17
sky130_fd_sc_hd__a2bb2o_2 8
sky130_fd_sc_hd__a31o_2 9
sky130_fd_sc_hd__a31oi_2 2
sky130_fd_sc_hd__a32oi_2 1
sky130_fd_sc_hd__a41o_2 1
sky130_fd_sc_hd__and2_2 32
sky130_fd_sc_hd__and2b_2 12
sky130_fd_sc_hd__and3_2 9
sky130_fd_sc_hd__and3b_2 2
sky130_fd_sc_hd__buf_2 10
sky130_fd_sc_hd__conb_1 12
sky130_fd_sc_hd__dfrtp_2 11
sky130_fd_sc_hd__dfxtp_2 38
sky130_fd_sc_hd__dlxtn_1 1
sky130_fd_sc_hd__inv_2 9
sky130_fd_sc_hd__mux2_1 6
sky130_fd_sc_hd__nand2_2 33
sky130_fd_sc_hd__nand2b_2 5
sky130_fd_sc_hd__nand3b_2 2
sky130_fd_sc_hd__nor2_2 38
sky130_fd_sc_hd__nor3_2 1
sky130_fd_sc_hd__inv_2 13
sky130_fd_sc_hd__mux2_1 7
sky130_fd_sc_hd__nand2_2 49
sky130_fd_sc_hd__nand2b_2 8
sky130_fd_sc_hd__nand3_2 4
sky130_fd_sc_hd__nand3b_2 1
sky130_fd_sc_hd__nor2_2 28
sky130_fd_sc_hd__nor3b_2 1
sky130_fd_sc_hd__o211a_2 14
sky130_fd_sc_hd__o21a_2 27
sky130_fd_sc_hd__o21ai_2 12
sky130_fd_sc_hd__o21ba_2 7
sky130_fd_sc_hd__o21bai_2 2
sky130_fd_sc_hd__o221a_2 1
sky130_fd_sc_hd__o22a_2 2
sky130_fd_sc_hd__o2bb2a_2 1
sky130_fd_sc_hd__o311a_2 1
sky130_fd_sc_hd__o31a_2 2
sky130_fd_sc_hd__or2_2 27
sky130_fd_sc_hd__or3_2 2
sky130_fd_sc_hd__or3b_2 3
sky130_fd_sc_hd__o2111a_2 1
sky130_fd_sc_hd__o211a_2 12
sky130_fd_sc_hd__o21a_2 23
sky130_fd_sc_hd__o21ai_2 13
sky130_fd_sc_hd__o21ba_2 4
sky130_fd_sc_hd__o221a_2 4
sky130_fd_sc_hd__o22ai_2 1
sky130_fd_sc_hd__o31a_2 1
sky130_fd_sc_hd__o31ai_2 2
sky130_fd_sc_hd__o41a_2 2
sky130_fd_sc_hd__or2_2 25
sky130_fd_sc_hd__or3_2 3
sky130_fd_sc_hd__or4_2 3
sky130_fd_sc_hd__xnor2_2 54
sky130_fd_sc_hd__xor2_2 21
sky130_fd_sc_hd__or4b_2 1
sky130_fd_sc_hd__xnor2_2 48
sky130_fd_sc_hd__xor2_2 23

Chip area for module '\tt_um_idann': 4972.268800
Chip area for module '\tt_um_idann': 4928.476800

Binary file modified projects/tt_um_idann/tt_um_idann.gds
View file
Binary file not shown.
Loading

0 comments on commit 9fca9e6

Please sign in to comment.