feat: update project tt_um_wokwi_413387224567846913 from aaroneiche/t…

…iny_tapeout

Commit: 4927e4188127463011a362c918fc7a6342f6b47d
Workflow: https://github.com/aaroneiche/tiny_tapeout/actions/runs/11768004890

projects/tt_um_wokwi_413387224567846913/commit_id.json

@@ -1,8 +1,8 @@
 {
-  "app": "Tiny Tapeout tt09 b176ed7c",
+  "app": "Tiny Tapeout tt09 a48b1c74",
   "repo": "https://github.com/aaroneiche/tiny_tapeout",
-  "commit": "fcf0cd88e38aed8536320db74c059f056a6c681d",
-  "workflow_url": "https://github.com/aaroneiche/tiny_tapeout/actions/runs/11637367322",
+  "commit": "4927e4188127463011a362c918fc7a6342f6b47d",
+  "workflow_url": "https://github.com/aaroneiche/tiny_tapeout/actions/runs/11768004890",
   "sort_id": 1730502945819,
   "openlane_version": "OpenLane2 2.1.9",
   "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"

projects/tt_um_wokwi_413387224567846913/docs/info.md

@@ -9,12 +9,12 @@ You can also include images in this folder and reference them in the markdown. E
 
 ## How it works
 
-Right now, if pins 1 and 6 are set, and you get an 'A' on a 7-segment display wired up to the outputs. 
+Pressing the clock button should step through the 5 letters of my name, output on a 7-segment display.
 
 ## How to test
 
-Provide logical HIGH values to input pin 1 and input pin 6. Segments 0,1,2, 4,5,6 are driven HIGH.
+Press the clock button, letters appear. Note that 0 and 1 are the same letter.
 
 ## External hardware
 
-List external hardware used in your project (e.g. PMOD, LED display, etc), if any
+None (Well, the 7-segment display)

projects/tt_um_wokwi_413387224567846913/info.yaml

@@ -4,7 +4,7 @@ project:
   title:        "Speller"      # Project title
   author:       "Aaron Eiche"      # Your name
   discord:      "sir_castor"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
-  description:  "Set the input to 65d to output an 'A' to the 7-segment display"      # One line description of what your project does
+  description:  "Spells 'AAron' on a 7-segment display" # One line description of what your project does
   language:     "Wokwi" # other examples include SystemVerilog, Amaranth, VHDL, etc
   clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
 

projects/tt_um_wokwi_413387224567846913/stats/metrics.csv

@@ -3,21 +3,21 @@ design__lint_error__count,0
 design__lint_timing_construct__count,0
 design__lint_warning__count,0
 design__inferred_latch__count,0
-design__instance__count,260
-design__instance__area,429.162
+design__instance__count,263
+design__instance__area,499.229
 design__instance_unmapped__count,0
 synthesis__check_error__count,0
 design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:nom_tt_025C_1v80,0
 design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
-power__internal__total,0.0000010015957059295033
-power__switching__total,0.000002404719225523877
-power__leakage__total,1.3520662367483283E-9
-power__total,0.0000034076670090144034
+power__internal__total,0.0000023368941128865117
+power__switching__total,0.0
+power__leakage__total,1.4371015488734429E-9
+power__total,0.000002338331114515313
 clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.0
 clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.0
-timing__hold__ws__corner:nom_tt_025C_1v80,8.20244517746305
-timing__setup__ws__corner:nom_tt_025C_1v80,10.979095277011199
+timing__hold__ws__corner:nom_tt_025C_1v80,0.7394272070595975
+timing__setup__ws__corner:nom_tt_025C_1v80,14.745688643050965
 timing__hold__tns__corner:nom_tt_025C_1v80,0.0
 timing__setup__tns__corner:nom_tt_025C_1v80,0.0
 timing__hold__wns__corner:nom_tt_025C_1v80,0
@@ -33,8 +33,8 @@ design__max_fanout_violation__count__corner:nom_ss_100C_1v60,0
 design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
 clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.0
 clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.0
-timing__hold__ws__corner:nom_ss_100C_1v60,8.654934791603916
-timing__setup__ws__corner:nom_ss_100C_1v60,10.307563094808941
+timing__hold__ws__corner:nom_ss_100C_1v60,1.7549666661078545
+timing__setup__ws__corner:nom_ss_100C_1v60,13.727797065436214
 timing__hold__tns__corner:nom_ss_100C_1v60,0.0
 timing__setup__tns__corner:nom_ss_100C_1v60,0.0
 timing__hold__wns__corner:nom_ss_100C_1v60,0
@@ -50,8 +50,8 @@ design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,0
 design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
 clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.0
 clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.0
-timing__hold__ws__corner:nom_ff_n40C_1v95,8.045800697864008
-timing__setup__ws__corner:nom_ff_n40C_1v95,11.273252872507868
+timing__hold__ws__corner:nom_ff_n40C_1v95,0.39736629000869195
+timing__setup__ws__corner:nom_ff_n40C_1v95,15.109245837690496
 timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
 timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
 timing__hold__wns__corner:nom_ff_n40C_1v95,0
@@ -67,8 +67,8 @@ design__max_fanout_violation__count,0
 design__max_cap_violation__count,0
 clock__skew__worst_hold,0.0
 clock__skew__worst_setup,0.0
-timing__hold__ws,8.044050986327713
-timing__setup__ws,10.299900779365483
+timing__hold__ws,0.39539617144020023
+timing__setup__ws,13.720678315200985
 timing__hold__tns,0.0
 timing__setup__tns,0.0
 timing__hold__wns,0
@@ -86,12 +86,12 @@ flow__errors__count,0
 design__io,45
 design__die__area,17954.7
 design__core__area,16493.3
-design__instance__count__stdcell,260
-design__instance__area__stdcell,429.162
+design__instance__count__stdcell,263
+design__instance__area__stdcell,499.229
 design__instance__count__macros,0
 design__instance__area__macros,0
-design__instance__utilization,0.0260203
-design__instance__utilization__stdcell,0.0260203
+design__instance__utilization,0.0302685
+design__instance__utilization__stdcell,0.0302685
 design__power_grid_violation__count__net:VGND,0
 design__power_grid_violation__count__net:VPWR,0
 design__power_grid_violation__count,0
@@ -100,40 +100,40 @@ timing__drv__floating__pins,0
 design__instance__displacement__total,0
 design__instance__displacement__mean,0
 design__instance__displacement__max,0
-route__wirelength__estimated,259.897
+route__wirelength__estimated,270.476
 design__violations,0
 design__instance__count__setup_buffer,0
-design__instance__count__hold_buffer,0
+design__instance__count__hold_buffer,1
 antenna__violating__nets,0
 antenna__violating__pins,0
 route__antenna_violation__count,0
-route__net,54
+route__net,57
 route__net__special,2
-route__drc_errors__iter:1,9
-route__wirelength__iter:1,244
+route__drc_errors__iter:1,11
+route__wirelength__iter:1,227
 route__drc_errors__iter:2,0
-route__wirelength__iter:2,247
+route__wirelength__iter:2,227
 route__drc_errors,0
-route__wirelength,247
-route__vias,165
-route__vias__singlecut,165
+route__wirelength,227
+route__vias,169
+route__vias__singlecut,169
 route__vias__multicut,0
-design__disconnected_pin__count,11
+design__disconnected_pin__count,18
 design__critical_disconnected_pin__count,0
-route__wirelength__max,43.58
-timing__unannotated_net__count__corner:nom_tt_025C_1v80,29
+route__wirelength__max,41.76
+timing__unannotated_net__count__corner:nom_tt_025C_1v80,35
 timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
-timing__unannotated_net__count__corner:nom_ss_100C_1v60,29
+timing__unannotated_net__count__corner:nom_ss_100C_1v60,35
 timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0
-timing__unannotated_net__count__corner:nom_ff_n40C_1v95,29
+timing__unannotated_net__count__corner:nom_ff_n40C_1v95,35
 timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
 design__max_slew_violation__count__corner:min_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:min_tt_025C_1v80,0
 design__max_cap_violation__count__corner:min_tt_025C_1v80,0
 clock__skew__worst_hold__corner:min_tt_025C_1v80,0.0
 clock__skew__worst_setup__corner:min_tt_025C_1v80,0.0
-timing__hold__ws__corner:min_tt_025C_1v80,8.199914757073758
-timing__setup__ws__corner:min_tt_025C_1v80,10.984877318686975
+timing__hold__ws__corner:min_tt_025C_1v80,0.7375480435149706
+timing__setup__ws__corner:min_tt_025C_1v80,14.75028940739513
 timing__hold__tns__corner:min_tt_025C_1v80,0.0
 timing__setup__tns__corner:min_tt_025C_1v80,0.0
 timing__hold__wns__corner:min_tt_025C_1v80,0
@@ -144,15 +144,15 @@ timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
 timing__setup_vio__count__corner:min_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity
 timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
-timing__unannotated_net__count__corner:min_tt_025C_1v80,29
+timing__unannotated_net__count__corner:min_tt_025C_1v80,35
 timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
 design__max_slew_violation__count__corner:min_ss_100C_1v60,0
 design__max_fanout_violation__count__corner:min_ss_100C_1v60,0
 design__max_cap_violation__count__corner:min_ss_100C_1v60,0
 clock__skew__worst_hold__corner:min_ss_100C_1v60,0.0
 clock__skew__worst_setup__corner:min_ss_100C_1v60,0.0
-timing__hold__ws__corner:min_ss_100C_1v60,8.651065886298282
-timing__setup__ws__corner:min_ss_100C_1v60,10.317748725214132
+timing__hold__ws__corner:min_ss_100C_1v60,1.751124184110954
+timing__setup__ws__corner:min_ss_100C_1v60,13.735732939840677
 timing__hold__tns__corner:min_ss_100C_1v60,0.0
 timing__setup__tns__corner:min_ss_100C_1v60,0.0
 timing__hold__wns__corner:min_ss_100C_1v60,0
@@ -163,15 +163,15 @@ timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
 timing__setup_vio__count__corner:min_ss_100C_1v60,0
 timing__setup_r2r__ws__corner:min_ss_100C_1v60,Infinity
 timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
-timing__unannotated_net__count__corner:min_ss_100C_1v60,29
+timing__unannotated_net__count__corner:min_ss_100C_1v60,35
 timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
 design__max_slew_violation__count__corner:min_ff_n40C_1v95,0
 design__max_fanout_violation__count__corner:min_ff_n40C_1v95,0
 design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
 clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.0
 clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.0
-timing__hold__ws__corner:min_ff_n40C_1v95,8.044050986327713
-timing__setup__ws__corner:min_ff_n40C_1v95,11.27723368829755
+timing__hold__ws__corner:min_ff_n40C_1v95,0.39539617144020023
+timing__setup__ws__corner:min_ff_n40C_1v95,15.112949541805394
 timing__hold__tns__corner:min_ff_n40C_1v95,0.0
 timing__setup__tns__corner:min_ff_n40C_1v95,0.0
 timing__hold__wns__corner:min_ff_n40C_1v95,0
@@ -182,15 +182,15 @@ timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
 timing__setup_vio__count__corner:min_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:min_ff_n40C_1v95,Infinity
 timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
-timing__unannotated_net__count__corner:min_ff_n40C_1v95,29
+timing__unannotated_net__count__corner:min_ff_n40C_1v95,35
 timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
 design__max_slew_violation__count__corner:max_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:max_tt_025C_1v80,0
 design__max_cap_violation__count__corner:max_tt_025C_1v80,0
 clock__skew__worst_hold__corner:max_tt_025C_1v80,0.0
 clock__skew__worst_setup__corner:max_tt_025C_1v80,0.0
-timing__hold__ws__corner:max_tt_025C_1v80,8.204811284840048
-timing__setup__ws__corner:max_tt_025C_1v80,10.974501618094592
+timing__hold__ws__corner:max_tt_025C_1v80,0.7414456480866027
+timing__setup__ws__corner:max_tt_025C_1v80,14.74129660064133
 timing__hold__tns__corner:max_tt_025C_1v80,0.0
 timing__setup__tns__corner:max_tt_025C_1v80,0.0
 timing__hold__wns__corner:max_tt_025C_1v80,0
@@ -201,15 +201,15 @@ timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
 timing__setup_vio__count__corner:max_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:max_tt_025C_1v80,Infinity
 timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
-timing__unannotated_net__count__corner:max_tt_025C_1v80,29
+timing__unannotated_net__count__corner:max_tt_025C_1v80,35
 timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
 design__max_slew_violation__count__corner:max_ss_100C_1v60,0
 design__max_fanout_violation__count__corner:max_ss_100C_1v60,0
 design__max_cap_violation__count__corner:max_ss_100C_1v60,0
 clock__skew__worst_hold__corner:max_ss_100C_1v60,0.0
 clock__skew__worst_setup__corner:max_ss_100C_1v60,0.0
-timing__hold__ws__corner:max_ss_100C_1v60,8.658999984345854
-timing__setup__ws__corner:max_ss_100C_1v60,10.299900779365483
+timing__hold__ws__corner:max_ss_100C_1v60,1.7585124965041852
+timing__setup__ws__corner:max_ss_100C_1v60,13.720678315200985
 timing__hold__tns__corner:max_ss_100C_1v60,0.0
 timing__setup__tns__corner:max_ss_100C_1v60,0.0
 timing__hold__wns__corner:max_ss_100C_1v60,0
@@ -220,15 +220,15 @@ timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
 timing__setup_vio__count__corner:max_ss_100C_1v60,0
 timing__setup_r2r__ws__corner:max_ss_100C_1v60,Infinity
 timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
-timing__unannotated_net__count__corner:max_ss_100C_1v60,29
+timing__unannotated_net__count__corner:max_ss_100C_1v60,35
 timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
 design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
 design__max_fanout_violation__count__corner:max_ff_n40C_1v95,0
 design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
 clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.0
 clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.0
-timing__hold__ws__corner:max_ff_n40C_1v95,8.047534422188296
-timing__setup__ws__corner:max_ff_n40C_1v95,11.270073193675415
+timing__hold__ws__corner:max_ff_n40C_1v95,0.3988200438338267
+timing__setup__ws__corner:max_ff_n40C_1v95,15.105961353801554
 timing__hold__tns__corner:max_ff_n40C_1v95,0.0
 timing__setup__tns__corner:max_ff_n40C_1v95,0.0
 timing__hold__wns__corner:max_ff_n40C_1v95,0
@@ -239,19 +239,19 @@ timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
 timing__setup_vio__count__corner:max_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:max_ff_n40C_1v95,Infinity
 timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0
-timing__unannotated_net__count__corner:max_ff_n40C_1v95,29
+timing__unannotated_net__count__corner:max_ff_n40C_1v95,35
 timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0
-timing__unannotated_net__count,29
+timing__unannotated_net__count,35
 timing__unannotated_net_filtered__count,0
 design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.8
 design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8
-design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.00000336338
-design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000240506
-design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,4.77988E-8
-design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000240506
+design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000030371
+design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000250859
+design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,3.65309E-8
+design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000250859
 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
-ir__drop__avg,6.0899999999999996079489707721810187734945429838262498378753662109375E-8
-ir__drop__worst,0.000003360000000000000017360245185837896997327334247529506683349609375
+ir__drop__avg,3.229999999999999806190797914558221481939881414291448891162872314453125E-8
+ir__drop__worst,0.00000304000000000000011654414412698432812476312392391264438629150390625
 magic__drc_error__count,0
 magic__illegal_overlap__count,0
 design__lvs_device_difference__count,0

projects/tt_um_wokwi_413387224567846913/stats/synthesis-stats.txt

@@ -2,19 +2,22 @@
 
 === tt_um_wokwi_413387224567846913 ===
 
-   Number of wires:                 11
-   Number of wire bits:             46
-   Number of public wires:           9
-   Number of public wire bits:      44
+   Number of wires:                 21
+   Number of wire bits:             56
+   Number of public wires:          18
+   Number of public wire bits:      53
    Number of memories:               0
    Number of memory bits:            0
    Number of processes:              0
-   Number of cells:                 27
-     sky130_fd_sc_hd__a22oi_2        1
-     sky130_fd_sc_hd__and4_2         1
-     sky130_fd_sc_hd__buf_2          6
-     sky130_fd_sc_hd__conb_1        18
-     sky130_fd_sc_hd__nand2_2        1
+   Number of cells:                 37
+     sky130_fd_sc_hd__and3_2         1
+     sky130_fd_sc_hd__buf_2          7
+     sky130_fd_sc_hd__conb_1        17
+     sky130_fd_sc_hd__dfxtp_2        3
+     sky130_fd_sc_hd__inv_2          6
+     sky130_fd_sc_hd__mux2_1         1
+     sky130_fd_sc_hd__nor2_2         1
+     sky130_fd_sc_hd__o21ai_2        1
 
-   Chip area for module '\tt_um_wokwi_413387224567846913': 126.371200
+   Chip area for module '\tt_um_wokwi_413387224567846913': 218.960000