feat: update project tt_um_toivoh_pio_ram_emu_example from toivoh/tt0…

…9-pio-ram-emulator-example

Commit: b08d5dd9c3b6eccac9b9081b33e04b702a22e379
Workflow: https://github.com/toivoh/tt09-pio-ram-emulator-example/actions/runs/11617414988

projects/tt_um_toivoh_pio_ram_emu_example/commit_id.json

@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout tt09 b176ed7c",
   "repo": "https://github.com/toivoh/tt09-pio-ram-emulator-example",
-  "commit": "49138980a3e00d32d13e5b10ad0802ee90978f0b",
-  "workflow_url": "https://github.com/toivoh/tt09-pio-ram-emulator-example/actions/runs/11530054565",
+  "commit": "b08d5dd9c3b6eccac9b9081b33e04b702a22e379",
+  "workflow_url": "https://github.com/toivoh/tt09-pio-ram-emulator-example/actions/runs/11617414988",
   "sort_id": 1729929406809,
   "openlane_version": "OpenLane2 2.1.9",
   "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"

projects/tt_um_toivoh_pio_ram_emu_example/stats/metrics.csv

@@ -3,21 +3,21 @@ design__lint_error__count,0
 design__lint_timing_construct__count,0
 design__lint_warning__count,31
 design__inferred_latch__count,0
-design__instance__count,2485
-design__instance__area,19205.9
+design__instance__count,2498
+design__instance__area,19297.3
 design__instance_unmapped__count,0
 synthesis__check_error__count,0
 design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:nom_tt_025C_1v80,11
 design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
-power__internal__total,0.0021556674037128687
-power__switching__total,0.002024804474785924
-power__leakage__total,2.1620758516860406E-8
-power__total,0.004180493298918009
-clock__skew__worst_hold__corner:nom_tt_025C_1v80,-0.03098216215718116
-clock__skew__worst_setup__corner:nom_tt_025C_1v80,-0.03098216215718116
-timing__hold__ws__corner:nom_tt_025C_1v80,0.3267092244769989
-timing__setup__ws__corner:nom_tt_025C_1v80,12.315987689402666
+power__internal__total,0.0022639241069555283
+power__switching__total,0.0022566935513168573
+power__leakage__total,2.164625101386264E-8
+power__total,0.004520638845860958
+clock__skew__worst_hold__corner:nom_tt_025C_1v80,-0.020792590460141938
+clock__skew__worst_setup__corner:nom_tt_025C_1v80,-0.020792590460141938
+timing__hold__ws__corner:nom_tt_025C_1v80,0.30890457732753546
+timing__setup__ws__corner:nom_tt_025C_1v80,12.612943935178961
 timing__hold__tns__corner:nom_tt_025C_1v80,0.0
 timing__setup__tns__corner:nom_tt_025C_1v80,0.0
 timing__hold__wns__corner:nom_tt_025C_1v80,0
@@ -28,13 +28,13 @@ timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80,0
 timing__setup_vio__count__corner:nom_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:nom_tt_025C_1v80,Infinity
 timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
-design__max_slew_violation__count__corner:nom_ss_100C_1v60,7
+design__max_slew_violation__count__corner:nom_ss_100C_1v60,0
 design__max_fanout_violation__count__corner:nom_ss_100C_1v60,11
 design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
-clock__skew__worst_hold__corner:nom_ss_100C_1v60,-0.0421775959429785
-clock__skew__worst_setup__corner:nom_ss_100C_1v60,-0.0421775959429785
-timing__hold__ws__corner:nom_ss_100C_1v60,0.8770601160249707
-timing__setup__ws__corner:nom_ss_100C_1v60,4.825588953902318
+clock__skew__worst_hold__corner:nom_ss_100C_1v60,-0.028805070255470095
+clock__skew__worst_setup__corner:nom_ss_100C_1v60,-0.028805070255470095
+timing__hold__ws__corner:nom_ss_100C_1v60,0.8498284538844983
+timing__setup__ws__corner:nom_ss_100C_1v60,5.409758127915238
 timing__hold__tns__corner:nom_ss_100C_1v60,0.0
 timing__setup__tns__corner:nom_ss_100C_1v60,0.0
 timing__hold__wns__corner:nom_ss_100C_1v60,0
@@ -48,10 +48,10 @@ timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
 design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0
 design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,11
 design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
-clock__skew__worst_hold__corner:nom_ff_n40C_1v95,-0.024028307801348677
-clock__skew__worst_setup__corner:nom_ff_n40C_1v95,-0.024028307801348677
-timing__hold__ws__corner:nom_ff_n40C_1v95,0.11262113782542164
-timing__setup__ws__corner:nom_ff_n40C_1v95,14.73073082986176
+clock__skew__worst_hold__corner:nom_ff_n40C_1v95,-0.01605099432132009
+clock__skew__worst_setup__corner:nom_ff_n40C_1v95,-0.01605099432132009
+timing__hold__ws__corner:nom_ff_n40C_1v95,0.11105894296328969
+timing__setup__ws__corner:nom_ff_n40C_1v95,14.760971529550973
 timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
 timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
 timing__hold__wns__corner:nom_ff_n40C_1v95,0
@@ -62,13 +62,13 @@ timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95,0
 timing__setup_vio__count__corner:nom_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:nom_ff_n40C_1v95,Infinity
 timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
-design__max_slew_violation__count,7
+design__max_slew_violation__count,4
 design__max_fanout_violation__count,11
 design__max_cap_violation__count,0
-clock__skew__worst_hold,0.04897593580423837
-clock__skew__worst_setup,-0.0421775959429785
-timing__hold__ws,0.11040285664833208
-timing__setup__ws,4.636897219657299
+clock__skew__worst_hold,-0.014275414587820253
+clock__skew__worst_setup,-0.035608628165093276
+timing__hold__ws,0.1094076527009118
+timing__setup__ws,5.231067282958887
 timing__hold__tns,0.0
 timing__setup__tns,0.0
 timing__hold__wns,0
@@ -86,12 +86,12 @@ flow__errors__count,0
 design__io,45
 design__die__area,36347.4
 design__core__area,34255.4
-design__instance__count__stdcell,2485
-design__instance__area__stdcell,19205.9
+design__instance__count__stdcell,2498
+design__instance__area__stdcell,19297.3
 design__instance__count__macros,0
 design__instance__area__macros,0
-design__instance__utilization,0.560669
-design__instance__utilization__stdcell,0.560669
+design__instance__utilization,0.563336
+design__instance__utilization__stdcell,0.563336
 design__power_grid_violation__count__net:VGND,0
 design__power_grid_violation__count__net:VPWR,0
 design__power_grid_violation__count,0
@@ -100,46 +100,46 @@ timing__drv__floating__pins,0
 design__instance__displacement__total,0
 design__instance__displacement__mean,0
 design__instance__displacement__max,0
-route__wirelength__estimated,39826.5
+route__wirelength__estimated,41035.7
 design__violations,0
 design__instance__count__setup_buffer,0
-design__instance__count__hold_buffer,164
-antenna__violating__nets,1
-antenna__violating__pins,1
-route__antenna_violation__count,1
-route__net,2040
+design__instance__count__hold_buffer,158
+antenna__violating__nets,0
+antenna__violating__pins,0
+route__antenna_violation__count,0
+route__net,2054
 route__net__special,2
-route__drc_errors__iter:1,714
-route__wirelength__iter:1,44291
-route__drc_errors__iter:2,223
-route__wirelength__iter:2,43851
-route__drc_errors__iter:3,283
-route__wirelength__iter:3,43842
-route__drc_errors__iter:4,30
-route__wirelength__iter:4,43804
+route__drc_errors__iter:1,809
+route__wirelength__iter:1,45871
+route__drc_errors__iter:2,268
+route__wirelength__iter:2,45550
+route__drc_errors__iter:3,263
+route__wirelength__iter:3,45320
+route__drc_errors__iter:4,14
+route__wirelength__iter:4,45291
 route__drc_errors__iter:5,0
-route__wirelength__iter:5,43791
+route__wirelength__iter:5,45275
 route__drc_errors,0
-route__wirelength,43791
-route__vias,14154
-route__vias__singlecut,14154
+route__wirelength,45275
+route__vias,14173
+route__vias__singlecut,14173
 route__vias__multicut,0
 design__disconnected_pin__count,15
 design__critical_disconnected_pin__count,0
-route__wirelength__max,243.63
-timing__unannotated_net__count__corner:nom_tt_025C_1v80,37
+route__wirelength__max,291.36
+timing__unannotated_net__count__corner:nom_tt_025C_1v80,36
 timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
-timing__unannotated_net__count__corner:nom_ss_100C_1v60,37
+timing__unannotated_net__count__corner:nom_ss_100C_1v60,36
 timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0
-timing__unannotated_net__count__corner:nom_ff_n40C_1v95,37
+timing__unannotated_net__count__corner:nom_ff_n40C_1v95,36
 timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
 design__max_slew_violation__count__corner:min_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:min_tt_025C_1v80,11
 design__max_cap_violation__count__corner:min_tt_025C_1v80,0
-clock__skew__worst_hold__corner:min_tt_025C_1v80,-0.02776046138205673
-clock__skew__worst_setup__corner:min_tt_025C_1v80,-0.02776046138205673
-timing__hold__ws__corner:min_tt_025C_1v80,0.32293574284303034
-timing__setup__ws__corner:min_tt_025C_1v80,12.402748512606417
+clock__skew__worst_hold__corner:min_tt_025C_1v80,-0.01848160565787433
+clock__skew__worst_setup__corner:min_tt_025C_1v80,-0.01848160565787433
+timing__hold__ws__corner:min_tt_025C_1v80,0.30431991121768265
+timing__setup__ws__corner:min_tt_025C_1v80,12.696369648322413
 timing__hold__tns__corner:min_tt_025C_1v80,0.0
 timing__setup__tns__corner:min_tt_025C_1v80,0.0
 timing__hold__wns__corner:min_tt_025C_1v80,0
@@ -150,15 +150,15 @@ timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
 timing__setup_vio__count__corner:min_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity
 timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
-timing__unannotated_net__count__corner:min_tt_025C_1v80,37
+timing__unannotated_net__count__corner:min_tt_025C_1v80,36
 timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
-design__max_slew_violation__count__corner:min_ss_100C_1v60,7
+design__max_slew_violation__count__corner:min_ss_100C_1v60,0
 design__max_fanout_violation__count__corner:min_ss_100C_1v60,11
 design__max_cap_violation__count__corner:min_ss_100C_1v60,0
-clock__skew__worst_hold__corner:min_ss_100C_1v60,-0.03748157446060645
-clock__skew__worst_setup__corner:min_ss_100C_1v60,-0.03748157446060645
-timing__hold__ws__corner:min_ss_100C_1v60,0.8682380615771895
-timing__setup__ws__corner:min_ss_100C_1v60,4.992687293796884
+clock__skew__worst_hold__corner:min_ss_100C_1v60,-0.02519640123416836
+clock__skew__worst_setup__corner:min_ss_100C_1v60,-0.02519640123416836
+timing__hold__ws__corner:min_ss_100C_1v60,0.8394716270840691
+timing__setup__ws__corner:min_ss_100C_1v60,5.562272577745867
 timing__hold__tns__corner:min_ss_100C_1v60,0.0
 timing__setup__tns__corner:min_ss_100C_1v60,0.0
 timing__hold__wns__corner:min_ss_100C_1v60,0
@@ -169,15 +169,15 @@ timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
 timing__setup_vio__count__corner:min_ss_100C_1v60,0
 timing__setup_r2r__ws__corner:min_ss_100C_1v60,Infinity
 timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
-timing__unannotated_net__count__corner:min_ss_100C_1v60,37
+timing__unannotated_net__count__corner:min_ss_100C_1v60,36
 timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
 design__max_slew_violation__count__corner:min_ff_n40C_1v95,0
 design__max_fanout_violation__count__corner:min_ff_n40C_1v95,11
 design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
-clock__skew__worst_hold__corner:min_ff_n40C_1v95,-0.021462027207348255
-clock__skew__worst_setup__corner:min_ff_n40C_1v95,-0.021462027207348255
-timing__hold__ws__corner:min_ff_n40C_1v95,0.11040285664833208
-timing__setup__ws__corner:min_ff_n40C_1v95,14.76535291381927
+clock__skew__worst_hold__corner:min_ff_n40C_1v95,-0.014275414587820253
+clock__skew__worst_setup__corner:min_ff_n40C_1v95,-0.014275414587820253
+timing__hold__ws__corner:min_ff_n40C_1v95,0.1094076527009118
+timing__setup__ws__corner:min_ff_n40C_1v95,14.793889199072876
 timing__hold__tns__corner:min_ff_n40C_1v95,0.0
 timing__setup__tns__corner:min_ff_n40C_1v95,0.0
 timing__hold__wns__corner:min_ff_n40C_1v95,0
@@ -188,15 +188,15 @@ timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
 timing__setup_vio__count__corner:min_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:min_ff_n40C_1v95,Infinity
 timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
-timing__unannotated_net__count__corner:min_ff_n40C_1v95,37
+timing__unannotated_net__count__corner:min_ff_n40C_1v95,36
 timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
 design__max_slew_violation__count__corner:max_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:max_tt_025C_1v80,11
 design__max_cap_violation__count__corner:max_tt_025C_1v80,0
-clock__skew__worst_hold__corner:max_tt_025C_1v80,0.03591765875273767
-clock__skew__worst_setup__corner:max_tt_025C_1v80,0.03591765875273767
-timing__hold__ws__corner:max_tt_025C_1v80,0.33152759254014486
-timing__setup__ws__corner:max_tt_025C_1v80,12.214663404239209
+clock__skew__worst_hold__corner:max_tt_025C_1v80,-0.025609570744467843
+clock__skew__worst_setup__corner:max_tt_025C_1v80,-0.025609570744467843
+timing__hold__ws__corner:max_tt_025C_1v80,0.3142872717700586
+timing__setup__ws__corner:max_tt_025C_1v80,12.51565286833343
 timing__hold__tns__corner:max_tt_025C_1v80,0.0
 timing__setup__tns__corner:max_tt_025C_1v80,0.0
 timing__hold__wns__corner:max_tt_025C_1v80,0
@@ -207,15 +207,15 @@ timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
 timing__setup_vio__count__corner:max_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:max_tt_025C_1v80,Infinity
 timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
-timing__unannotated_net__count__corner:max_tt_025C_1v80,37
+timing__unannotated_net__count__corner:max_tt_025C_1v80,36
 timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
-design__max_slew_violation__count__corner:max_ss_100C_1v60,7
+design__max_slew_violation__count__corner:max_ss_100C_1v60,4
 design__max_fanout_violation__count__corner:max_ss_100C_1v60,11
 design__max_cap_violation__count__corner:max_ss_100C_1v60,0
-clock__skew__worst_hold__corner:max_ss_100C_1v60,0.04897593580423837
-clock__skew__worst_setup__corner:max_ss_100C_1v60,0.04897593580423837
-timing__hold__ws__corner:max_ss_100C_1v60,0.8866878593445088
-timing__setup__ws__corner:max_ss_100C_1v60,4.636897219657299
+clock__skew__worst_hold__corner:max_ss_100C_1v60,-0.035608628165093276
+clock__skew__worst_setup__corner:max_ss_100C_1v60,-0.035608628165093276
+timing__hold__ws__corner:max_ss_100C_1v60,0.8613701107303169
+timing__setup__ws__corner:max_ss_100C_1v60,5.231067282958887
 timing__hold__tns__corner:max_ss_100C_1v60,0.0
 timing__setup__tns__corner:max_ss_100C_1v60,0.0
 timing__hold__wns__corner:max_ss_100C_1v60,0
@@ -226,15 +226,15 @@ timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
 timing__setup_vio__count__corner:max_ss_100C_1v60,0
 timing__setup_r2r__ws__corner:max_ss_100C_1v60,Infinity
 timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
-timing__unannotated_net__count__corner:max_ss_100C_1v60,37
+timing__unannotated_net__count__corner:max_ss_100C_1v60,36
 timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
 design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
 design__max_fanout_violation__count__corner:max_ff_n40C_1v95,11
 design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
-clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.02819664026519232
-clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.02819664026519232
-timing__hold__ws__corner:max_ff_n40C_1v95,0.11545065230600546
-timing__setup__ws__corner:max_ff_n40C_1v95,14.695861832296588
+clock__skew__worst_hold__corner:max_ff_n40C_1v95,-0.01996633470627217
+clock__skew__worst_setup__corner:max_ff_n40C_1v95,-0.01996633470627217
+timing__hold__ws__corner:max_ff_n40C_1v95,0.1130376380048892
+timing__setup__ws__corner:max_ff_n40C_1v95,14.717235846571171
 timing__hold__tns__corner:max_ff_n40C_1v95,0.0
 timing__setup__tns__corner:max_ff_n40C_1v95,0.0
 timing__hold__wns__corner:max_ff_n40C_1v95,0
@@ -245,19 +245,19 @@ timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
 timing__setup_vio__count__corner:max_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:max_ff_n40C_1v95,Infinity
 timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0
-timing__unannotated_net__count__corner:max_ff_n40C_1v95,37
+timing__unannotated_net__count__corner:max_ff_n40C_1v95,36
 timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0
-timing__unannotated_net__count,37
+timing__unannotated_net__count,36
 timing__unannotated_net_filtered__count,0
-design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79985
-design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.79997
-design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.000146118
-design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.000141333
-design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.0000350351
-design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.000141333
+design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.7998
+design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.79996
+design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.000198965
+design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.000233919
+design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.0000380629
+design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.000233919
 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
-ir__drop__avg,0.000034100000000000002162679757500285404603346250951290130615234375
-ir__drop__worst,0.00014599999999999999805190553647804563297540880739688873291015625
+ir__drop__avg,0.0000374999999999999967148674173689215649574180133640766143798828125
+ir__drop__worst,0.0001990000000000000123824561715224490399123169481754302978515625
 magic__drc_error__count,0
 magic__illegal_overlap__count,0
 design__lvs_device_difference__count,0