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feat: update project tt_um_wokwi_413471588783557633 from ajb497stanfo…
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…rd/tt_test_ex

Commit: 46e39a3b343a2402df13fb19cc75f05f55a3c112
Workflow: https://github.com/ajb497stanford/tt_test_ex/actions/runs/11768040368
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@TinyTapeoutBot @urish
TinyTapeoutBot authored and urish committed Nov 10, 2024
1 parent c1fa6a0 commit 41e6215
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Showing 8 changed files with 680 additions and 386 deletions.
4 changes: 2 additions & 2 deletions projects/tt_um_wokwi_413471588783557633/commit_id.json
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
{
"app": "Tiny Tapeout tt09 a48b1c74",
"repo": "https://github.com/ajb497stanford/tt_test_ex",
"commit": "322d1f483d913c67e948b52c6fb898dd223326f5",
"workflow_url": "https://github.com/ajb497stanford/tt_test_ex/actions/runs/11753108084",
"commit": "46e39a3b343a2402df13fb19cc75f05f55a3c112",
"workflow_url": "https://github.com/ajb497stanford/tt_test_ex/actions/runs/11768040368",
"sort_id": 1731120302924,
"openlane_version": "OpenLane2 2.1.9",
"pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"
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32 changes: 16 additions & 16 deletions projects/tt_um_wokwi_413471588783557633/info.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@ project:
title: "TT Test" # Project title
author: "Austin" # Your name
discord: "" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
description: "This is a test proj." # One line description of what your project does
description: "8-bit shift register." # One line description of what your project does
language: "Wokwi" # other examples include SystemVerilog, Amaranth, VHDL, etc
clock_hz: 0 # Clock frequency in Hz (or 0 if not applicable)

Expand All @@ -15,24 +15,24 @@ project:
# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
pinout:
# Inputs
ui[0]: "input0"
ui[1]: "input1"
ui[2]: "input2"
ui[3]: "input3"
ui[4]: "input4"
ui[5]: "input5"
ui[6]: "input6"
ui[0]: "input"
ui[1]: "set"
ui[2]: ""
ui[3]: ""
ui[4]: ""
ui[5]: ""
ui[6]: ""
ui[7]: ""

# Outputs
uo[0]: ""
uo[1]: ""
uo[2]: ""
uo[3]: ""
uo[4]: ""
uo[5]: ""
uo[6]: ""
uo[7]: ""
uo[0]: "output0"
uo[1]: "output1"
uo[2]: "output2"
uo[3]: "output3"
uo[4]: "output4"
uo[5]: "output5"
uo[6]: "output6"
uo[7]: "output7"

# Bidirectional pins
uio[0]: ""
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164 changes: 85 additions & 79 deletions projects/tt_um_wokwi_413471588783557633/stats/metrics.csv
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Original file line number Diff line number Diff line change
Expand Up @@ -3,21 +3,21 @@ design__lint_error__count,0
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power__switching__total,0.0000031227491490426473
power__leakage__total,1.373262170645262E-9
power__total,0.000004139742486586329
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clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.0
timing__hold__ws__corner:nom_tt_025C_1v80,7.933451453665008
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power__internal__total,0.000059039964980911463
power__switching__total,0.000023195001631393097
power__leakage__total,2.1396155958086638E-9
power__total,0.00008223710756283253
clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.005978856468031849
clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.005978856468031849
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Expand All @@ -31,10 +31,10 @@ timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
design__max_slew_violation__count__corner:nom_ss_100C_1v60,0
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timing__setup__tns__corner:nom_ss_100C_1v60,0.0
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Expand All @@ -48,10 +48,10 @@ timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,0
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clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.0
timing__hold__ws__corner:nom_ff_n40C_1v95,7.8696145161220485
timing__setup__ws__corner:nom_ff_n40C_1v95,11.51065764173746
clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.003995220933833038
clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.003995220933833038
timing__hold__ws__corner:nom_ff_n40C_1v95,0.4264163032258974
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timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
timing__hold__wns__corner:nom_ff_n40C_1v95,0
Expand All @@ -65,10 +65,10 @@ timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
design__max_slew_violation__count,0
design__max_fanout_violation__count,0
design__max_cap_violation__count,0
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timing__hold__ws,7.868541596560706
timing__setup__ws,11.060422224489544
clock__skew__worst_hold,0.010124235070192188
clock__skew__worst_setup,0.003477995767607666
timing__hold__ws,0.4252643912941193
timing__setup__ws,13.574311836565396
timing__hold__tns,0.0
timing__setup__tns,0.0
timing__hold__wns,0
Expand All @@ -86,12 +86,12 @@ flow__errors__count,0
design__io,45
design__die__area,17954.7
design__core__area,16493.3
design__instance__count__stdcell,257
design__instance__area__stdcell,416.65
design__instance__count__stdcell,296
design__instance__area__stdcell,942.154
design__instance__count__macros,0
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design__instance__utilization,0.0252617
design__instance__utilization__stdcell,0.0252617
design__instance__utilization,0.0571234
design__instance__utilization__stdcell,0.0571234
design__power_grid_violation__count__net:VGND,0
design__power_grid_violation__count__net:VPWR,0
design__power_grid_violation__count,0
Expand All @@ -100,40 +100,46 @@ timing__drv__floating__pins,0
design__instance__displacement__total,0
design__instance__displacement__mean,0
design__instance__displacement__max,0
route__wirelength__estimated,502.927
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route__vias,361
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clock__skew__worst_hold__corner:min_tt_025C_1v80,0.005157208139844585
clock__skew__worst_setup__corner:min_tt_025C_1v80,0.005157208139844585
timing__hold__ws__corner:min_tt_025C_1v80,0.7621047897354105
timing__setup__ws__corner:min_tt_025C_1v80,14.633246140115256
timing__hold__tns__corner:min_tt_025C_1v80,0.0
timing__setup__tns__corner:min_tt_025C_1v80,0.0
timing__hold__wns__corner:min_tt_025C_1v80,0
Expand All @@ -144,15 +150,15 @@ timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
timing__setup_vio__count__corner:min_tt_025C_1v80,0
timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity
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timing__unannotated_net__count__corner:min_tt_025C_1v80,39
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timing__hold__ws__corner:min_ss_100C_1v60,8.104237510462465
timing__setup__ws__corner:min_ss_100C_1v60,11.078070330188108
clock__skew__worst_hold__corner:min_ss_100C_1v60,0.008082146292093691
clock__skew__worst_setup__corner:min_ss_100C_1v60,0.008082146292093691
timing__hold__ws__corner:min_ss_100C_1v60,1.7071038399395861
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timing__hold__wns__corner:min_ss_100C_1v60,0
Expand All @@ -163,15 +169,15 @@ timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
timing__setup_vio__count__corner:min_ss_100C_1v60,0
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timing__hold__ws__corner:min_ff_n40C_1v95,7.868541596560706
timing__setup__ws__corner:min_ff_n40C_1v95,11.514052259753559
clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.003477995767607666
clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.003477995767607666
timing__hold__ws__corner:min_ff_n40C_1v95,0.4252643912941193
timing__setup__ws__corner:min_ff_n40C_1v95,15.024893754429096
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timing__hold__wns__corner:min_ff_n40C_1v95,0
Expand All @@ -182,15 +188,15 @@ timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
timing__setup_vio__count__corner:min_ff_n40C_1v95,0
timing__setup_r2r__ws__corner:min_ff_n40C_1v95,Infinity
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timing__hold__ws__corner:max_tt_025C_1v80,7.9349116190282905
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clock__skew__worst_hold__corner:max_tt_025C_1v80,0.006657730111214374
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timing__setup__tns__corner:max_tt_025C_1v80,0.0
timing__hold__wns__corner:max_tt_025C_1v80,0
Expand All @@ -201,15 +207,15 @@ timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
timing__setup_vio__count__corner:max_tt_025C_1v80,0
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clock__skew__worst_hold__corner:max_ss_100C_1v60,0.0
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Expand All @@ -220,15 +226,15 @@ timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
timing__setup_vio__count__corner:max_ss_100C_1v60,0
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timing__setup__ws__corner:max_ff_n40C_1v95,11.508950562766517
clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.00449748584437848
clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.00449748584437848
timing__hold__ws__corner:max_ff_n40C_1v95,0.4274159480655418
timing__setup__ws__corner:max_ff_n40C_1v95,15.014699242239457
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timing__setup__tns__corner:max_ff_n40C_1v95,0.0
timing__hold__wns__corner:max_ff_n40C_1v95,0
Expand All @@ -239,19 +245,19 @@ timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
timing__setup_vio__count__corner:max_ff_n40C_1v95,0
timing__setup_r2r__ws__corner:max_ff_n40C_1v95,Infinity
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design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.8
design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79995
design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8
design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.00000406459
design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000416345
design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,8.3193E-8
design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000416345
design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000470844
design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.00004193
design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.0000013838
design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.00004193
ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
ir__drop__avg,7.10000000000000004928850838754883501025005898554809391498565673828125E-8
ir__drop__worst,0.000004060000000000000091563041870745820460797403939068317413330078125
ir__drop__avg,0.000001430000000000000072932653839841155019030338735319674015045166015625
ir__drop__worst,0.0000470999999999999996685810799146310046126018278300762176513671875
magic__drc_error__count,0
magic__illegal_overlap__count,0
design__lvs_device_difference__count,0
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16 changes: 9 additions & 7 deletions projects/tt_um_wokwi_413471588783557633/stats/synthesis-stats.txt
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=== tt_um_wokwi_413471588783557633 ===

Number of wires: 12
Number of wire bits: 47
Number of public wires: 12
Number of public wire bits: 47
Number of wires: 48
Number of wire bits: 83
Number of public wires: 16
Number of public wire bits: 51
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 28
Number of cells: 56
sky130_fd_sc_hd__buf_2 8
sky130_fd_sc_hd__conb_1 16
sky130_fd_sc_hd__inv_2 4
sky130_fd_sc_hd__dfbbn_2 8
sky130_fd_sc_hd__inv_2 16
sky130_fd_sc_hd__nand2b_2 8

Chip area for module '\tt_um_wokwi_413471588783557633': 115.110400
Chip area for module '\tt_um_wokwi_413471588783557633': 510.489600

Binary file modified projects/tt_um_wokwi_413471588783557633/tt_um_wokwi_413471588783557633.gds
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