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feat: update project tt_um_senolgulgonul from senolgulgonul/tt09-seno…
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…lgulgonul

Commit: 288ca74f0aea9d18a309147f2a8742d7b9beddf3
Workflow: https://github.com/senolgulgonul/tt09-senolgulgonul/actions/runs/11704449707
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@TinyTapeoutBot @urish
TinyTapeoutBot authored and urish committed Nov 6, 2024
1 parent 6c8c913 commit 04f4cf0
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6 changes: 3 additions & 3 deletions projects/tt_um_senolgulgonul/commit_id.json
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
{
"app": "Tiny Tapeout tt09 b176ed7c",
"app": "Tiny Tapeout tt09 a48b1c74",
"repo": "https://github.com/senolgulgonul/tt09-senolgulgonul",
"commit": "cbb0a2aae60ae2222efc5d3d42e4993417718c72",
"workflow_url": "https://github.com/senolgulgonul/tt09-senolgulgonul/actions/runs/11669642412",
"commit": "288ca74f0aea9d18a309147f2a8742d7b9beddf3",
"workflow_url": "https://github.com/senolgulgonul/tt09-senolgulgonul/actions/runs/11704449707",
"sort_id": 1730725111692,
"openlane_version": "OpenLane2 2.1.9",
"pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"
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2 changes: 1 addition & 1 deletion projects/tt_um_senolgulgonul/info.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,7 @@ project:
# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
pinout:
# Inputs
ui[0]: "btn"
ui[0]: ""
ui[1]: ""
ui[2]: ""
ui[3]: ""
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166 changes: 84 additions & 82 deletions projects/tt_um_senolgulgonul/stats/metrics.csv
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Original file line number Diff line number Diff line change
Expand Up @@ -3,21 +3,21 @@ design__lint_error__count,0
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power__switching__total,3.8007280522833753E-7
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power__total,0.0000016236555211435189
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timing__setup__ws__corner:nom_tt_025C_1v80,1.0000000433293989E+39
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power__leakage__total,1.8443998550665697E-9
power__total,0.00007044856465654448
clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.0006913636525628001
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timing__setup__ws__corner:nom_tt_025C_1v80,14.7000176192399
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timing__setup__tns__corner:nom_tt_025C_1v80,0.0
timing__hold__wns__corner:nom_tt_025C_1v80,0
Expand All @@ -31,10 +31,10 @@ timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
design__max_slew_violation__count__corner:nom_ss_100C_1v60,0
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timing__setup__ws__corner:nom_ss_100C_1v60,1.0000000433293989E+39
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timing__setup__tns__corner:nom_ss_100C_1v60,0.0
timing__hold__wns__corner:nom_ss_100C_1v60,0
Expand All @@ -48,10 +48,10 @@ timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,0
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timing__setup__ws__corner:nom_ff_n40C_1v95,1.0000000433293989E+39
clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.000582561793072408
clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.000582561793072408
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Expand All @@ -65,10 +65,10 @@ timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
design__max_slew_violation__count,0
design__max_fanout_violation__count,0
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timing__setup__ws,13.688949916616698
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timing__hold__wns,0
Expand All @@ -86,56 +86,58 @@ flow__errors__count,0
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design__die__area,17954.7
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design__instance__utilization__stdcell,0.0435442
design__power_grid_violation__count__net:VGND,0
design__instance__utilization,0.0568958
design__instance__utilization__stdcell,0.0568958
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clock__skew__worst_setup__corner:min_tt_025C_1v80,0.0
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clock__skew__worst_setup__corner:min_tt_025C_1v80,0.000486499743149896
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timing__setup__ws__corner:min_tt_025C_1v80,14.705980849318417
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timing__hold__wns__corner:min_tt_025C_1v80,0
Expand All @@ -146,15 +148,15 @@ timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
timing__setup_vio__count__corner:min_tt_025C_1v80,0
timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity
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timing__setup__tns__corner:min_ss_100C_1v60,0.0
timing__hold__wns__corner:min_ss_100C_1v60,0
Expand All @@ -165,15 +167,15 @@ timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
timing__setup_vio__count__corner:min_ss_100C_1v60,0
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timing__setup__ws__corner:min_ff_n40C_1v95,1.0000000433293989E+39
clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.00039143689397780595
clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.00039143689397780595
timing__hold__ws__corner:min_ff_n40C_1v95,0.1179136266446428
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timing__setup__tns__corner:min_ff_n40C_1v95,0.0
timing__hold__wns__corner:min_ff_n40C_1v95,0
Expand All @@ -184,15 +186,15 @@ timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
timing__setup_vio__count__corner:min_ff_n40C_1v95,0
timing__setup_r2r__ws__corner:min_ff_n40C_1v95,Infinity
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timing__setup__tns__corner:max_tt_025C_1v80,0.0
timing__hold__wns__corner:max_tt_025C_1v80,0
Expand All @@ -203,15 +205,15 @@ timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
timing__setup_vio__count__corner:max_tt_025C_1v80,0
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timing__hold__wns__corner:max_ss_100C_1v60,0
Expand All @@ -222,15 +224,15 @@ timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
timing__setup_vio__count__corner:max_ss_100C_1v60,0
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timing__setup__tns__corner:max_ff_n40C_1v95,0.0
timing__hold__wns__corner:max_ff_n40C_1v95,0
Expand All @@ -241,19 +243,19 @@ timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
timing__setup_vio__count__corner:max_ff_n40C_1v95,0
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magic__drc_error__count,0
magic__illegal_overlap__count,0
design__lvs_device_difference__count,0
Expand Down
31 changes: 17 additions & 14 deletions projects/tt_um_senolgulgonul/stats/synthesis-stats.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2,30 +2,33 @@

=== tt_um_senolgulgonul ===

Number of wires: 36
Number of wire bits: 71
Number of wires: 38
Number of wire bits: 73
Number of public wires: 12
Number of public wire bits: 47
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 52
Number of cells: 54
sky130_fd_sc_hd__a211o_2 1
sky130_fd_sc_hd__a21boi_2 1
sky130_fd_sc_hd__a21o_2 2
sky130_fd_sc_hd__a21oi_2 3
sky130_fd_sc_hd__and2b_2 1
sky130_fd_sc_hd__and3_2 1
sky130_fd_sc_hd__a21oi_2 2
sky130_fd_sc_hd__a31o_2 1
sky130_fd_sc_hd__and2_2 1
sky130_fd_sc_hd__and3_2 2
sky130_fd_sc_hd__buf_2 1
sky130_fd_sc_hd__conb_1 17
sky130_fd_sc_hd__dfxtp_2 10
sky130_fd_sc_hd__inv_2 2
sky130_fd_sc_hd__nand2_2 3
sky130_fd_sc_hd__conb_1 16
sky130_fd_sc_hd__dfrtp_2 11
sky130_fd_sc_hd__inv_2 4
sky130_fd_sc_hd__mux2_1 3
sky130_fd_sc_hd__nand2_2 2
sky130_fd_sc_hd__nand2b_2 1
sky130_fd_sc_hd__nor2_2 1
sky130_fd_sc_hd__o211a_2 2
sky130_fd_sc_hd__o21a_2 3
sky130_fd_sc_hd__o211a_2 1
sky130_fd_sc_hd__o21ba_2 1
sky130_fd_sc_hd__or2_2 3
sky130_fd_sc_hd__or3_2 2
sky130_fd_sc_hd__xnor2_2 1

Chip area for module '\tt_um_senolgulgonul': 474.204800
Chip area for module '\tt_um_senolgulgonul': 569.296000

Binary file modified projects/tt_um_senolgulgonul/tt_um_senolgulgonul.gds
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