feat: update project tt_um_toivoh_pio_ram_emu_example from toivoh/tt0…

…9-pio-ram-emulator-example

Commit: 9ae25a2aa0980db966a51fb456d1b3f6b7d19741
Workflow: https://github.com/toivoh/tt09-pio-ram-emulator-example/actions/runs/11718641488

projects/tt_um_toivoh_pio_ram_emu_example/commit_id.json

@@ -1,8 +1,8 @@
 {
-  "app": "Tiny Tapeout tt09 b176ed7c",
+  "app": "Tiny Tapeout tt09 a48b1c74",
   "repo": "https://github.com/toivoh/tt09-pio-ram-emulator-example",
-  "commit": "b08d5dd9c3b6eccac9b9081b33e04b702a22e379",
-  "workflow_url": "https://github.com/toivoh/tt09-pio-ram-emulator-example/actions/runs/11617414988",
+  "commit": "9ae25a2aa0980db966a51fb456d1b3f6b7d19741",
+  "workflow_url": "https://github.com/toivoh/tt09-pio-ram-emulator-example/actions/runs/11718641488",
   "sort_id": 1729929406809,
   "openlane_version": "OpenLane2 2.1.9",
   "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"

projects/tt_um_toivoh_pio_ram_emu_example/stats/metrics.csv

@@ -1,23 +1,23 @@
 Metric,Value
 design__lint_error__count,0
 design__lint_timing_construct__count,0
-design__lint_warning__count,31
+design__lint_warning__count,38
 design__inferred_latch__count,0
-design__instance__count,2498
-design__instance__area,19297.3
+design__instance__count,3012
+design__instance__area,23814.1
 design__instance_unmapped__count,0
 synthesis__check_error__count,0
 design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
-design__max_fanout_violation__count__corner:nom_tt_025C_1v80,11
+design__max_fanout_violation__count__corner:nom_tt_025C_1v80,20
 design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
-power__internal__total,0.0022639241069555283
-power__switching__total,0.0022566935513168573
-power__leakage__total,2.164625101386264E-8
-power__total,0.004520638845860958
-clock__skew__worst_hold__corner:nom_tt_025C_1v80,-0.020792590460141938
-clock__skew__worst_setup__corner:nom_tt_025C_1v80,-0.020792590460141938
-timing__hold__ws__corner:nom_tt_025C_1v80,0.30890457732753546
-timing__setup__ws__corner:nom_tt_025C_1v80,12.612943935178961
+power__internal__total,0.0022186723072081804
+power__switching__total,0.001936699845828116
+power__leakage__total,2.577833058126089E-8
+power__total,0.00415539788082242
+clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.24061886497678134
+clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.24061886497678134
+timing__hold__ws__corner:nom_tt_025C_1v80,0.3017044477423004
+timing__setup__ws__corner:nom_tt_025C_1v80,11.132143522087166
 timing__hold__tns__corner:nom_tt_025C_1v80,0.0
 timing__setup__tns__corner:nom_tt_025C_1v80,0.0
 timing__hold__wns__corner:nom_tt_025C_1v80,0
@@ -28,13 +28,13 @@ timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80,0
 timing__setup_vio__count__corner:nom_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:nom_tt_025C_1v80,Infinity
 timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
-design__max_slew_violation__count__corner:nom_ss_100C_1v60,0
-design__max_fanout_violation__count__corner:nom_ss_100C_1v60,11
+design__max_slew_violation__count__corner:nom_ss_100C_1v60,6
+design__max_fanout_violation__count__corner:nom_ss_100C_1v60,20
 design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
-clock__skew__worst_hold__corner:nom_ss_100C_1v60,-0.028805070255470095
-clock__skew__worst_setup__corner:nom_ss_100C_1v60,-0.028805070255470095
-timing__hold__ws__corner:nom_ss_100C_1v60,0.8498284538844983
-timing__setup__ws__corner:nom_ss_100C_1v60,5.409758127915238
+clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.4106514688972676
+clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.4106514688972676
+timing__hold__ws__corner:nom_ss_100C_1v60,0.8425882452469408
+timing__setup__ws__corner:nom_ss_100C_1v60,5.312156198614019
 timing__hold__tns__corner:nom_ss_100C_1v60,0.0
 timing__setup__tns__corner:nom_ss_100C_1v60,0.0
 timing__hold__wns__corner:nom_ss_100C_1v60,0
@@ -46,12 +46,12 @@ timing__setup_vio__count__corner:nom_ss_100C_1v60,0
 timing__setup_r2r__ws__corner:nom_ss_100C_1v60,Infinity
 timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
 design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0
-design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,11
+design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,20
 design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
-clock__skew__worst_hold__corner:nom_ff_n40C_1v95,-0.01605099432132009
-clock__skew__worst_setup__corner:nom_ff_n40C_1v95,-0.01605099432132009
-timing__hold__ws__corner:nom_ff_n40C_1v95,0.11105894296328969
-timing__setup__ws__corner:nom_ff_n40C_1v95,14.760971529550973
+clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.16751184247178286
+clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.16751184247178286
+timing__hold__ws__corner:nom_ff_n40C_1v95,0.10418483037845616
+timing__setup__ws__corner:nom_ff_n40C_1v95,12.9623639935123
 timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
 timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
 timing__hold__wns__corner:nom_ff_n40C_1v95,0
@@ -62,13 +62,13 @@ timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95,0
 timing__setup_vio__count__corner:nom_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:nom_ff_n40C_1v95,Infinity
 timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
-design__max_slew_violation__count,4
-design__max_fanout_violation__count,11
+design__max_slew_violation__count,6
+design__max_fanout_violation__count,20
 design__max_cap_violation__count,0
-clock__skew__worst_hold,-0.014275414587820253
-clock__skew__worst_setup,-0.035608628165093276
-timing__hold__ws,0.1094076527009118
-timing__setup__ws,5.231067282958887
+clock__skew__worst_hold,0.4256324302371914
+clock__skew__worst_setup,0.16133947412508595
+timing__hold__ws,0.10317841317817004
+timing__setup__ws,5.16411816814528
 timing__hold__tns,0.0
 timing__setup__tns,0.0
 timing__hold__wns,0
@@ -86,60 +86,60 @@ flow__errors__count,0
 design__io,45
 design__die__area,36347.4
 design__core__area,34255.4
-design__instance__count__stdcell,2498
-design__instance__area__stdcell,19297.3
+design__instance__count__stdcell,3012
+design__instance__area__stdcell,23814.1
 design__instance__count__macros,0
 design__instance__area__macros,0
-design__instance__utilization,0.563336
-design__instance__utilization__stdcell,0.563336
-design__power_grid_violation__count__net:VGND,0
+design__instance__utilization,0.695193
+design__instance__utilization__stdcell,0.695193
 design__power_grid_violation__count__net:VPWR,0
+design__power_grid_violation__count__net:VGND,0
 design__power_grid_violation__count,0
 timing__drv__floating__nets,0
 timing__drv__floating__pins,0
 design__instance__displacement__total,0
 design__instance__displacement__mean,0
 design__instance__displacement__max,0
-route__wirelength__estimated,41035.7
+route__wirelength__estimated,45812
 design__violations,0
 design__instance__count__setup_buffer,0
-design__instance__count__hold_buffer,158
+design__instance__count__hold_buffer,214
 antenna__violating__nets,0
 antenna__violating__pins,0
 route__antenna_violation__count,0
-route__net,2054
+route__net,2554
 route__net__special,2
-route__drc_errors__iter:1,809
-route__wirelength__iter:1,45871
-route__drc_errors__iter:2,268
-route__wirelength__iter:2,45550
-route__drc_errors__iter:3,263
-route__wirelength__iter:3,45320
+route__drc_errors__iter:1,1292
+route__wirelength__iter:1,51031
+route__drc_errors__iter:2,404
+route__wirelength__iter:2,50573
+route__drc_errors__iter:3,364
+route__wirelength__iter:3,50354
 route__drc_errors__iter:4,14
-route__wirelength__iter:4,45291
+route__wirelength__iter:4,50333
 route__drc_errors__iter:5,0
-route__wirelength__iter:5,45275
+route__wirelength__iter:5,50330
 route__drc_errors,0
-route__wirelength,45275
-route__vias,14173
-route__vias__singlecut,14173
+route__wirelength,50330
+route__vias,17530
+route__vias__singlecut,17530
 route__vias__multicut,0
-design__disconnected_pin__count,15
+design__disconnected_pin__count,8
 design__critical_disconnected_pin__count,0
-route__wirelength__max,291.36
-timing__unannotated_net__count__corner:nom_tt_025C_1v80,36
+route__wirelength__max,397.31
+timing__unannotated_net__count__corner:nom_tt_025C_1v80,43
 timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
-timing__unannotated_net__count__corner:nom_ss_100C_1v60,36
+timing__unannotated_net__count__corner:nom_ss_100C_1v60,43
 timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0
-timing__unannotated_net__count__corner:nom_ff_n40C_1v95,36
+timing__unannotated_net__count__corner:nom_ff_n40C_1v95,43
 timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
 design__max_slew_violation__count__corner:min_tt_025C_1v80,0
-design__max_fanout_violation__count__corner:min_tt_025C_1v80,11
+design__max_fanout_violation__count__corner:min_tt_025C_1v80,20
 design__max_cap_violation__count__corner:min_tt_025C_1v80,0
-clock__skew__worst_hold__corner:min_tt_025C_1v80,-0.01848160565787433
-clock__skew__worst_setup__corner:min_tt_025C_1v80,-0.01848160565787433
-timing__hold__ws__corner:min_tt_025C_1v80,0.30431991121768265
-timing__setup__ws__corner:min_tt_025C_1v80,12.696369648322413
+clock__skew__worst_hold__corner:min_tt_025C_1v80,0.23282726405844925
+clock__skew__worst_setup__corner:min_tt_025C_1v80,0.23282726405844925
+timing__hold__ws__corner:min_tt_025C_1v80,0.2985594633803472
+timing__setup__ws__corner:min_tt_025C_1v80,11.193886134857241
 timing__hold__tns__corner:min_tt_025C_1v80,0.0
 timing__setup__tns__corner:min_tt_025C_1v80,0.0
 timing__hold__wns__corner:min_tt_025C_1v80,0
@@ -150,15 +150,15 @@ timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
 timing__setup_vio__count__corner:min_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity
 timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
-timing__unannotated_net__count__corner:min_tt_025C_1v80,36
+timing__unannotated_net__count__corner:min_tt_025C_1v80,43
 timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
-design__max_slew_violation__count__corner:min_ss_100C_1v60,0
-design__max_fanout_violation__count__corner:min_ss_100C_1v60,11
+design__max_slew_violation__count__corner:min_ss_100C_1v60,6
+design__max_fanout_violation__count__corner:min_ss_100C_1v60,20
 design__max_cap_violation__count__corner:min_ss_100C_1v60,0
-clock__skew__worst_hold__corner:min_ss_100C_1v60,-0.02519640123416836
-clock__skew__worst_setup__corner:min_ss_100C_1v60,-0.02519640123416836
-timing__hold__ws__corner:min_ss_100C_1v60,0.8394716270840691
-timing__setup__ws__corner:min_ss_100C_1v60,5.562272577745867
+clock__skew__worst_hold__corner:min_ss_100C_1v60,0.3980693665144958
+clock__skew__worst_setup__corner:min_ss_100C_1v60,0.3980693665144958
+timing__hold__ws__corner:min_ss_100C_1v60,0.8366279017483682
+timing__setup__ws__corner:min_ss_100C_1v60,5.445150262584406
 timing__hold__tns__corner:min_ss_100C_1v60,0.0
 timing__setup__tns__corner:min_ss_100C_1v60,0.0
 timing__hold__wns__corner:min_ss_100C_1v60,0
@@ -169,15 +169,15 @@ timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
 timing__setup_vio__count__corner:min_ss_100C_1v60,0
 timing__setup_r2r__ws__corner:min_ss_100C_1v60,Infinity
 timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
-timing__unannotated_net__count__corner:min_ss_100C_1v60,36
+timing__unannotated_net__count__corner:min_ss_100C_1v60,43
 timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
 design__max_slew_violation__count__corner:min_ff_n40C_1v95,0
-design__max_fanout_violation__count__corner:min_ff_n40C_1v95,11
+design__max_fanout_violation__count__corner:min_ff_n40C_1v95,20
 design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
-clock__skew__worst_hold__corner:min_ff_n40C_1v95,-0.014275414587820253
-clock__skew__worst_setup__corner:min_ff_n40C_1v95,-0.014275414587820253
-timing__hold__ws__corner:min_ff_n40C_1v95,0.1094076527009118
-timing__setup__ws__corner:min_ff_n40C_1v95,14.793889199072876
+clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.16133947412508595
+clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.16133947412508595
+timing__hold__ws__corner:min_ff_n40C_1v95,0.10317841317817004
+timing__setup__ws__corner:min_ff_n40C_1v95,13.00001743050198
 timing__hold__tns__corner:min_ff_n40C_1v95,0.0
 timing__setup__tns__corner:min_ff_n40C_1v95,0.0
 timing__hold__wns__corner:min_ff_n40C_1v95,0
@@ -188,15 +188,15 @@ timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
 timing__setup_vio__count__corner:min_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:min_ff_n40C_1v95,Infinity
 timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
-timing__unannotated_net__count__corner:min_ff_n40C_1v95,36
+timing__unannotated_net__count__corner:min_ff_n40C_1v95,43
 timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
-design__max_slew_violation__count__corner:max_tt_025C_1v80,0
-design__max_fanout_violation__count__corner:max_tt_025C_1v80,11
+design__max_slew_violation__count__corner:max_tt_025C_1v80,2
+design__max_fanout_violation__count__corner:max_tt_025C_1v80,20
 design__max_cap_violation__count__corner:max_tt_025C_1v80,0
-clock__skew__worst_hold__corner:max_tt_025C_1v80,-0.025609570744467843
-clock__skew__worst_setup__corner:max_tt_025C_1v80,-0.025609570744467843
-timing__hold__ws__corner:max_tt_025C_1v80,0.3142872717700586
-timing__setup__ws__corner:max_tt_025C_1v80,12.51565286833343
+clock__skew__worst_hold__corner:max_tt_025C_1v80,0.25019825808222956
+clock__skew__worst_setup__corner:max_tt_025C_1v80,0.25019825808222956
+timing__hold__ws__corner:max_tt_025C_1v80,0.30516490198562285
+timing__setup__ws__corner:max_tt_025C_1v80,11.069431906633794
 timing__hold__tns__corner:max_tt_025C_1v80,0.0
 timing__setup__tns__corner:max_tt_025C_1v80,0.0
 timing__hold__wns__corner:max_tt_025C_1v80,0
@@ -207,15 +207,15 @@ timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
 timing__setup_vio__count__corner:max_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:max_tt_025C_1v80,Infinity
 timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
-timing__unannotated_net__count__corner:max_tt_025C_1v80,36
+timing__unannotated_net__count__corner:max_tt_025C_1v80,43
 timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
-design__max_slew_violation__count__corner:max_ss_100C_1v60,4
-design__max_fanout_violation__count__corner:max_ss_100C_1v60,11
+design__max_slew_violation__count__corner:max_ss_100C_1v60,6
+design__max_fanout_violation__count__corner:max_ss_100C_1v60,20
 design__max_cap_violation__count__corner:max_ss_100C_1v60,0
-clock__skew__worst_hold__corner:max_ss_100C_1v60,-0.035608628165093276
-clock__skew__worst_setup__corner:max_ss_100C_1v60,-0.035608628165093276
-timing__hold__ws__corner:max_ss_100C_1v60,0.8613701107303169
-timing__setup__ws__corner:max_ss_100C_1v60,5.231067282958887
+clock__skew__worst_hold__corner:max_ss_100C_1v60,0.4256324302371914
+clock__skew__worst_setup__corner:max_ss_100C_1v60,0.4256324302371914
+timing__hold__ws__corner:max_ss_100C_1v60,0.8490139942505989
+timing__setup__ws__corner:max_ss_100C_1v60,5.16411816814528
 timing__hold__tns__corner:max_ss_100C_1v60,0.0
 timing__setup__tns__corner:max_ss_100C_1v60,0.0
 timing__hold__wns__corner:max_ss_100C_1v60,0
@@ -226,15 +226,15 @@ timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
 timing__setup_vio__count__corner:max_ss_100C_1v60,0
 timing__setup_r2r__ws__corner:max_ss_100C_1v60,Infinity
 timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
-timing__unannotated_net__count__corner:max_ss_100C_1v60,36
+timing__unannotated_net__count__corner:max_ss_100C_1v60,43
 timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
 design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
-design__max_fanout_violation__count__corner:max_ff_n40C_1v95,11
+design__max_fanout_violation__count__corner:max_ff_n40C_1v95,20
 design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
-clock__skew__worst_hold__corner:max_ff_n40C_1v95,-0.01996633470627217
-clock__skew__worst_setup__corner:max_ff_n40C_1v95,-0.01996633470627217
-timing__hold__ws__corner:max_ff_n40C_1v95,0.1130376380048892
-timing__setup__ws__corner:max_ff_n40C_1v95,14.717235846571171
+clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.17541654736394743
+clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.17541654736394743
+timing__hold__ws__corner:max_ff_n40C_1v95,0.10394452259797968
+timing__setup__ws__corner:max_ff_n40C_1v95,12.925223923663728
 timing__hold__tns__corner:max_ff_n40C_1v95,0.0
 timing__setup__tns__corner:max_ff_n40C_1v95,0.0
 timing__hold__wns__corner:max_ff_n40C_1v95,0
@@ -245,19 +245,19 @@ timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
 timing__setup_vio__count__corner:max_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:max_ff_n40C_1v95,Infinity
 timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0
-timing__unannotated_net__count__corner:max_ff_n40C_1v95,36
+timing__unannotated_net__count__corner:max_ff_n40C_1v95,43
 timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0
-timing__unannotated_net__count,36
+timing__unannotated_net__count,43
 timing__unannotated_net_filtered__count,0
-design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.7998
-design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.79996
-design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.000198965
-design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.000233919
-design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.0000380629
-design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.000233919
+design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79982
+design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.79997
+design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.000180819
+design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.000192932
+design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.0000346719
+design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.000192932
 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
-ir__drop__avg,0.0000374999999999999967148674173689215649574180133640766143798828125
-ir__drop__worst,0.0001990000000000000123824561715224490399123169481754302978515625
+ir__drop__avg,0.0000341999999999999978171107140045847927467548288404941558837890625
+ir__drop__worst,0.0001810000000000000085383089487578445186954922974109649658203125
 magic__drc_error__count,0
 magic__illegal_overlap__count,0
 design__lvs_device_difference__count,0