feat: update project tt_um_favoritohjs_scroller from FavoritoHJS/tt08…

…-favoritohjs-scroller

Commit: 38c700b6e2a04212e34f9b74e5a21c62d5963aff
Workflow: https://github.com/FavoritoHJS/tt08-favoritohjs-scroller/actions/runs/10604929472

projects/tt_um_favoritohjs_scroller/commit_id.json

@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout tt08 86beb5d8",
   "repo": "https://github.com/FavoritoHJS/tt08-favoritohjs-scroller",
-  "commit": "bf6300bc81e2a00f3e2f22c41ff73b267b2aefd0",
-  "workflow_url": "https://github.com/FavoritoHJS/tt08-favoritohjs-scroller/actions/runs/10587603163",
+  "commit": "38c700b6e2a04212e34f9b74e5a21c62d5963aff",
+  "workflow_url": "https://github.com/FavoritoHJS/tt08-favoritohjs-scroller/actions/runs/10604929472",
   "sort_id": 1724871583419,
   "openlane_version": "OpenLane2 2.0.8",
   "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"

projects/tt_um_favoritohjs_scroller/stats/metrics.csv

@@ -3,81 +3,81 @@ design__lint_error__count,0
 design__lint_timing_construct__count,0
 design__lint_warning__count,3
 design__inferred_latch__count,0
-design__instance__count,817
-design__instance__area,6090.84
+design__instance__count,841
+design__instance__area,6337.33
 design__instance_unmapped__count,0
 synthesis__check_error__count,0
 design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:nom_tt_025C_1v80,8
 design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
-power__internal__total,0.00035954220220446587
-power__switching__total,0.00010474283044459298
-power__leakage__total,7.1307875160186995e-09
-power__total,0.00046429215581156313
-clock__skew__worst_hold__corner:nom_tt_025C_1v80,-0.020022
-clock__skew__worst_setup__corner:nom_tt_025C_1v80,-0.020022
-timing__hold__ws__corner:nom_tt_025C_1v80,0.314698
-timing__setup__ws__corner:nom_tt_025C_1v80,14.277033
+power__internal__total,0.0003685734118334949
+power__switching__total,0.00011673667904688045
+power__leakage__total,7.309036931246737e-09
+power__total,0.0004853174032177776
+clock__skew__worst_hold__corner:nom_tt_025C_1v80,-0.018865
+clock__skew__worst_setup__corner:nom_tt_025C_1v80,-0.018865
+timing__hold__ws__corner:nom_tt_025C_1v80,0.310309
+timing__setup__ws__corner:nom_tt_025C_1v80,14.328888
 timing__hold__tns__corner:nom_tt_025C_1v80,0.0
 timing__setup__tns__corner:nom_tt_025C_1v80,0.0
 timing__hold__wns__corner:nom_tt_025C_1v80,0.0
 timing__setup__wns__corner:nom_tt_025C_1v80,0.0
 timing__hold_vio__count__corner:nom_tt_025C_1v80,0
-timing__hold_r2r__ws__corner:nom_tt_025C_1v80,0.314698
+timing__hold_r2r__ws__corner:nom_tt_025C_1v80,0.310309
 timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80,0
 timing__setup_vio__count__corner:nom_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:nom_tt_025C_1v80,inf
 timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
 design__max_slew_violation__count__corner:nom_ss_100C_1v60,0
 design__max_fanout_violation__count__corner:nom_ss_100C_1v60,8
 design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
-clock__skew__worst_hold__corner:nom_ss_100C_1v60,-0.031928
-clock__skew__worst_setup__corner:nom_ss_100C_1v60,-0.031928
-timing__hold__ws__corner:nom_ss_100C_1v60,0.853288
-timing__setup__ws__corner:nom_ss_100C_1v60,12.336541
+clock__skew__worst_hold__corner:nom_ss_100C_1v60,-0.029469
+clock__skew__worst_setup__corner:nom_ss_100C_1v60,-0.029469
+timing__hold__ws__corner:nom_ss_100C_1v60,0.843533
+timing__setup__ws__corner:nom_ss_100C_1v60,12.93188
 timing__hold__tns__corner:nom_ss_100C_1v60,0.0
 timing__setup__tns__corner:nom_ss_100C_1v60,0.0
 timing__hold__wns__corner:nom_ss_100C_1v60,0.0
 timing__setup__wns__corner:nom_ss_100C_1v60,0.0
 timing__hold_vio__count__corner:nom_ss_100C_1v60,0
-timing__hold_r2r__ws__corner:nom_ss_100C_1v60,0.853288
+timing__hold_r2r__ws__corner:nom_ss_100C_1v60,0.843533
 timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60,0
 timing__setup_vio__count__corner:nom_ss_100C_1v60,0
-timing__setup_r2r__ws__corner:nom_ss_100C_1v60,12.336541
+timing__setup_r2r__ws__corner:nom_ss_100C_1v60,13.065924
 timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
 design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0
 design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,8
 design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
-clock__skew__worst_hold__corner:nom_ff_n40C_1v95,-0.015416
-clock__skew__worst_setup__corner:nom_ff_n40C_1v95,-0.015416
-timing__hold__ws__corner:nom_ff_n40C_1v95,0.118745
-timing__setup__ws__corner:nom_ff_n40C_1v95,14.832499
+clock__skew__worst_hold__corner:nom_ff_n40C_1v95,-0.014559
+clock__skew__worst_setup__corner:nom_ff_n40C_1v95,-0.014559
+timing__hold__ws__corner:nom_ff_n40C_1v95,0.11108
+timing__setup__ws__corner:nom_ff_n40C_1v95,14.92327
 timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
 timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
 timing__hold__wns__corner:nom_ff_n40C_1v95,0.0
 timing__setup__wns__corner:nom_ff_n40C_1v95,0.0
 timing__hold_vio__count__corner:nom_ff_n40C_1v95,0
-timing__hold_r2r__ws__corner:nom_ff_n40C_1v95,0.118745
+timing__hold_r2r__ws__corner:nom_ff_n40C_1v95,0.11108
 timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95,0
 timing__setup_vio__count__corner:nom_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:nom_ff_n40C_1v95,inf
 timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
-design__max_slew_violation__count,5
+design__max_slew_violation__count,0
 design__max_fanout_violation__count,8
 design__max_cap_violation__count,0
-clock__skew__worst_hold,-0.014689
-clock__skew__worst_setup,-0.033256
-timing__hold__ws,0.115331
-timing__setup__ws,12.297603
+clock__skew__worst_hold,-0.013523
+clock__skew__worst_setup,-0.030925
+timing__hold__ws,0.108827
+timing__setup__ws,12.87329
 timing__hold__tns,0.0
 timing__setup__tns,0.0
 timing__hold__wns,0.0
 timing__setup__wns,0.0
 timing__hold_vio__count,0
-timing__hold_r2r__ws,0.115331
+timing__hold_r2r__ws,0.108827
 timing__hold_r2r_vio__count,0
 timing__setup_vio__count,0
-timing__setup_r2r__ws,12.297603
+timing__setup_r2r__ws,12.986362
 timing__setup_r2r_vio__count,0
 design__die__bbox,0.0 0.0 161.0 111.52
 design__core__bbox,2.76 2.72 158.24 108.8
@@ -86,12 +86,12 @@ flow__errors__count,0
 design__io,45
 design__die__area,17954.7
 design__core__area,16493.3
-design__instance__count__stdcell,817
-design__instance__area__stdcell,6090.84
+design__instance__count__stdcell,841
+design__instance__area__stdcell,6337.33
 design__instance__count__macros,0
 design__instance__area__macros,0
-design__instance__utilization,0.369291
-design__instance__utilization__stdcell,0.369291
+design__instance__utilization,0.384236
+design__instance__utilization__stdcell,0.384236
 design__power_grid_violation__count__net:VGND,0
 design__power_grid_violation__count__net:VPWR,0
 design__power_grid_violation__count,0
@@ -100,31 +100,33 @@ timing__drv__floating__pins,0
 design__instance__displacement__total,0
 design__instance__displacement__mean,0
 design__instance__displacement__max,0
-route__wirelength__estimated,10107
+route__wirelength__estimated,10469.7
 design__violations,0
 design__instance__count__setup_buffer,0
-design__instance__count__hold_buffer,50
+design__instance__count__hold_buffer,49
 antenna__violating__nets,0
 antenna__violating__pins,0
 route__antenna_violation__count,0
-route__net,611
+route__net,635
 route__net__special,2
-route__drc_errors__iter:1,317
-route__wirelength__iter:1,11682
-route__drc_errors__iter:2,69
-route__wirelength__iter:2,11450
-route__drc_errors__iter:3,77
-route__wirelength__iter:3,11341
-route__drc_errors__iter:4,0
-route__wirelength__iter:4,11327
+route__drc_errors__iter:1,368
+route__wirelength__iter:1,12047
+route__drc_errors__iter:2,107
+route__wirelength__iter:2,11874
+route__drc_errors__iter:3,59
+route__wirelength__iter:3,11816
+route__drc_errors__iter:4,4
+route__wirelength__iter:4,11791
+route__drc_errors__iter:5,0
+route__wirelength__iter:5,11790
 route__drc_errors,0
-route__wirelength,11327
-route__vias,4080
-route__vias__singlecut,4080
+route__wirelength,11790
+route__vias,4172
+route__vias__singlecut,4172
 route__vias__multicut,0
 design__disconnected_pin__count,17
 design__critical_disconnected_pin__count,0
-route__wirelength__max,175.24
+route__wirelength__max,174.2
 timing__unannotated_net__count__corner:nom_tt_025C_1v80,33
 timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
 timing__unannotated_net__count__corner:nom_ss_100C_1v60,33
@@ -134,16 +136,16 @@ timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
 design__max_slew_violation__count__corner:min_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:min_tt_025C_1v80,8
 design__max_cap_violation__count__corner:min_tt_025C_1v80,0
-clock__skew__worst_hold__corner:min_tt_025C_1v80,-0.018951
-clock__skew__worst_setup__corner:min_tt_025C_1v80,-0.018951
-timing__hold__ws__corner:min_tt_025C_1v80,0.310745
-timing__setup__ws__corner:min_tt_025C_1v80,14.327536
+clock__skew__worst_hold__corner:min_tt_025C_1v80,-0.01761
+clock__skew__worst_setup__corner:min_tt_025C_1v80,-0.01761
+timing__hold__ws__corner:min_tt_025C_1v80,0.306358
+timing__setup__ws__corner:min_tt_025C_1v80,14.35862
 timing__hold__tns__corner:min_tt_025C_1v80,0.0
 timing__setup__tns__corner:min_tt_025C_1v80,0.0
 timing__hold__wns__corner:min_tt_025C_1v80,0.0
 timing__setup__wns__corner:min_tt_025C_1v80,0.0
 timing__hold_vio__count__corner:min_tt_025C_1v80,0
-timing__hold_r2r__ws__corner:min_tt_025C_1v80,0.310745
+timing__hold_r2r__ws__corner:min_tt_025C_1v80,0.306358
 timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
 timing__setup_vio__count__corner:min_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:min_tt_025C_1v80,inf
@@ -153,35 +155,35 @@ timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
 design__max_slew_violation__count__corner:min_ss_100C_1v60,0
 design__max_fanout_violation__count__corner:min_ss_100C_1v60,8
 design__max_cap_violation__count__corner:min_ss_100C_1v60,0
-clock__skew__worst_hold__corner:min_ss_100C_1v60,-0.030594
-clock__skew__worst_setup__corner:min_ss_100C_1v60,-0.030594
-timing__hold__ws__corner:min_ss_100C_1v60,0.847777
-timing__setup__ws__corner:min_ss_100C_1v60,12.379954
+clock__skew__worst_hold__corner:min_ss_100C_1v60,-0.02802
+clock__skew__worst_setup__corner:min_ss_100C_1v60,-0.02802
+timing__hold__ws__corner:min_ss_100C_1v60,0.83816
+timing__setup__ws__corner:min_ss_100C_1v60,12.987107
 timing__hold__tns__corner:min_ss_100C_1v60,0.0
 timing__setup__tns__corner:min_ss_100C_1v60,0.0
 timing__hold__wns__corner:min_ss_100C_1v60,0.0
 timing__setup__wns__corner:min_ss_100C_1v60,0.0
 timing__hold_vio__count__corner:min_ss_100C_1v60,0
-timing__hold_r2r__ws__corner:min_ss_100C_1v60,0.847777
+timing__hold_r2r__ws__corner:min_ss_100C_1v60,0.83816
 timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
 timing__setup_vio__count__corner:min_ss_100C_1v60,0
-timing__setup_r2r__ws__corner:min_ss_100C_1v60,12.379954
+timing__setup_r2r__ws__corner:min_ss_100C_1v60,13.170222
 timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
 timing__unannotated_net__count__corner:min_ss_100C_1v60,33
 timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
 design__max_slew_violation__count__corner:min_ff_n40C_1v95,0
 design__max_fanout_violation__count__corner:min_ff_n40C_1v95,8
 design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
-clock__skew__worst_hold__corner:min_ff_n40C_1v95,-0.014689
-clock__skew__worst_setup__corner:min_ff_n40C_1v95,-0.014689
-timing__hold__ws__corner:min_ff_n40C_1v95,0.115331
-timing__setup__ws__corner:min_ff_n40C_1v95,14.862948
+clock__skew__worst_hold__corner:min_ff_n40C_1v95,-0.013523
+clock__skew__worst_setup__corner:min_ff_n40C_1v95,-0.013523
+timing__hold__ws__corner:min_ff_n40C_1v95,0.108827
+timing__setup__ws__corner:min_ff_n40C_1v95,14.942798
 timing__hold__tns__corner:min_ff_n40C_1v95,0.0
 timing__setup__tns__corner:min_ff_n40C_1v95,0.0
 timing__hold__wns__corner:min_ff_n40C_1v95,0.0
 timing__setup__wns__corner:min_ff_n40C_1v95,0.0
 timing__hold_vio__count__corner:min_ff_n40C_1v95,0
-timing__hold_r2r__ws__corner:min_ff_n40C_1v95,0.115331
+timing__hold_r2r__ws__corner:min_ff_n40C_1v95,0.108827
 timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
 timing__setup_vio__count__corner:min_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:min_ff_n40C_1v95,inf
@@ -191,54 +193,54 @@ timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
 design__max_slew_violation__count__corner:max_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:max_tt_025C_1v80,8
 design__max_cap_violation__count__corner:max_tt_025C_1v80,0
-clock__skew__worst_hold__corner:max_tt_025C_1v80,-0.021061
-clock__skew__worst_setup__corner:max_tt_025C_1v80,-0.021061
-timing__hold__ws__corner:max_tt_025C_1v80,0.318233
-timing__setup__ws__corner:max_tt_025C_1v80,14.225217
+clock__skew__worst_hold__corner:max_tt_025C_1v80,-0.020128
+clock__skew__worst_setup__corner:max_tt_025C_1v80,-0.020128
+timing__hold__ws__corner:max_tt_025C_1v80,0.313945
+timing__setup__ws__corner:max_tt_025C_1v80,14.298061
 timing__hold__tns__corner:max_tt_025C_1v80,0.0
 timing__setup__tns__corner:max_tt_025C_1v80,0.0
 timing__hold__wns__corner:max_tt_025C_1v80,0.0
 timing__setup__wns__corner:max_tt_025C_1v80,0.0
 timing__hold_vio__count__corner:max_tt_025C_1v80,0
-timing__hold_r2r__ws__corner:max_tt_025C_1v80,0.318233
+timing__hold_r2r__ws__corner:max_tt_025C_1v80,0.313945
 timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
 timing__setup_vio__count__corner:max_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:max_tt_025C_1v80,inf
 timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
 timing__unannotated_net__count__corner:max_tt_025C_1v80,33
 timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
-design__max_slew_violation__count__corner:max_ss_100C_1v60,5
+design__max_slew_violation__count__corner:max_ss_100C_1v60,0
 design__max_fanout_violation__count__corner:max_ss_100C_1v60,8
 design__max_cap_violation__count__corner:max_ss_100C_1v60,0
-clock__skew__worst_hold__corner:max_ss_100C_1v60,-0.033256
-clock__skew__worst_setup__corner:max_ss_100C_1v60,-0.033256
-timing__hold__ws__corner:max_ss_100C_1v60,0.8593
-timing__setup__ws__corner:max_ss_100C_1v60,12.297603
+clock__skew__worst_hold__corner:max_ss_100C_1v60,-0.030925
+clock__skew__worst_setup__corner:max_ss_100C_1v60,-0.030925
+timing__hold__ws__corner:max_ss_100C_1v60,0.849771
+timing__setup__ws__corner:max_ss_100C_1v60,12.87329
 timing__hold__tns__corner:max_ss_100C_1v60,0.0
 timing__setup__tns__corner:max_ss_100C_1v60,0.0
 timing__hold__wns__corner:max_ss_100C_1v60,0.0
 timing__setup__wns__corner:max_ss_100C_1v60,0.0
 timing__hold_vio__count__corner:max_ss_100C_1v60,0
-timing__hold_r2r__ws__corner:max_ss_100C_1v60,0.8593
+timing__hold_r2r__ws__corner:max_ss_100C_1v60,0.849771
 timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
 timing__setup_vio__count__corner:max_ss_100C_1v60,0
-timing__setup_r2r__ws__corner:max_ss_100C_1v60,12.297603
+timing__setup_r2r__ws__corner:max_ss_100C_1v60,12.986362
 timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
 timing__unannotated_net__count__corner:max_ss_100C_1v60,33
 timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
 design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
 design__max_fanout_violation__count__corner:max_ff_n40C_1v95,8
 design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
-clock__skew__worst_hold__corner:max_ff_n40C_1v95,-0.016236
-clock__skew__worst_setup__corner:max_ff_n40C_1v95,-0.016236
-timing__hold__ws__corner:max_ff_n40C_1v95,0.122726
-timing__setup__ws__corner:max_ff_n40C_1v95,14.800902
+clock__skew__worst_hold__corner:max_ff_n40C_1v95,-0.015614
+clock__skew__worst_setup__corner:max_ff_n40C_1v95,-0.015614
+timing__hold__ws__corner:max_ff_n40C_1v95,0.112987
+timing__setup__ws__corner:max_ff_n40C_1v95,14.90323
 timing__hold__tns__corner:max_ff_n40C_1v95,0.0
 timing__setup__tns__corner:max_ff_n40C_1v95,0.0
 timing__hold__wns__corner:max_ff_n40C_1v95,0.0
 timing__setup__wns__corner:max_ff_n40C_1v95,0.0
 timing__hold_vio__count__corner:max_ff_n40C_1v95,0
-timing__hold_r2r__ws__corner:max_ff_n40C_1v95,0.122726
+timing__hold_r2r__ws__corner:max_ff_n40C_1v95,0.112987
 timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
 timing__setup_vio__count__corner:max_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:max_ff_n40C_1v95,inf
@@ -249,13 +251,13 @@ timing__unannotated_net__count,33
 timing__unannotated_net_filtered__count,0
 design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79994
 design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.79999
-design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000584029
-design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000646694
-design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000803644
-design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000646694
+design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000648481
+design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000601932
+design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000832826
+design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000601932
 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
-ir__drop__avg,0.000007849999999999999380074881816238274723218637518584728240966796875
-ir__drop__worst,0.0000584000000000000032865203614118598807181115262210369110107421875
+ir__drop__avg,0.00000825000000000000063252354742804328679994796402752399444580078125
+ir__drop__worst,0.0000648000000000000029969082770975319363060407340526580810546875
 magic__drc_error__count,0
 magic__illegal_overlap__count,0
 design__lvs_device_difference__count,0