feat: update project tt_um_johshoff_metaballs from johshoff/tt08-meta…

…balls

Commit: 43a77932c0da356f35f32cbb3e6657cbc093ef11
Workflow: https://github.com/johshoff/tt08-metaballs/actions/runs/10742983539

projects/tt_um_johshoff_metaballs/commit_id.json

@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout tt08 587b6cb0",
   "repo": "https://github.com/johshoff/tt08-metaballs",
-  "commit": "bb52681f4d1ab1cd17ed34694d1212ac805a40db",
-  "workflow_url": "https://github.com/johshoff/tt08-metaballs/actions/runs/10725233200",
+  "commit": "43a77932c0da356f35f32cbb3e6657cbc093ef11",
+  "workflow_url": "https://github.com/johshoff/tt08-metaballs/actions/runs/10742983539",
   "sort_id": 1725631745115,
   "openlane_version": "OpenLane2 2.0.8",
   "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"

projects/tt_um_johshoff_metaballs/stats/metrics.csv

@@ -1,83 +1,83 @@
 Metric,Value
 design__lint_error__count,0
 design__lint_timing_construct__count,0
-design__lint_warning__count,0
+design__lint_warning__count,4
 design__inferred_latch__count,0
-design__instance__count,1385
-design__instance__area,9406.52
+design__instance__count,1565
+design__instance__area,11402.2
 design__instance_unmapped__count,0
 synthesis__check_error__count,0
 design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:nom_tt_025C_1v80,1
 design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
-power__internal__total,0.0002043167914962396
-power__switching__total,0.00016046894597820938
-power__leakage__total,1.0246266946012383e-08
-power__total,0.0003647959674708545
-clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.015317
-clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.015317
-timing__hold__ws__corner:nom_tt_025C_1v80,0.324973
-timing__setup__ws__corner:nom_tt_025C_1v80,14.558705
+power__internal__total,0.0001146833601524122
+power__switching__total,6.159316399134696e-05
+power__leakage__total,1.1664498700270087e-08
+power__total,0.0001762881875038147
+clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.00928
+clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.00928
+timing__hold__ws__corner:nom_tt_025C_1v80,0.332866
+timing__setup__ws__corner:nom_tt_025C_1v80,14.328883
 timing__hold__tns__corner:nom_tt_025C_1v80,0.0
 timing__setup__tns__corner:nom_tt_025C_1v80,0.0
 timing__hold__wns__corner:nom_tt_025C_1v80,0.0
 timing__setup__wns__corner:nom_tt_025C_1v80,0.0
 timing__hold_vio__count__corner:nom_tt_025C_1v80,0
-timing__hold_r2r__ws__corner:nom_tt_025C_1v80,0.324973
+timing__hold_r2r__ws__corner:nom_tt_025C_1v80,0.332866
 timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80,0
 timing__setup_vio__count__corner:nom_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:nom_tt_025C_1v80,inf
 timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
-design__max_slew_violation__count__corner:nom_ss_100C_1v60,2
+design__max_slew_violation__count__corner:nom_ss_100C_1v60,9
 design__max_fanout_violation__count__corner:nom_ss_100C_1v60,1
 design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
-clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.02564
-clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.02564
-timing__hold__ws__corner:nom_ss_100C_1v60,0.859809
-timing__setup__ws__corner:nom_ss_100C_1v60,13.435703
+clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.015853
+clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.015853
+timing__hold__ws__corner:nom_ss_100C_1v60,0.870958
+timing__setup__ws__corner:nom_ss_100C_1v60,13.156604
 timing__hold__tns__corner:nom_ss_100C_1v60,0.0
 timing__setup__tns__corner:nom_ss_100C_1v60,0.0
 timing__hold__wns__corner:nom_ss_100C_1v60,0.0
 timing__setup__wns__corner:nom_ss_100C_1v60,0.0
 timing__hold_vio__count__corner:nom_ss_100C_1v60,0
-timing__hold_r2r__ws__corner:nom_ss_100C_1v60,0.859809
+timing__hold_r2r__ws__corner:nom_ss_100C_1v60,0.870958
 timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60,0
 timing__setup_vio__count__corner:nom_ss_100C_1v60,0
-timing__setup_r2r__ws__corner:nom_ss_100C_1v60,13.844309
+timing__setup_r2r__ws__corner:nom_ss_100C_1v60,14.65145
 timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
 design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0
 design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,1
 design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
-clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.012161
-clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.012161
-timing__hold__ws__corner:nom_ff_n40C_1v95,0.120382
-timing__setup__ws__corner:nom_ff_n40C_1v95,14.996003
+clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.007188
+clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.007188
+timing__hold__ws__corner:nom_ff_n40C_1v95,0.119945
+timing__setup__ws__corner:nom_ff_n40C_1v95,14.801385
 timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
 timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
 timing__hold__wns__corner:nom_ff_n40C_1v95,0.0
 timing__setup__wns__corner:nom_ff_n40C_1v95,0.0
 timing__hold_vio__count__corner:nom_ff_n40C_1v95,0
-timing__hold_r2r__ws__corner:nom_ff_n40C_1v95,0.120382
+timing__hold_r2r__ws__corner:nom_ff_n40C_1v95,0.119945
 timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95,0
 timing__setup_vio__count__corner:nom_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:nom_ff_n40C_1v95,inf
 timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
-design__max_slew_violation__count,2
+design__max_slew_violation__count,19
 design__max_fanout_violation__count,1
 design__max_cap_violation__count,0
-clock__skew__worst_hold,0.026721
-clock__skew__worst_setup,0.011703
-timing__hold__ws,0.117291
-timing__setup__ws,13.397601
+clock__skew__worst_hold,0.016
+clock__skew__worst_setup,0.006964
+timing__hold__ws,0.117698
+timing__setup__ws,13.082654
 timing__hold__tns,0.0
 timing__setup__tns,0.0
 timing__hold__wns,0.0
 timing__setup__wns,0.0
 timing__hold_vio__count,0
-timing__hold_r2r__ws,0.117291
+timing__hold_r2r__ws,0.117698
 timing__hold_r2r_vio__count,0
 timing__setup_vio__count,0
-timing__setup_r2r__ws,13.777779
+timing__setup_r2r__ws,14.56928
 timing__setup_r2r_vio__count,0
 design__die__bbox,0.0 0.0 161.0 111.52
 design__core__bbox,2.76 2.72 158.24 108.8
@@ -86,12 +86,12 @@ flow__errors__count,0
 design__io,45
 design__die__area,17954.7
 design__core__area,16493.3
-design__instance__count__stdcell,1385
-design__instance__area__stdcell,9406.52
+design__instance__count__stdcell,1565
+design__instance__area__stdcell,11402.2
 design__instance__count__macros,0
 design__instance__area__macros,0
-design__instance__utilization,0.570323
-design__instance__utilization__stdcell,0.570323
+design__instance__utilization,0.691321
+design__instance__utilization__stdcell,0.691321
 design__power_grid_violation__count__net:VGND,0
 design__power_grid_violation__count__net:VPWR,0
 design__power_grid_violation__count,0
@@ -100,33 +100,37 @@ timing__drv__floating__pins,0
 design__instance__displacement__total,0
 design__instance__displacement__mean,0
 design__instance__displacement__max,0
-route__wirelength__estimated,18991.7
+route__wirelength__estimated,23006.4
 design__violations,0
 design__instance__count__setup_buffer,0
-design__instance__count__hold_buffer,9
+design__instance__count__hold_buffer,11
 antenna__violating__nets,0
 antenna__violating__pins,0
 route__antenna_violation__count,0
-route__net,1179
+route__net,1359
 route__net__special,2
-route__drc_errors__iter:1,613
-route__wirelength__iter:1,20901
-route__drc_errors__iter:2,222
-route__wirelength__iter:2,20590
-route__drc_errors__iter:3,171
-route__wirelength__iter:3,20594
-route__drc_errors__iter:4,54
-route__wirelength__iter:4,20597
-route__drc_errors__iter:5,0
-route__wirelength__iter:5,20589
+route__drc_errors__iter:1,673
+route__wirelength__iter:1,26988
+route__drc_errors__iter:2,510
+route__wirelength__iter:2,26780
+route__drc_errors__iter:3,370
+route__wirelength__iter:3,26727
+route__drc_errors__iter:4,88
+route__wirelength__iter:4,26640
+route__drc_errors__iter:5,27
+route__wirelength__iter:5,26633
+route__drc_errors__iter:6,3
+route__wirelength__iter:6,26651
+route__drc_errors__iter:7,0
+route__wirelength__iter:7,26649
 route__drc_errors,0
-route__wirelength,20589
-route__vias,7448
-route__vias__singlecut,7448
+route__wirelength,26649
+route__vias,9705
+route__vias__singlecut,9705
 route__vias__multicut,0
 design__disconnected_pin__count,17
 design__critical_disconnected_pin__count,0
-route__wirelength__max,182.06
+route__wirelength__max,167.11
 timing__unannotated_net__count__corner:nom_tt_025C_1v80,33
 timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
 timing__unannotated_net__count__corner:nom_ss_100C_1v60,33
@@ -136,54 +140,54 @@ timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
 design__max_slew_violation__count__corner:min_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:min_tt_025C_1v80,1
 design__max_cap_violation__count__corner:min_tt_025C_1v80,0
-clock__skew__worst_hold__corner:min_tt_025C_1v80,0.014695
-clock__skew__worst_setup__corner:min_tt_025C_1v80,0.014695
-timing__hold__ws__corner:min_tt_025C_1v80,0.319792
-timing__setup__ws__corner:min_tt_025C_1v80,14.581182
+clock__skew__worst_hold__corner:min_tt_025C_1v80,0.009053
+clock__skew__worst_setup__corner:min_tt_025C_1v80,0.009053
+timing__hold__ws__corner:min_tt_025C_1v80,0.32731
+timing__setup__ws__corner:min_tt_025C_1v80,14.367997
 timing__hold__tns__corner:min_tt_025C_1v80,0.0
 timing__setup__tns__corner:min_tt_025C_1v80,0.0
 timing__hold__wns__corner:min_tt_025C_1v80,0.0
 timing__setup__wns__corner:min_tt_025C_1v80,0.0
 timing__hold_vio__count__corner:min_tt_025C_1v80,0
-timing__hold_r2r__ws__corner:min_tt_025C_1v80,0.319792
+timing__hold_r2r__ws__corner:min_tt_025C_1v80,0.32731
 timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
 timing__setup_vio__count__corner:min_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:min_tt_025C_1v80,inf
 timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
 timing__unannotated_net__count__corner:min_tt_025C_1v80,33
 timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
-design__max_slew_violation__count__corner:min_ss_100C_1v60,2
+design__max_slew_violation__count__corner:min_ss_100C_1v60,0
 design__max_fanout_violation__count__corner:min_ss_100C_1v60,1
 design__max_cap_violation__count__corner:min_ss_100C_1v60,0
-clock__skew__worst_hold__corner:min_ss_100C_1v60,0.02512
-clock__skew__worst_setup__corner:min_ss_100C_1v60,0.02512
-timing__hold__ws__corner:min_ss_100C_1v60,0.851431
-timing__setup__ws__corner:min_ss_100C_1v60,13.476351
+clock__skew__worst_hold__corner:min_ss_100C_1v60,0.015771
+clock__skew__worst_setup__corner:min_ss_100C_1v60,0.015771
+timing__hold__ws__corner:min_ss_100C_1v60,0.861045
+timing__setup__ws__corner:min_ss_100C_1v60,13.229576
 timing__hold__tns__corner:min_ss_100C_1v60,0.0
 timing__setup__tns__corner:min_ss_100C_1v60,0.0
 timing__hold__wns__corner:min_ss_100C_1v60,0.0
 timing__setup__wns__corner:min_ss_100C_1v60,0.0
 timing__hold_vio__count__corner:min_ss_100C_1v60,0
-timing__hold_r2r__ws__corner:min_ss_100C_1v60,0.851431
+timing__hold_r2r__ws__corner:min_ss_100C_1v60,0.861045
 timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
 timing__setup_vio__count__corner:min_ss_100C_1v60,0
-timing__setup_r2r__ws__corner:min_ss_100C_1v60,13.91534
+timing__setup_r2r__ws__corner:min_ss_100C_1v60,14.725225
 timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
 timing__unannotated_net__count__corner:min_ss_100C_1v60,33
 timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
 design__max_slew_violation__count__corner:min_ff_n40C_1v95,0
 design__max_fanout_violation__count__corner:min_ff_n40C_1v95,1
 design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
-clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.011703
-clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.011703
-timing__hold__ws__corner:min_ff_n40C_1v95,0.117291
-timing__setup__ws__corner:min_ff_n40C_1v95,15.010574
+clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.006964
+clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.006964
+timing__hold__ws__corner:min_ff_n40C_1v95,0.117698
+timing__setup__ws__corner:min_ff_n40C_1v95,14.828169
 timing__hold__tns__corner:min_ff_n40C_1v95,0.0
 timing__setup__tns__corner:min_ff_n40C_1v95,0.0
 timing__hold__wns__corner:min_ff_n40C_1v95,0.0
 timing__setup__wns__corner:min_ff_n40C_1v95,0.0
 timing__hold_vio__count__corner:min_ff_n40C_1v95,0
-timing__hold_r2r__ws__corner:min_ff_n40C_1v95,0.117291
+timing__hold_r2r__ws__corner:min_ff_n40C_1v95,0.117698
 timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
 timing__setup_vio__count__corner:min_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:min_ff_n40C_1v95,inf
@@ -193,54 +197,54 @@ timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
 design__max_slew_violation__count__corner:max_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:max_tt_025C_1v80,1
 design__max_cap_violation__count__corner:max_tt_025C_1v80,0
-clock__skew__worst_hold__corner:max_tt_025C_1v80,0.01654
-clock__skew__worst_setup__corner:max_tt_025C_1v80,0.01654
-timing__hold__ws__corner:max_tt_025C_1v80,0.330144
-timing__setup__ws__corner:max_tt_025C_1v80,14.538036
+clock__skew__worst_hold__corner:max_tt_025C_1v80,0.00993
+clock__skew__worst_setup__corner:max_tt_025C_1v80,0.00993
+timing__hold__ws__corner:max_tt_025C_1v80,0.338966
+timing__setup__ws__corner:max_tt_025C_1v80,14.289222
 timing__hold__tns__corner:max_tt_025C_1v80,0.0
 timing__setup__tns__corner:max_tt_025C_1v80,0.0
 timing__hold__wns__corner:max_tt_025C_1v80,0.0
 timing__setup__wns__corner:max_tt_025C_1v80,0.0
 timing__hold_vio__count__corner:max_tt_025C_1v80,0
-timing__hold_r2r__ws__corner:max_tt_025C_1v80,0.330144
+timing__hold_r2r__ws__corner:max_tt_025C_1v80,0.338966
 timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
 timing__setup_vio__count__corner:max_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:max_tt_025C_1v80,inf
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 timing__unannotated_net__count__corner:max_tt_025C_1v80,33
 timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
-design__max_slew_violation__count__corner:max_ss_100C_1v60,2
+design__max_slew_violation__count__corner:max_ss_100C_1v60,19
 design__max_fanout_violation__count__corner:max_ss_100C_1v60,1
 design__max_cap_violation__count__corner:max_ss_100C_1v60,0
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-timing__hold__ws__corner:max_ss_100C_1v60,0.869619
-timing__setup__ws__corner:max_ss_100C_1v60,13.397601
+clock__skew__worst_hold__corner:max_ss_100C_1v60,0.016
+clock__skew__worst_setup__corner:max_ss_100C_1v60,0.016
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+timing__setup__ws__corner:max_ss_100C_1v60,13.082654
 timing__hold__tns__corner:max_ss_100C_1v60,0.0
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 timing__hold_vio__count__corner:max_ss_100C_1v60,0
-timing__hold_r2r__ws__corner:max_ss_100C_1v60,0.869619
+timing__hold_r2r__ws__corner:max_ss_100C_1v60,0.881709
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 timing__setup_vio__count__corner:max_ss_100C_1v60,0
-timing__setup_r2r__ws__corner:max_ss_100C_1v60,13.777779
+timing__setup_r2r__ws__corner:max_ss_100C_1v60,14.56928
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 timing__unannotated_net__count__corner:max_ss_100C_1v60,33
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-timing__setup__ws__corner:max_ff_n40C_1v95,14.984694
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+timing__setup__ws__corner:max_ff_n40C_1v95,14.773479
 timing__hold__tns__corner:max_ff_n40C_1v95,0.0
 timing__setup__tns__corner:max_ff_n40C_1v95,0.0
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 timing__setup__wns__corner:max_ff_n40C_1v95,0.0
 timing__hold_vio__count__corner:max_ff_n40C_1v95,0
-timing__hold_r2r__ws__corner:max_ff_n40C_1v95,0.12333
+timing__hold_r2r__ws__corner:max_ff_n40C_1v95,0.122266
 timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
 timing__setup_vio__count__corner:max_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:max_ff_n40C_1v95,inf
@@ -249,15 +253,15 @@ timing__unannotated_net__count__corner:max_ff_n40C_1v95,33
 timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0
 timing__unannotated_net__count,33
 timing__unannotated_net_filtered__count,0
-design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79995
-design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.79999
-design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000481497
-design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000466756
-design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000643057
-design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000466756
+design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79996
+design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8
+design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000429722
+design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000399399
+design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000320627
+design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000399399
 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
-ir__drop__avg,0.0000066000000000000003366122484915745616262938710860908031463623046875
-ir__drop__worst,0.0000480999999999999968704721131640411613261676393449306488037109375
+ir__drop__avg,0.00000323999999999999989573552967858649509480528649874031543731689453125
+ir__drop__worst,0.000043000000000000001654058834343885564521769993007183074951171875
 magic__drc_error__count,0
 magic__illegal_overlap__count,0
 design__lvs_device_difference__count,0