feat: update project tt_um_rejunity_vga_logo from rejunity/tt08-huge-…

…480x480-tiny-tapeout-logo-in-1-tile

Commit: db5615f0a8d3fd5ee738526bbc2e877fc608d1d2
Workflow: https://github.com/rejunity/tt08-huge-480x480-tiny-tapeout-logo-in-1-tile/actions/runs/10744258571

projects/tt_um_rejunity_vga_logo/commit_id.json

@@ -1,8 +1,8 @@
 {
-  "app": "Tiny Tapeout tt08 58dc0db1",
+  "app": "Tiny Tapeout tt08 587b6cb0",
   "repo": "https://github.com/rejunity/tt08-huge-480x480-tiny-tapeout-logo-in-1-tile",
-  "commit": "ab0dd33ffa24cefe7ab91fbbc83ccf33657b2e48",
-  "workflow_url": "https://github.com/rejunity/tt08-huge-480x480-tiny-tapeout-logo-in-1-tile/actions/runs/9545869232",
+  "commit": "db5615f0a8d3fd5ee738526bbc2e877fc608d1d2",
+  "workflow_url": "https://github.com/rejunity/tt08-huge-480x480-tiny-tapeout-logo-in-1-tile/actions/runs/10744258571",
   "sort_id": 1718227691885,
   "openlane_version": "OpenLane 337ffbf4749b8bc6e8d8742ed9a595934142198b",
   "pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"

projects/tt_um_rejunity_vga_logo/info.yaml

@@ -1,10 +1,10 @@
 
 # Tiny Tapeout project information
 project:
-  title:        "480x480 Tiny Tapeout logo in 1 tile"      # Project title
+  title:        "VGA Tiny Logo (1 tile)"      # Project title
   author:       "Renaldas Zioma"
   discord:      "rzioma"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
-  description:  "Large 480x480 pixels Tiny Tapeout logo crammed into 1 tile"
+  description:  "Large 480x480 pixels Tiny Tapeout logo with bling and dithered colors crammed into 1 tile!"
   language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
   clock_hz:     25175000       # Clock frequency in Hz (or 0 if not applicable)
 

projects/tt_um_rejunity_vga_logo/stats/metrics.csv

@@ -1,2 +1,2 @@
 design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
-/work/src,tt_um_rejunity_vga_logo,wokwi,flow completed,0h2m6s0ms,0h1m44s0ms,92788.97136797455,0.01795472,46394.485683987274,48.47,44.879400000000004,591.47,792,0,0,0,0,0,0,0,0,0,0,-1,-1,15572,5821,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,11068304.0,0.0,34.54,22.03,6.26,1.56,-1,1121,1383,36,227,0,0,0,1195,57,31,52,118,136,167,44,26,65,61,18,827,225,0,352,833,2237,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,31.0,32.25806451612903,30,1,50,26.520,38.870,0.3,1,10,0.81,0,sky130_fd_sc_hd,AREA 0
+/work/src,tt_um_rejunity_vga_logo,wokwi,flow completed,0h2m8s0ms,0h1m46s0ms,92788.97136797455,0.01795472,46394.485683987274,48.47,44.879400000000004,591.71,792,0,0,0,0,0,0,0,0,0,0,-1,-1,15572,5821,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,11068304.0,0.0,34.54,22.03,6.26,1.56,-1,1121,1383,36,227,0,0,0,1195,57,31,52,118,136,167,44,26,65,61,18,827,225,0,352,833,2237,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,31.0,32.25806451612903,30,1,50,26.520,38.870,0.3,1,10,0.81,0,sky130_fd_sc_hd,AREA 0

projects/tt_um_rejunity_vga_logo/tt_um_rejunity_vga_logo.spef

@@ -1,6 +1,6 @@
 *SPEF "ieee 1481-1999"
 *DESIGN "tt_um_rejunity_vga_logo"
-*DATE "10:13:42 Monday June 17, 2024"
+*DATE "19:44:04 Friday September 06, 2024"
 *VENDOR "The OpenROAD Project"
 *PROGRAM "OpenROAD"
 *VERSION "da0053d7b0014ab9c87ea148875ff6c2a0f9b658"