feat: update project tt_um_rebeccargb_universal_decoder from RebeccaR…

…GB/ubcd

Commit: d84feed75990ba265da3c1e19b5f2c143bc619bc
Workflow: https://github.com/RebeccaRGB/ubcd/actions/runs/10052827038

projects/tt_um_rebeccargb_universal_decoder/commit_id.json

@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout tt08 3c88e6eb",
   "repo": "https://github.com/RebeccaRGB/ubcd",
-  "commit": "53d59742d9eec89bc2bb3c3fbb79f591e5c999a5",
-  "workflow_url": "https://github.com/RebeccaRGB/ubcd/actions/runs/10003439252",
+  "commit": "d84feed75990ba265da3c1e19b5f2c143bc619bc",
+  "workflow_url": "https://github.com/RebeccaRGB/ubcd/actions/runs/10052827038",
   "sort_id": 1720377934355,
   "openlane_version": "OpenLane2 2.0.8",
   "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"

projects/tt_um_rebeccargb_universal_decoder/stats/metrics.csv

@@ -3,21 +3,21 @@ design__lint_error__count,0
 design__lint_timing_construct__count,0
 design__lint_warning__count,0
 design__inferred_latch__count,0
-design__instance__count,755
-design__instance__area,4490.56
+design__instance__count,762
+design__instance__area,4369.19
 design__instance_unmapped__count,0
 synthesis__check_error__count,0
 design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:nom_tt_025C_1v80,0
 design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
-power__internal__total,4.5078482798999175e-05
-power__switching__total,7.849368557799608e-05
-power__leakage__total,5.950961945444533e-09
-power__total,0.00012357812374830246
+power__internal__total,3.5158300306648016e-05
+power__switching__total,6.91758468747139e-05
+power__leakage__total,5.594762431115896e-09
+power__total,0.00010433974239276722
 clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.0
 clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.0
-timing__hold__ws__corner:nom_tt_025C_1v80,8.134354
-timing__setup__ws__corner:nom_tt_025C_1v80,7.864316
+timing__hold__ws__corner:nom_tt_025C_1v80,8.110597
+timing__setup__ws__corner:nom_tt_025C_1v80,7.850508
 timing__hold__tns__corner:nom_tt_025C_1v80,0.0
 timing__setup__tns__corner:nom_tt_025C_1v80,0.0
 timing__hold__wns__corner:nom_tt_025C_1v80,0.0
@@ -28,13 +28,13 @@ timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80,0
 timing__setup_vio__count__corner:nom_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:nom_tt_025C_1v80,inf
 timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
-design__max_slew_violation__count__corner:nom_ss_100C_1v60,27
+design__max_slew_violation__count__corner:nom_ss_100C_1v60,11
 design__max_fanout_violation__count__corner:nom_ss_100C_1v60,0
 design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
 clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.0
 clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.0
-timing__hold__ws__corner:nom_ss_100C_1v60,8.444912
-timing__setup__ws__corner:nom_ss_100C_1v60,3.644471
+timing__hold__ws__corner:nom_ss_100C_1v60,8.41385
+timing__setup__ws__corner:nom_ss_100C_1v60,3.927818
 timing__hold__tns__corner:nom_ss_100C_1v60,0.0
 timing__setup__tns__corner:nom_ss_100C_1v60,0.0
 timing__hold__wns__corner:nom_ss_100C_1v60,0.0
@@ -50,8 +50,8 @@ design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,0
 design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
 clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.0
 clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.0
-timing__hold__ws__corner:nom_ff_n40C_1v95,8.010991
-timing__setup__ws__corner:nom_ff_n40C_1v95,9.31332
+timing__hold__ws__corner:nom_ff_n40C_1v95,7.992766
+timing__setup__ws__corner:nom_ff_n40C_1v95,9.329489
 timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
 timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
 timing__hold__wns__corner:nom_ff_n40C_1v95,0.0
@@ -62,13 +62,13 @@ timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95,0
 timing__setup_vio__count__corner:nom_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:nom_ff_n40C_1v95,inf
 timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
-design__max_slew_violation__count,32
+design__max_slew_violation__count,11
 design__max_fanout_violation__count,0
 design__max_cap_violation__count,0
 clock__skew__worst_hold,0.0
 clock__skew__worst_setup,0.0
-timing__hold__ws,8.00977
-timing__setup__ws,3.529534
+timing__hold__ws,7.990977
+timing__setup__ws,3.79771
 timing__hold__tns,0.0
 timing__setup__tns,0.0
 timing__hold__wns,0.0
@@ -86,12 +86,12 @@ flow__errors__count,0
 design__io,45
 design__die__area,17954.7
 design__core__area,16493.3
-design__instance__count__stdcell,755
-design__instance__area__stdcell,4490.56
+design__instance__count__stdcell,762
+design__instance__area__stdcell,4369.19
 design__instance__count__macros,0
 design__instance__area__macros,0
-design__instance__utilization,0.272265
-design__instance__utilization__stdcell,0.272265
+design__instance__utilization,0.264907
+design__instance__utilization__stdcell,0.264907
 design__power_grid_violation__count__net:VPWR,0
 design__power_grid_violation__count__net:VGND,0
 design__power_grid_violation__count,0
@@ -100,46 +100,46 @@ timing__drv__floating__pins,0
 design__instance__displacement__total,0
 design__instance__displacement__mean,0
 design__instance__displacement__max,0
-route__wirelength__estimated,17395.6
+route__wirelength__estimated,17022.6
 design__violations,0
 design__instance__count__setup_buffer,0
 design__instance__count__hold_buffer,0
-antenna__violating__nets,0
-antenna__violating__pins,0
-route__antenna_violation__count,0
-route__net,549
+antenna__violating__nets,1
+antenna__violating__pins,1
+route__antenna_violation__count,1
+route__net,556
 route__net__special,2
-route__drc_errors__iter:1,729
-route__wirelength__iter:1,21418
-route__drc_errors__iter:2,460
-route__wirelength__iter:2,21085
-route__drc_errors__iter:3,327
-route__wirelength__iter:3,20873
-route__drc_errors__iter:4,57
-route__wirelength__iter:4,20878
+route__drc_errors__iter:1,716
+route__wirelength__iter:1,20970
+route__drc_errors__iter:2,328
+route__wirelength__iter:2,20678
+route__drc_errors__iter:3,306
+route__wirelength__iter:3,20581
+route__drc_errors__iter:4,97
+route__wirelength__iter:4,20490
 route__drc_errors__iter:5,0
-route__wirelength__iter:5,20843
+route__wirelength__iter:5,20481
 route__drc_errors,0
-route__wirelength,20843
-route__vias,4843
-route__vias__singlecut,4843
+route__wirelength,20481
+route__vias,4941
+route__vias__singlecut,4941
 route__vias__multicut,0
 design__disconnected_pin__count,3
 design__critical_disconnected_pin__count,0
-route__wirelength__max,250.79
-timing__unannotated_net__count__corner:nom_tt_025C_1v80,22
+route__wirelength__max,214.74
+timing__unannotated_net__count__corner:nom_tt_025C_1v80,15
 timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
-timing__unannotated_net__count__corner:nom_ss_100C_1v60,22
+timing__unannotated_net__count__corner:nom_ss_100C_1v60,15
 timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0
-timing__unannotated_net__count__corner:nom_ff_n40C_1v95,22
+timing__unannotated_net__count__corner:nom_ff_n40C_1v95,15
 timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
 design__max_slew_violation__count__corner:min_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:min_tt_025C_1v80,0
 design__max_cap_violation__count__corner:min_tt_025C_1v80,0
 clock__skew__worst_hold__corner:min_tt_025C_1v80,0.0
 clock__skew__worst_setup__corner:min_tt_025C_1v80,0.0
-timing__hold__ws__corner:min_tt_025C_1v80,8.132819
-timing__setup__ws__corner:min_tt_025C_1v80,7.937357
+timing__hold__ws__corner:min_tt_025C_1v80,8.108212
+timing__setup__ws__corner:min_tt_025C_1v80,7.943294
 timing__hold__tns__corner:min_tt_025C_1v80,0.0
 timing__setup__tns__corner:min_tt_025C_1v80,0.0
 timing__hold__wns__corner:min_tt_025C_1v80,0.0
@@ -150,15 +150,15 @@ timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
 timing__setup_vio__count__corner:min_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:min_tt_025C_1v80,inf
 timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
-timing__unannotated_net__count__corner:min_tt_025C_1v80,22
+timing__unannotated_net__count__corner:min_tt_025C_1v80,15
 timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
-design__max_slew_violation__count__corner:min_ss_100C_1v60,25
+design__max_slew_violation__count__corner:min_ss_100C_1v60,7
 design__max_fanout_violation__count__corner:min_ss_100C_1v60,0
 design__max_cap_violation__count__corner:min_ss_100C_1v60,0
 clock__skew__worst_hold__corner:min_ss_100C_1v60,0.0
 clock__skew__worst_setup__corner:min_ss_100C_1v60,0.0
-timing__hold__ws__corner:min_ss_100C_1v60,8.441909
-timing__setup__ws__corner:min_ss_100C_1v60,3.781119
+timing__hold__ws__corner:min_ss_100C_1v60,8.410071
+timing__setup__ws__corner:min_ss_100C_1v60,4.091572
 timing__hold__tns__corner:min_ss_100C_1v60,0.0
 timing__setup__tns__corner:min_ss_100C_1v60,0.0
 timing__hold__wns__corner:min_ss_100C_1v60,0.0
@@ -169,15 +169,15 @@ timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
 timing__setup_vio__count__corner:min_ss_100C_1v60,0
 timing__setup_r2r__ws__corner:min_ss_100C_1v60,inf
 timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
-timing__unannotated_net__count__corner:min_ss_100C_1v60,22
+timing__unannotated_net__count__corner:min_ss_100C_1v60,15
 timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
 design__max_slew_violation__count__corner:min_ff_n40C_1v95,0
 design__max_fanout_violation__count__corner:min_ff_n40C_1v95,0
 design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
 clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.0
 clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.0
-timing__hold__ws__corner:min_ff_n40C_1v95,8.00977
-timing__setup__ws__corner:min_ff_n40C_1v95,9.380386
+timing__hold__ws__corner:min_ff_n40C_1v95,7.990977
+timing__setup__ws__corner:min_ff_n40C_1v95,9.389252
 timing__hold__tns__corner:min_ff_n40C_1v95,0.0
 timing__setup__tns__corner:min_ff_n40C_1v95,0.0
 timing__hold__wns__corner:min_ff_n40C_1v95,0.0
@@ -188,15 +188,15 @@ timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
 timing__setup_vio__count__corner:min_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:min_ff_n40C_1v95,inf
 timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
-timing__unannotated_net__count__corner:min_ff_n40C_1v95,22
+timing__unannotated_net__count__corner:min_ff_n40C_1v95,15
 timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
-design__max_slew_violation__count__corner:max_tt_025C_1v80,10
+design__max_slew_violation__count__corner:max_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:max_tt_025C_1v80,0
 design__max_cap_violation__count__corner:max_tt_025C_1v80,0
 clock__skew__worst_hold__corner:max_tt_025C_1v80,0.0
 clock__skew__worst_setup__corner:max_tt_025C_1v80,0.0
-timing__hold__ws__corner:max_tt_025C_1v80,8.134711
-timing__setup__ws__corner:max_tt_025C_1v80,7.787971
+timing__hold__ws__corner:max_tt_025C_1v80,8.113045
+timing__setup__ws__corner:max_tt_025C_1v80,7.765048
 timing__hold__tns__corner:max_tt_025C_1v80,0.0
 timing__setup__tns__corner:max_tt_025C_1v80,0.0
 timing__hold__wns__corner:max_tt_025C_1v80,0.0
@@ -207,15 +207,15 @@ timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
 timing__setup_vio__count__corner:max_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:max_tt_025C_1v80,inf
 timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
-timing__unannotated_net__count__corner:max_tt_025C_1v80,22
+timing__unannotated_net__count__corner:max_tt_025C_1v80,15
 timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
-design__max_slew_violation__count__corner:max_ss_100C_1v60,32
+design__max_slew_violation__count__corner:max_ss_100C_1v60,11
 design__max_fanout_violation__count__corner:max_ss_100C_1v60,0
 design__max_cap_violation__count__corner:max_ss_100C_1v60,0
 clock__skew__worst_hold__corner:max_ss_100C_1v60,0.0
 clock__skew__worst_setup__corner:max_ss_100C_1v60,0.0
-timing__hold__ws__corner:max_ss_100C_1v60,8.44591
-timing__setup__ws__corner:max_ss_100C_1v60,3.529534
+timing__hold__ws__corner:max_ss_100C_1v60,8.417569
+timing__setup__ws__corner:max_ss_100C_1v60,3.79771
 timing__hold__tns__corner:max_ss_100C_1v60,0.0
 timing__setup__tns__corner:max_ss_100C_1v60,0.0
 timing__hold__wns__corner:max_ss_100C_1v60,0.0
@@ -226,15 +226,15 @@ timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
 timing__setup_vio__count__corner:max_ss_100C_1v60,0
 timing__setup_r2r__ws__corner:max_ss_100C_1v60,inf
 timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
-timing__unannotated_net__count__corner:max_ss_100C_1v60,22
+timing__unannotated_net__count__corner:max_ss_100C_1v60,15
 timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
 design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
 design__max_fanout_violation__count__corner:max_ff_n40C_1v95,0
 design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
 clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.0
 clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.0
-timing__hold__ws__corner:max_ff_n40C_1v95,8.010788
-timing__setup__ws__corner:max_ff_n40C_1v95,9.254134
+timing__hold__ws__corner:max_ff_n40C_1v95,7.994877
+timing__setup__ws__corner:max_ff_n40C_1v95,9.274708
 timing__hold__tns__corner:max_ff_n40C_1v95,0.0
 timing__setup__tns__corner:max_ff_n40C_1v95,0.0
 timing__hold__wns__corner:max_ff_n40C_1v95,0.0
@@ -245,19 +245,19 @@ timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
 timing__setup_vio__count__corner:max_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:max_ff_n40C_1v95,inf
 timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0
-timing__unannotated_net__count__corner:max_ff_n40C_1v95,22
+timing__unannotated_net__count__corner:max_ff_n40C_1v95,15
 timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0
-timing__unannotated_net__count,22
+timing__unannotated_net__count,15
 timing__unannotated_net_filtered__count,0
-design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79999
+design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79998
 design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8
-design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000137555
-design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000173126
-design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000211633
-design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000173126
+design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000158417
+design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000169657
+design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000185124
+design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000169657
 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
-ir__drop__avg,0.000002110000000000000126864664606873844832080067135393619537353515625
-ir__drop__worst,0.00001380000000000000001079865363795562416271422989666461944580078125
+ir__drop__avg,0.000001839999999999999959088173122345732934945772285573184490203857421875
+ir__drop__worst,0.00001580000000000000119084429817117865013642585836350917816162109375
 magic__drc_error__count,0
 magic__illegal_overlap__count,0
 design__lvs_device_difference__count,0