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feat: update project tt_um_tommythorn_maxbw from tommythorn/tt08-maxbw
Commit: 6c9586f96cb07f6ae94397d1c10b6bb6cd6f6cce Workflow: https://github.com/tommythorn/tt08-maxbw/actions/runs/10697216217
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<!--- | ||
This file is used to generate your project datasheet. Please fill in | ||
the information below and delete any unused sections. | ||
You can also include images in this folder and reference them in the | ||
markdown. Each image must be less than 512 kb in size, and the | ||
combined size of all images must be less than 1 MB. | ||
This file is used to generate your project datasheet. Please fill in the information below and delete any unused | ||
sections. | ||
You can also include images in this folder and reference them in the markdown. Each image must be less than | ||
512 kb in size, and the combined size of all images must be less than 1 MB. | ||
--> | ||
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## How it works | ||
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(please refer to the README.md for now) | ||
This project does work | ||
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## How to test | ||
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Drive it with a very dedicated test bench. | ||
This project can't be tested | ||
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## External hardware | ||
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A suitable uncore, like the RP2040 running the corresponding firmware. | ||
No hardware needed |
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# Tiny Tapeout project information | ||
project: | ||
title: "MaxBW interconnect" | ||
title: "Experiments" | ||
author: "Tommy Thorn" | ||
discord: "tommythorn" | ||
description: "A testbench and proof of concept of the MaxBW core-uncore interconnection" | ||
description: "A 32-bit multiplier" | ||
language: "Verilog" | ||
clock_hz: 66000000 | ||
tiles: "1x1" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2 | ||
top_module: "tt_um_tommythorn_maxbw" | ||
clock_hz: 100 # Clock frequency in Hz (or 0 if not applicable) | ||
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# How many tiles your design occupies? A single tile is about 167x108 uM. | ||
tiles: "1x1" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2 | ||
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# Your top module name must start with "tt_um_". Make it unique by including your github username: | ||
top_module: "tt_um_tommythorn_maxbw" | ||
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# List your project's source files here. | ||
# Source files must be in ./src and you must list each source file separately, one per line. | ||
# Don't forget to also update `PROJECT_SOURCES` in test/Makefile. | ||
source_files: | ||
- "project.v" | ||
- "tokenflow.v" | ||
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# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins. | ||
pinout: | ||
# Inputs | ||
ui[0]: "ingress0" | ||
ui[1]: "ingress1" | ||
ui[2]: "ingress2" | ||
ui[3]: "ingress3" | ||
ui[4]: "ingress4" | ||
ui[5]: "ingress5" | ||
ui[6]: "ingress6" | ||
ui[7]: "ingress7" | ||
ui[0]: "" | ||
ui[1]: "" | ||
ui[2]: "" | ||
ui[3]: "" | ||
ui[4]: "" | ||
ui[5]: "" | ||
ui[6]: "" | ||
ui[7]: "" | ||
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# Outputs | ||
uo[0]: "egress0" | ||
uo[1]: "egress1" | ||
uo[2]: "egress2" | ||
uo[3]: "egress3" | ||
uo[4]: "egress4" | ||
uo[5]: "egress5" | ||
uo[6]: "egress6" | ||
uo[7]: "egress7" | ||
uo[0]: "product_24" | ||
uo[1]: "product_25" | ||
uo[2]: "product_26" | ||
uo[3]: "product_27" | ||
uo[4]: "product_28" | ||
uo[5]: "product_29" | ||
uo[6]: "product_30" | ||
uo[7]: "product_31" | ||
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# Bidirectional pins | ||
uio[0]: "ingress8" | ||
uio[1]: "ingress9" | ||
uio[2]: "ingress10" | ||
uio[3]: "ingress11" | ||
uio[4]: "ingress12" | ||
uio[5]: "ingress13" | ||
uio[6]: "ingress14" | ||
uio[7]: "ingress15" | ||
uio[0]: "product_16" | ||
uio[1]: "product_17" | ||
uio[2]: "product_18" | ||
uio[3]: "product_19" | ||
uio[4]: "product_20" | ||
uio[5]: "product_21" | ||
uio[6]: "product_22" | ||
uio[7]: "product_23" | ||
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# Do not change! | ||
yaml_version: 6 |
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