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feat: update project tt_um_micro_tiles_container_group2 from TinyTape…
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…out/tt08-micro-tiles-container-group2

Commit: 94dc894a789e7e3273e5077a11b4ea235b98b7aa
Workflow: https://github.com/TinyTapeout/tt08-micro-tiles-container-group2/actions/runs/10744374040
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@TinyTapeoutBot @urish
TinyTapeoutBot authored and urish committed Sep 6, 2024
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4 changes: 2 additions & 2 deletions projects/tt_um_micro_tiles_container_group2/commit_id.json
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
{
"app": "Tiny Tapeout tt08 587b6cb0",
"repo": "https://github.com/TinyTapeout/tt08-micro-tiles-container-group2",
"commit": "1b8c0854f47231e1a2c49132c84ff9ff96d80b87",
"workflow_url": "https://github.com/TinyTapeout/tt08-micro-tiles-container-group2/actions/runs/10739450455",
"commit": "94dc894a789e7e3273e5077a11b4ea235b98b7aa",
"workflow_url": "https://github.com/TinyTapeout/tt08-micro-tiles-container-group2/actions/runs/10744374040",
"sort_id": 1725630642709,
"openlane_version": "OpenLane2 2.0.8",
"pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"
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27 changes: 27 additions & 0 deletions projects/tt_um_micro_tiles_container_group2/docs/info.md
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Original file line number Diff line number Diff line change
Expand Up @@ -65,3 +65,30 @@ of 7SEG font states at the output.

None, just the standard Tiny Tapeout PCB.

## Project 2 - NCO
* Repo: https://github.com/gfg-development/tt-micro-tiles-nco
* Author: Gerrit Grutzeck
* Description: Micro tiles nummerical controlled oscillator, which generates a PDM stream of a sawtooth

### How it works
On `ui_in` the desired frequency is set. The hightest output frequency is the clock divided by $2^{21} / (2^8 - 1)$. The lowest possible frequency is the clock divided by $2^{21}$.
First a phase accumulator is used to generate the sawtooth. The resulting waveform is then converted into a PDM stream in a second stage.
This generated PDM datastream is output via `uo_out[7]`.

### How to test
Connect the audio Pmod to the output ports or any other low pass filter with a speaker to `uo_out[7]`.
Then configure the clock to a meaningfull frequency (e.g. 50 MHz for frequencies between 6 kHz and 24 Hz).
Finally set the `ui_in` pins to the desired frequency (= clk / $2^{21}$ * `ui_in`). After applying the reset, the sawtooth will be generated.

## Project 3 - Micro Maze
* Repo: https://github.com/htfab/micro-maze
* Author: htfab
* Description: A simple fixed maze game with 7-segment output

## How it works

The player can walk around the maze, showing the adjacent walls on the 7-segment display.

## How to test

Use the first four inputs to move up, down, left or right.
72 changes: 36 additions & 36 deletions projects/tt_um_micro_tiles_container_group2/stats/metrics.csv
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Original file line number Diff line number Diff line change
Expand Up @@ -10,14 +10,14 @@ synthesis__check_error__count,0
design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
design__max_fanout_violation__count__corner:nom_tt_025C_1v80,0
design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
power__internal__total,4.046745743835345e-05
power__switching__total,2.3532173145213164e-05
power__leakage__total,1.745988797985376e-09
power__total,6.400137499440461e-05
power__internal__total,4.0464161429554224e-05
power__switching__total,2.3569771656184457e-05
power__leakage__total,1.7383852135566258e-09
power__total,6.403567385859787e-05
clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.0
clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.0
timing__hold__ws__corner:nom_tt_025C_1v80,8.457853
timing__setup__ws__corner:nom_tt_025C_1v80,9.94586
timing__hold__ws__corner:nom_tt_025C_1v80,8.46102
timing__setup__ws__corner:nom_tt_025C_1v80,9.939017
timing__hold__tns__corner:nom_tt_025C_1v80,0.0
timing__setup__tns__corner:nom_tt_025C_1v80,0.0
timing__hold__wns__corner:nom_tt_025C_1v80,0.0
Expand All @@ -33,8 +33,8 @@ design__max_fanout_violation__count__corner:nom_ss_100C_1v60,0
design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.0
clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.0
timing__hold__ws__corner:nom_ss_100C_1v60,9.035491
timing__setup__ws__corner:nom_ss_100C_1v60,8.474111
timing__hold__ws__corner:nom_ss_100C_1v60,9.041263
timing__setup__ws__corner:nom_ss_100C_1v60,8.462856
timing__hold__tns__corner:nom_ss_100C_1v60,0.0
timing__setup__tns__corner:nom_ss_100C_1v60,0.0
timing__hold__wns__corner:nom_ss_100C_1v60,0.0
Expand All @@ -50,8 +50,8 @@ design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,0
design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.0
clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.0
timing__hold__ws__corner:nom_ff_n40C_1v95,8.193748
timing__setup__ws__corner:nom_ff_n40C_1v95,10.562642
timing__hold__ws__corner:nom_ff_n40C_1v95,8.195415
timing__setup__ws__corner:nom_ff_n40C_1v95,10.558708
timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
timing__hold__wns__corner:nom_ff_n40C_1v95,0.0
Expand All @@ -67,8 +67,8 @@ design__max_fanout_violation__count,0
design__max_cap_violation__count,0
clock__skew__worst_hold,0.0
clock__skew__worst_setup,0.0
timing__hold__ws,8.181328
timing__setup__ws,8.395441
timing__hold__ws,8.182369
timing__setup__ws,8.383325
timing__hold__tns,0.0
timing__setup__tns,0.0
timing__hold__wns,0.0
Expand Down Expand Up @@ -100,7 +100,7 @@ timing__drv__floating__pins,0
design__instance__displacement__total,0
design__instance__displacement__mean,0
design__instance__displacement__max,0
route__wirelength__estimated,5336.82
route__wirelength__estimated,5321.75
design__violations,0
design__instance__count__setup_buffer,0
design__instance__count__hold_buffer,0
Expand All @@ -109,22 +109,22 @@ antenna__violating__pins,1
route__antenna_violation__count,1
route__net,192
route__net__special,2
route__drc_errors__iter:1,156
route__wirelength__iter:1,6482
route__drc_errors__iter:2,32
route__wirelength__iter:2,6173
route__drc_errors__iter:3,23
route__wirelength__iter:3,6007
route__drc_errors__iter:1,128
route__wirelength__iter:1,6468
route__drc_errors__iter:2,45
route__wirelength__iter:2,6202
route__drc_errors__iter:3,33
route__wirelength__iter:3,6025
route__drc_errors__iter:4,0
route__wirelength__iter:4,6018
route__wirelength__iter:4,6020
route__drc_errors,0
route__wirelength,6018
route__vias,1068
route__vias__singlecut,1068
route__wirelength,6020
route__vias,1077
route__vias__singlecut,1077
route__vias__multicut,0
design__disconnected_pin__count,7
design__critical_disconnected_pin__count,0
route__wirelength__max,209.03
route__wirelength__max,210.68
timing__unannotated_net__count__corner:nom_tt_025C_1v80,55
timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
timing__unannotated_net__count__corner:nom_ss_100C_1v60,55
Expand All @@ -136,8 +136,8 @@ design__max_fanout_violation__count__corner:min_tt_025C_1v80,0
design__max_cap_violation__count__corner:min_tt_025C_1v80,0
clock__skew__worst_hold__corner:min_tt_025C_1v80,0.0
clock__skew__worst_setup__corner:min_tt_025C_1v80,0.0
timing__hold__ws__corner:min_tt_025C_1v80,8.438751
timing__setup__ws__corner:min_tt_025C_1v80,9.999144
timing__hold__ws__corner:min_tt_025C_1v80,8.440777
timing__setup__ws__corner:min_tt_025C_1v80,9.992782
timing__hold__tns__corner:min_tt_025C_1v80,0.0
timing__setup__tns__corner:min_tt_025C_1v80,0.0
timing__hold__wns__corner:min_tt_025C_1v80,0.0
Expand All @@ -155,8 +155,8 @@ design__max_fanout_violation__count__corner:min_ss_100C_1v60,0
design__max_cap_violation__count__corner:min_ss_100C_1v60,0
clock__skew__worst_hold__corner:min_ss_100C_1v60,0.0
clock__skew__worst_setup__corner:min_ss_100C_1v60,0.0
timing__hold__ws__corner:min_ss_100C_1v60,9.003592
timing__setup__ws__corner:min_ss_100C_1v60,8.567878
timing__hold__ws__corner:min_ss_100C_1v60,9.006213
timing__setup__ws__corner:min_ss_100C_1v60,8.556613
timing__hold__tns__corner:min_ss_100C_1v60,0.0
timing__setup__tns__corner:min_ss_100C_1v60,0.0
timing__hold__wns__corner:min_ss_100C_1v60,0.0
Expand All @@ -174,8 +174,8 @@ design__max_fanout_violation__count__corner:min_ff_n40C_1v95,0
design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.0
clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.0
timing__hold__ws__corner:min_ff_n40C_1v95,8.181328
timing__setup__ws__corner:min_ff_n40C_1v95,10.597659
timing__hold__ws__corner:min_ff_n40C_1v95,8.182369
timing__setup__ws__corner:min_ff_n40C_1v95,10.593604
timing__hold__tns__corner:min_ff_n40C_1v95,0.0
timing__setup__tns__corner:min_ff_n40C_1v95,0.0
timing__hold__wns__corner:min_ff_n40C_1v95,0.0
Expand All @@ -193,8 +193,8 @@ design__max_fanout_violation__count__corner:max_tt_025C_1v80,0
design__max_cap_violation__count__corner:max_tt_025C_1v80,0
clock__skew__worst_hold__corner:max_tt_025C_1v80,0.0
clock__skew__worst_setup__corner:max_tt_025C_1v80,0.0
timing__hold__ws__corner:max_tt_025C_1v80,8.476133
timing__setup__ws__corner:max_tt_025C_1v80,9.903157
timing__hold__ws__corner:max_tt_025C_1v80,8.476195
timing__setup__ws__corner:max_tt_025C_1v80,9.895711
timing__hold__tns__corner:max_tt_025C_1v80,0.0
timing__setup__tns__corner:max_tt_025C_1v80,0.0
timing__hold__wns__corner:max_tt_025C_1v80,0.0
Expand All @@ -212,8 +212,8 @@ design__max_fanout_violation__count__corner:max_ss_100C_1v60,0
design__max_cap_violation__count__corner:max_ss_100C_1v60,0
clock__skew__worst_hold__corner:max_ss_100C_1v60,0.0
clock__skew__worst_setup__corner:max_ss_100C_1v60,0.0
timing__hold__ws__corner:max_ss_100C_1v60,9.066138
timing__setup__ws__corner:max_ss_100C_1v60,8.395441
timing__hold__ws__corner:max_ss_100C_1v60,9.066339
timing__setup__ws__corner:max_ss_100C_1v60,8.383325
timing__hold__tns__corner:max_ss_100C_1v60,0.0
timing__setup__tns__corner:max_ss_100C_1v60,0.0
timing__hold__wns__corner:max_ss_100C_1v60,0.0
Expand All @@ -231,8 +231,8 @@ design__max_fanout_violation__count__corner:max_ff_n40C_1v95,0
design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.0
clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.0
timing__hold__ws__corner:max_ff_n40C_1v95,8.205956
timing__setup__ws__corner:max_ff_n40C_1v95,10.532553
timing__hold__ws__corner:max_ff_n40C_1v95,8.205779
timing__setup__ws__corner:max_ff_n40C_1v95,10.528255
timing__hold__tns__corner:max_ff_n40C_1v95,0.0
timing__setup__tns__corner:max_ff_n40C_1v95,0.0
timing__hold__wns__corner:max_ff_n40C_1v95,0.0
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8 changes: 4 additions & 4 deletions projects/tt_um_micro_tiles_container_group2/stats/synthesis-stats.txt
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Expand Up @@ -18,15 +18,15 @@
sky130_fd_sc_hd__nor2_2 1
sky130_fd_sc_hd__o41a_2 8
sky130_fd_sc_hd__or3_2 8
tt_um_micro_stub_3 1
tt_um_micro_stub_4 1
tt_um_htfab_micro_maze 1
tt_um_micro_gfg_development_nco 1
tt_um_micro_test 1
tt_um_wokwi_408272151035187201 1

Area for cell type \tt_um_micro_test is unknown!
Area for cell type \tt_um_wokwi_408272151035187201 is unknown!
Area for cell type \tt_um_micro_stub_3 is unknown!
Area for cell type \tt_um_micro_stub_4 is unknown!
Area for cell type \tt_um_micro_gfg_development_nco is unknown!
Area for cell type \tt_um_htfab_micro_maze is unknown!

Chip area for module '\tt_um_micro_tiles_container_group2': 773.241600

Binary file modified projects/tt_um_micro_tiles_container_group2/tt_um_micro_tiles_container_group2.gds
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94 changes: 47 additions & 47 deletions projects/tt_um_micro_tiles_container_group2/tt_um_micro_tiles_container_group2.lef
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Expand Up @@ -494,55 +494,55 @@ MACRO tt_um_micro_tiles_container_group2
LAYER li1 ;
RECT 2.760 2.635 155.480 106.165 ;
LAYER met1 ;
RECT 2.760 2.480 155.480 110.460 ;
RECT 2.760 2.480 155.480 108.760 ;
LAYER met2 ;
RECT 3.000 2.480 152.170 110.685 ;
RECT 3.000 2.480 153.550 111.365 ;
LAYER met3 ;
RECT 3.010 2.515 152.195 110.665 ;
LAYER met4 ;
RECT 31.370 110.120 33.030 111.170 ;
RECT 34.130 110.120 35.790 111.170 ;
RECT 36.890 110.120 38.550 111.170 ;
RECT 39.650 110.120 41.310 111.170 ;
RECT 42.410 110.120 44.070 111.170 ;
RECT 45.170 110.120 46.830 111.170 ;
RECT 47.930 110.120 49.590 111.170 ;
RECT 50.690 110.120 52.350 111.170 ;
RECT 53.450 110.120 55.110 111.170 ;
RECT 56.210 110.120 57.870 111.170 ;
RECT 58.970 110.120 60.630 111.170 ;
RECT 61.730 110.120 63.390 111.170 ;
RECT 64.490 110.120 66.150 111.170 ;
RECT 67.250 110.120 68.910 111.170 ;
RECT 70.010 110.120 71.670 111.170 ;
RECT 72.770 110.120 74.430 111.170 ;
RECT 75.530 110.120 77.190 111.170 ;
RECT 78.290 110.120 79.950 111.170 ;
RECT 81.050 110.120 82.710 111.170 ;
RECT 83.810 110.120 85.470 111.170 ;
RECT 86.570 110.120 88.230 111.170 ;
RECT 89.330 110.120 90.990 111.170 ;
RECT 92.090 110.120 93.750 111.170 ;
RECT 94.850 110.120 96.510 111.170 ;
RECT 97.610 110.120 99.270 111.170 ;
RECT 100.370 110.120 102.030 111.170 ;
RECT 103.130 110.120 104.790 111.170 ;
RECT 105.890 110.120 107.550 111.170 ;
RECT 108.650 110.120 110.310 111.170 ;
RECT 111.410 110.120 113.070 111.170 ;
RECT 114.170 110.120 115.830 111.170 ;
RECT 116.930 110.120 118.590 111.170 ;
RECT 119.690 110.120 121.350 111.170 ;
RECT 122.450 110.120 124.110 111.170 ;
RECT 125.210 110.120 126.870 111.170 ;
RECT 127.970 110.120 129.630 111.170 ;
RECT 130.730 110.120 132.390 111.170 ;
RECT 133.490 110.120 135.150 111.170 ;
RECT 136.250 110.120 137.910 111.170 ;
RECT 139.010 110.120 140.670 111.170 ;
RECT 141.770 110.120 143.430 111.170 ;
RECT 144.530 110.120 146.190 111.170 ;
RECT 147.290 110.120 150.585 111.170 ;
RECT 3.010 2.515 153.575 111.345 ;
LAYER met4 ;
RECT 31.370 110.120 33.030 111.345 ;
RECT 34.130 110.120 35.790 111.345 ;
RECT 36.890 110.120 38.550 111.345 ;
RECT 39.650 110.120 41.310 111.345 ;
RECT 42.410 110.120 44.070 111.345 ;
RECT 45.170 110.120 46.830 111.345 ;
RECT 47.930 110.120 49.590 111.345 ;
RECT 50.690 110.120 52.350 111.345 ;
RECT 53.450 110.120 55.110 111.345 ;
RECT 56.210 110.120 57.870 111.345 ;
RECT 58.970 110.120 60.630 111.345 ;
RECT 61.730 110.120 63.390 111.345 ;
RECT 64.490 110.120 66.150 111.345 ;
RECT 67.250 110.120 68.910 111.345 ;
RECT 70.010 110.120 71.670 111.345 ;
RECT 72.770 110.120 74.430 111.345 ;
RECT 75.530 110.120 77.190 111.345 ;
RECT 78.290 110.120 79.950 111.345 ;
RECT 81.050 110.120 82.710 111.345 ;
RECT 83.810 110.120 85.470 111.345 ;
RECT 86.570 110.120 88.230 111.345 ;
RECT 89.330 110.120 90.990 111.345 ;
RECT 92.090 110.120 93.750 111.345 ;
RECT 94.850 110.120 96.510 111.345 ;
RECT 97.610 110.120 99.270 111.345 ;
RECT 100.370 110.120 102.030 111.345 ;
RECT 103.130 110.120 104.790 111.345 ;
RECT 105.890 110.120 107.550 111.345 ;
RECT 108.650 110.120 110.310 111.345 ;
RECT 111.410 110.120 113.070 111.345 ;
RECT 114.170 110.120 115.830 111.345 ;
RECT 116.930 110.120 118.590 111.345 ;
RECT 119.690 110.120 121.350 111.345 ;
RECT 122.450 110.120 124.110 111.345 ;
RECT 125.210 110.120 126.870 111.345 ;
RECT 127.970 110.120 129.630 111.345 ;
RECT 130.730 110.120 132.390 111.345 ;
RECT 133.490 110.120 135.150 111.345 ;
RECT 136.250 110.120 137.910 111.345 ;
RECT 139.010 110.120 140.670 111.345 ;
RECT 141.770 110.120 143.430 111.345 ;
RECT 144.530 110.120 146.190 111.345 ;
RECT 147.290 110.120 150.585 111.345 ;
RECT 30.655 106.720 150.585 110.120 ;
RECT 30.655 15.135 34.600 106.720 ;
RECT 37.000 15.135 42.600 106.720 ;
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