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Test setup for vhdl_testbench #23

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merged 11 commits into from
Jun 23, 2023
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Rename methods and properties verilog_ -> rtl_
mkosunen committed May 31, 2023
commit 20db444fc46d7bcc2d538fcc8eedfdd022a0b2b0
4 changes: 2 additions & 2 deletions inverter/__init__.py
Original file line number Diff line number Diff line change
@@ -264,10 +264,10 @@ def define_io_conditions(self):

'''
# Input A is read to verilog simulation after 'initdone' is set to 1 by controller
self.iofile_bundle.Members['A'].verilog_io_condition='initdone'
self.iofile_bundle.Members['A'].rtl_io_condition='initdone'
# Output is read to verilog simulation when all of the outputs are valid,
# and after 'initdone' is set to 1 by controller
self.iofile_bundle.Members['Z'].verilog_io_condition_append(cond='&& initdone')
self.iofile_bundle.Members['Z'].rtl_io_condition_append(cond='&& initdone')

if __name__=="__main__":
import argparse