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TheLeopardsH committed Jan 22, 2020
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22 changes: 22 additions & 0 deletions ALU.v
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module ALU(input [31:0] a,b,
input [3:0] ALUop,
output reg[31:0] ALUOut,
output reg over);// 0 indicate no overflow
always @(*)
begin
case (ALUop)
4'b00_00: ALUOut=a+b;
4'b00_01: ALUOut=a-b;
4'b01_00: ALUOut=a&b;
4'b01_01: ALUOut=a|b;
4'b01_10: ALUOut=a^b;
4'b10_00: ALUOut=a<<b[4:0];//left shift logical
4'b10_10: ALUOut=a>>b[4:0];//right shift logical
4'b10_11: ALUOut=$signed(a)>>>$signed(b[4:0]);//arithmetic right shift
4'b11_00: ALUOut=$signed(a) < $signed(b)? 32'b1:32'b0;//set less than
4'b11_01: ALUOut=a < b ? 32'b1:32'b0;//set less than unsigned
endcase
over<=0;
end
endmodule
31 changes: 31 additions & 0 deletions ALU.v.bak
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//Note a and b in terms of shift in logical unit try to change them in ALU via contril unit.I corrected them in right way
//auipcis not added
// removement of nor
module ALU(input [31:0] a,b,
input [3:0] ALUop,
output reg[31:0] ALUOut,
output reg over);// 0 indicate no overflow
always @(*)
begin
case (ALUop)
4'b00_00: ALUOut=a+b;
4'b00_01: ALUOut=a-b;
4'b00_10: ALUOut={b[31:12],12'b0};//lui
//missing
4'b01_00: ALUOut=a&b;
4'b01_01: ALUOut=a|b;
4'b01_10: ALUOut=a^b;
//AUIPC 4'b01_11: ALUOut=a+{b[31:12],12b'0};//**here PC comes as a and immediate as b AUIPC(NO NOR)check PC selection in control unit
4'b10_00: ALUOut=a<<b[4:0];//left shift logical
//missing
4'b10_10: ALUOut=a>>b[4:0];//right shift logical(my rule mistake happened here]
4'b10_11: ALUOut=$signed(a)>>>$signed(b[4:0]);//arithmetic right shift
4'b11_00: ALUOut=$signed(a) < $signed(b)? 32'b1:32'b0;//set less than
4'b11_01: ALUOut=a < b ? 32'b1:32'b0;//set less than unsigned
//missing
//missing
endcase
over<=0;
end
endmodule
134 changes: 134 additions & 0 deletions Control_E.v
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`include"defination.v"


module Control_ID(input [31:0] instr,//basically this module is for signed extension selections

output reg PCsel,

output reg [1:0] extOp);//ext tells which immediate to choose signed or unsigned

always @(*)
begin
PCsel <= 1'b0;
//handle extOp
//checkif following are true for signed extension
//on cheatsheet it is written immediate fields are sign extented
//confusion in ALU I am also taking signed operations whats their meaning may be nothing to notice
//what about 'a' if we put the number in a what about it does compiler would put sign extension or not just check
if(`LB || `LH || `LW || `ADDI || `SLTI || `XORI ||`ORI || `ANDI ||`SLLI || `SRLI || `SRAI )
extOp <= 2'b01;
else if (`SB || `SH || `SW)
extOp <=2'b11;
else
extOp <= 2'b00;

end // always @ (*)
endmodule // ConTrol_ID

//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//Also b selection is from here also
module Control_E(input [31:0] instr,
output reg [3:0] ALUOp,
output reg BSel);

always @(*)
begin
//handle ALUOp
if(`SUB)
ALUOp = 4'b00_01;
else if(`AND || `ANDI)
ALUOp = 4'b01_00;
else if(`OR || `ORI)
ALUOp = 4'b01_01;
else if(`XOR || `XORI)
ALUOp = 4'b01_10;
else if(`SLL || `SLLI)
ALUOp = 4'b10_00;
else if(`SRL || `SRLI)
ALUOp = 4'b10_10;
else if(`SRA || `SRAI)
ALUOp = 4'b10_11;
else if(`SLT || `SLTI)
ALUOp = 4'b11_00;
else if(`SLTU || `SLTIU)
ALUOp = 4'b11_01;
else //others use add
ALUOp = 4'b00_00;

if(`LB || `LBU || `LH || `LHU || `LW ||`ADDI || `ANDI || `ORI || `XORI || `SLTI || `SLTIU || `SLLI || `SRLI || `SRAI ||`SB || `SH || `SW)
BSel = 1'b1;

else
BSel = 1'b0;//for selecting b register

end
endmodule // Control_IE

//Memory write for store instructions based on byte or half word or word level store
//check how store instruction works otherwise destination can go wrong
module Control_M(input [31:0] instr,
output reg memWr,
output reg [1:0] BEextOp);
always @(*)
begin
if(`SB || `SH || `SW)
memWr = 1;
else
memWr = 0;

if(`SH)
BEextOp = 2'b10;
else if(`SB)
BEextOp = 2'b11;
else
BEextOp = 2'b00;
end

endmodule // Control_M

//for writing to mem
module Control_W(input [31:0] instr,
output reg WRSel,
output reg WDSel,
output reg regWr,
output reg [2:0] WBextOp);
always @(*)
begin
if(`LBU)
WBextOp = 3'b001;
else if(`LB)
WBextOp = 3'b010;
else if(`LHU)
WBextOp = 3'b011;
else if(`LH)
WBextOp = 3'b100;
else
WBextOp = 3'b000;

if(`ADD || `SUB || `SLT || `SLTU || `SLL || `SRL || `SRA || `AND || `OR || `XOR) //r-r cal and MF
begin
regWr <= 1'b1;
WRSel <= 1'b0;//RD
WDSel <= 1'b0;//ALU
end
else if(`LB || `LBU || `LH || `LHU || `LW) //load
begin
regWr <= 1'b1;
WRSel <= 1'b0;//RD
WDSel <= 1'b1; //rdata
end
else if(`ADDI || `ANDI || `ORI || `XORI || `SLTI || `SLTIU) //r-i cal
begin
regWr <= 1'b1;
WRSel <= 1'b0;//
WDSel <= 1'b0;//ALU
end
else //default maybe for Store instructions msitake here
begin
regWr <= 1'b0;
WRSel <= 1'b0;//********* converted from 1 to 0 as i think RD is always this
WDSel <= 1'b0;
end //
end // always @ begin

endmodule // Control_W
46 changes: 46 additions & 0 deletions Control_E.v.bak
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`include"defination.v"
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//Also b selection is from here also
module Control_E(input [31:0] instr,
output reg [3:0] ALUOp,
//output reg ASel, NOT NEEDED CHECK DOWN
output reg [1:0] BSel);//**** need to change 1 bit to 2 bit in pipeline

always @(*)
begin
//handle ALUOp
if(`LUI)
ALUOp = 4'b00_10;
else if(`SUB)
ALUOp = 4'b00_01;
else if(`AND || `ANDI)
ALUOp = 4'b01_00;
else if(`OR || `ORI)
ALUOp = 4'b01_01;
else if(`XOR || `XORI)
ALUOp = 4'b01_10;
else if(`SLL || `SLLI)
ALUOp = 4'b10_00;
else if(`SRL || `SRLI)
ALUOp = 4'b10_10;
else if(`SRA || `SRAI)
ALUOp = 4'b10_11;
else if(`SLT || `SLTI)
ALUOp = 4'b11_00;
else if(`SLTU || `SLTIU)
ALUOp = 4'b11_01;
else //others use add
ALUOp = 4'b00_00;

if(`LB || `LBU || `LH || `LHU || `LW ||`ADDI || `ANDI || `ORI || `XORI || `SLTI || `SLTIU || `SLLI || `SRLI || `SRAI)
BSel = 2'b00;

else if ( `LUI )
BSel = 2'b01;
else if ( `SB || `SH || `SW )
BSel = 2'b10;
else
BSel = 2'b11;//for selecting b register

end
endmodule // Control_IE
16 changes: 16 additions & 0 deletions EXT.v
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module EXT(input [31:0] immIn,
input [1:0] ExtOp,
output reg [31:0] immOut);//**need to change in pipeline immediate
always @(ExtOp or immIn)
begin
if (ExtOp==2'b11)
immOut <={{20{immIn[31]}},immIn[31:25],immIn[11:7]};
else if(ExtOp==2'b01)
immOut <= {{20{immIn[31]}},immIn[31:20]};
else
immOut <= {20'b0,immIn[31:20]};
end

endmodule // ext
9 changes: 9 additions & 0 deletions EXT.v.bak
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module EXT(input [11:0] immIn,
input ExtOp,
output reg [31:0] immOut);//**need to change in pipeline immediate
always @(ExtOp or immIn)
if(ExtOp)
immOut <= {{20{immIn[11]}},immIn[11:0]};
else
immOut <= {20'b0,immIn[11:0]};
endmodule // ext
125 changes: 125 additions & 0 deletions HazardUnit.v
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`include "defination.v"
module StallUnit(input reset,
input [31:0] instr_D,instr_E,instr_M,
output reg stall);
//FOR MEMORY STORE WE ALWAYS HAVE RS2 DESTINATION
always @ (*)
begin
if(reset==1'b0)
stall<=1'b0;
else if(load(instr_E))
begin
if(cal_r(instr_D) && instr_E[`RD] == instr_D[`RS2])
stall <= 1'b1;//**correct
else if((cal_r(instr_D) || cal_i(instr_D) || load(instr_D) || store(instr_D)) && instr_E[`RD] == instr_D[`RS1])
stall <= 1'b1;//**wrong making everything wrong
else
stall <= 1'b0;
end // if (load(instr_E))
else if(cal_i(instr_E)) //cal_i_E
stall <= 1'b0;
else if(cal_r(instr_E) && instr_E[`RD] != 5'b0 )
stall <= 1'b0;
else if(load(instr_M))
stall <= 1'b0;
else
stall <= 1'b0;
end // always @ begin

function load;
input [31:0] instr ;
load = (`LB || `LBU || `LH || `LHU || `LW);
endfunction // StallUnit

function cal_r;//include sll srl sra
input [31:0] instr;
cal_r = (`ADD || `SUB || `SLT || `SLTU || `SLL || `SRL || `SRA || `AND || `OR || `XOR);
endfunction // StallUnit

function cal_i;
input [31:0] instr;
cal_i = (`ADDI || `ORI || `XORI || `SLTI || `SLTIU || `SLLI||`SRLI||`SRAI||`ANDI);
endfunction // StallUnit

function store;
input [31:0] instr;
store = (`SB || `SH || `SW);
endfunction // StallUnit

endmodule // StallUnit



module HazardUnit(input [31:0] instr_D,instr_E,instr_M,instr_W,
output reg [1:0] FowardRS1E,FowardRS2E,//RSD=DECODING INSTRUCTION NEED OF RS1 SO FORWARD AND ALSO SAMEFOR OTHERS
output reg FowardRDM);





always @(*) //for Foward RS1E
//between memory and execute for rs1
//if(cal_r(instr_E) || cal_i(instr_E) || load(instr_E) || store(instr_E) || )//cal_i cal_r lw sw E

if((cal_r(instr_M) && instr_M[`RD] != 5'b0) && instr_M[`RD] == instr_E[`RS1]) //cal_r M **RS2 to RD
FowardRS1E <= 2'b01;
else if(cal_i(instr_M) && instr_M[`RD] == instr_E[`RS1]) //cal_i M
FowardRS1E <= 2'b01;
else if((cal_r(instr_W) && instr_W[`RD] != 5'b0) && instr_W[`RD] == instr_E[`RS1]) //cal_r W
FowardRS1E <= 2'b11;
else if(cal_i(instr_W) && instr_W[`RD] == instr_E[`RS1]) //cal_i W
FowardRS1E <= 2'b11;
else if(load(instr_W) && instr_W[`RD] == instr_E[`RS1]) //load W****IMP FOR LOAD
FowardRS1E <= 2'b11;
else
FowardRS1E <= 2'b00;


always @(*) //for Foward RS2E
//between memory/WRITE TO REGISTER and execute for for RS2
//if(cal_r(instr_E) || store(instr_E) //cal_i sw E
if((cal_r(instr_M) && instr_M[`RD] != 5'b0) && instr_M[`RD] == instr_E[`RS2]) //cal_r M
FowardRS2E <= 2'b01;
else if(cal_i(instr_M) && instr_M[`RD] == instr_E[`RS2]) //cal_i M
FowardRS2E <= 2'b01;
else if((cal_r(instr_W) && instr_W[`RD] != 5'b0 ) && instr_W[`RD] == instr_E[`RS2]) //cal_r W
FowardRS2E <= 2'b11;
else if(cal_i(instr_W) && instr_W[`RD] == instr_E[`RS2]) //cal_i W
FowardRS2E <= 2'b11;
else if(load(instr_W) && instr_W[`RD] == instr_E[`RS2]) //load W
FowardRS2E <= 2'b11;
else
FowardRS2E <= 2'b00;

always @(*) //for Foward RDM
//BETWEEN MEMORY AND WRITE TO REGISTER
//if(store(instr_M)) //sw M
if((cal_r(instr_W) && instr_W[`RD] != 5'b0 ) && instr_W[`RD] == instr_M[`RS2]) //cal_r W
FowardRDM <= 1'b1;
else if((cal_i(instr_W) || load(instr_W)) && instr_W[`RD] == instr_M[`RS2]) //cal_i W
FowardRDM <= 1'b1;
else
FowardRDM <= 1'b0;

function load;
input [31:0] instr;
load = (`LB || `LBU || `LH || `LHU || `LW);
endfunction // StallUnit

function cal_r;//include sll srl sra
input [31:0] instr;
cal_r = (`ADD || `SUB || `SLT || `SLTU || `SLL || `SRL || `SRA || `AND || `OR || `XOR);
endfunction // StallUnit

function cal_i;
input [31:0] instr;
cal_i = (`ADDI || `ORI || `XORI || `SLTI || `SLTIU||`SLLI||`SRLI||`SRAI||`ANDI);
endfunction // StallUnit

function store;
input [31:0] instr;
store = (`SB || `SH || `SW);
endfunction // StallUnit

endmodule // HazardUnit
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