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vtr_flow/tasks/regression_tests/parmys_reg_basic/freecores/config/golden_results.txt
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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time | ||
k6_frac_N10_frac_chain_mem32K_40nm.xml aes_cipher.v common 18.53 parmys 449.26 MiB -1 -1 15.62 460044 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 | ||
k6_frac_N10_frac_chain_mem32K_40nm.xml aes_inv_cipher.v common 18.57 parmys 456.23 MiB -1 -1 16.18 467176 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 | ||
k6_frac_N10_frac_chain_mem32K_40nm.xml 8051.v common 9.39 parmys 72.02 MiB -1 -1 7.45 73744 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 | ||
k6_frac_N10_frac_chain_mem32K_40nm.xml ethmac.v common 10.80 parmys 105.79 MiB -1 -1 8.57 108328 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 | ||
k6_frac_N10_frac_chain_mem32K_40nm.xml mips_16.v common 2.22 parmys 23.50 MiB -1 -1 0.48 24064 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 | ||
k6_frac_N10_frac_chain_mem32K_40nm.xml xtea.v common 2.60 parmys 32.87 MiB -1 -1 0.78 33660 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 | ||
k6_frac_N10_frac_chain_mem32K_40nm.xml aes_cipher.v common 18.53 parmys 449.26 MiB -1 -1 15.62 460044 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 | ||
k6_frac_N10_frac_chain_mem32K_40nm.xml aes_inv_cipher.v common 18.57 parmys 456.23 MiB -1 -1 16.18 467176 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 | ||
k6_frac_N10_frac_chain_mem32K_40nm.xml 8051.v common 9.39 parmys 72.02 MiB -1 -1 7.45 73744 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 | ||
k6_frac_N10_frac_chain_mem32K_40nm.xml ethmac.v common 10.80 parmys 105.79 MiB -1 -1 8.57 108328 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 | ||
k6_frac_N10_frac_chain_mem32K_40nm.xml mips_16.v common 2.22 parmys 23.50 MiB -1 -1 0.48 24064 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 | ||
k6_frac_N10_frac_chain_mem32K_40nm.xml xtea.v common 2.60 parmys 32.87 MiB -1 -1 0.78 33660 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 |
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