International Hellenic University (IHU) Thessaloniki, Sindos
This circuit is a Pseudo Random Number Generator (PRNG)
A pseudorandom number generator (PRNG), also known as a deterministic random bit generator (DRBG), is an algorithm for generating a sequence of numbers whose properties approximate the properties of sequences of random numbers. The PRNG-generated sequence is not truly random, because it is completely determined by an initial value, called the PRNG's seed (which may include truly random values).
There are also Real Random Number Generator (TRNG)
is a device that generates random numbers from a physical process capable of producing entropy (in other words, the device always has access to a physical entropy source)
-In this project as source of pseudo-randomness we used 2 LFSR's. One that works with 8-bit and one with 16-bit. The circuit don't have input data, just 1 clock and 1 enable pin. The output will be on two 7 segment displays, so 14 output pins.
-The 16-bit LFSR produces the input of a 16-to-8 multiplexer and the 8-bit LFSR produces the selection bits of 16-to-8 multiplexer.
-The 16-to-8 multiplexer is implemented by 8 2-to-1 multiplexers.
-In the final stage the data are converted to BCD format and are shown in two 7-segment displays. The format is hexadecimal.
| # | Input | Output |
|---|---|---|
| 0 | CLK | Segment0 A |
| 1 | EN | Segment0 B |
| 2 | RST_N | Segment0 C |
| 3 | NONE | Segment0 D |
| 4 | NONE | Segment0 E |
| 5 | NONE | Segment0 F |
| 6 | NONE | Segment0 G |
| 7 | NONE | Segment1 A |
| 8 | NONE | Segment1 B |
| 9 | NONE | Segment1 C |
| 10 | NONE | Segment1 D |
| 11 | NONE | Segment1 E |
| 12 | NONE | Segment1 F |
| 13 | NONE | Segment1 G |
This is the 2d photo of gds file of chip
Test done in FPGA Cyclone V De1-Soc Board
The idea for the implementation of this cell came from the paper: Dopingless Transistor Based Hybrid Oscillator Arbiter Physical Unclonable Function
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@@ -25,12 +78,11 @@ After that, the action uses the open source ASIC tool called [OpenLane](https://
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