adding layouts with DRC issues

[newmansc2]

These layouts have DRC issues that I wasn't able to resolve. Committing anyway in case they can be accepted.

I realize it is past the deadline and these layouts therefore are unlikely to be accepted in any case.

[lukasc-ubc]

For the disks: it would be better to create a PCell. @newmansc2 would you like to write such a PCell and contribute it the PDK?

For the CDCs, indeed, the ports are so close together that it makes it impossible to connect waveguides. We need some sort of IO cell, @mustafacc? Perhaps a separate PCell for IO? Or an option on the CDC to add the ports. I guess we already have the EBeam.contra_directional_coupler cell which does the same thing as EBeam_Beta.Contra_DC cell, so should we remove the Beta one?

[newmansc2]

@lukasc-ubc thanks for the feedback. I would like to contribute by making a disk resonator PCell. I don't currently know how to do this, but this would be a good learning opportunity. I'll put it on my to-do list.

[lukasc-ubc]

My suggestion is:

• look at the wg_heater or ebeam_dc_halfring_straight PCell in the EBeam library to see how to create a PCell.
• KLayout has a native PCell for a disk (see screenshot)
• look at ring_doublebus in the EBeam_PDK library to see how to instantiate a PCell inside a PCell

Feel free to start a PR and I can give you feedback.