Arm basics, minor changes in riscv #160
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Major CodeGen cleanup; most static globals move into the CodeGen object.
Only "return 0;", no registers, no encoding, but yah gotta start somewhere
Parser bug fref in args Some new test cases.
Add calling convention basics to X86; con+ret RegMasks. GCM computes CFG for all users. Drop unused MultiUse. Pick up reg-pressure aware ListScheduler. Re-layout CodeGen file to get code & data chunks nearer each other. minor Ary extension
InstSel handles folding 2+ ideal ops into 1 machine op
Bool,If,CProj,Region,Phi Handle 2-op expansions Shuffle instSel graph walk back again.
mul-by-small constant opt. Some utilities.
Change inst sel walk again to pre-order, to set an early visit bit to stop cycles. CFGNode copies dom/loop info. Cmp not-immediate form. Ret/Fun lazy updates
* left shift codegen basic * sar codegen basic * merge * some basic ops * addf * divf, subf, mulf * rsp allowed in bitwise input, not output * formatting * left shift codegen basic * sar codegen basic * merge * some basic ops * addf * divf, subf, mulf * rsp allowed in bitwise input, not output * formatting * Remove non-exsting FP+imm ops * Handle first loop Change inst sel walk again to pre-order, to set an early visit bit to stop cycles. CFGNode copies dom/loop info. Cmp not-immediate form. Ret/Fun lazy updates * float ops without imm values * merge * merge * inst select for new struct allocation * left shift codegen basic * sar codegen basic * merge * some basic ops * addf * divf, subf, mulf * rsp allowed in bitwise input, not output * formatting * Remove non-exsting FP+imm ops * left shift codegen basic * sar codegen basic * merge * some basic ops * addf * divf, subf, mulf * rsp allowed in bitwise input, not output * formatting * float ops without imm values * merge * merge * Rebased on ch 19 * Update tests --------- Co-authored-by: Cliff Click <[email protected]>
alpha-sort helper fcns implicit test vs zero/null
asm print works on ideal nodes for all tests
Drop New taking inits; just follow with initializing stores. Simplifies inst selelection which otherwise needs to undo this optimization and emit following init stores. Basic load/store for now, op-to-mem comes later add same becomes Shl by 1. Drop DivF-immiedate
* merge2 * merge3
ld/st get size (but not signed/unsigned) Add unsigned LT for later range checks.
Hels15
changed the title
cliffclick
reviewed
Feb 16, 2025
| import java.lang.StringBuilder; | ||
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| public class CastX86 extends MachConcreteNode implements MachNode{ |
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No CastX86, Cast is just a type assertion. Use the normal CastNode.
| assertEquals("return (ori,(mov,arg));", code._stop.toString()); | ||
| CodeGen code_x86 = new CodeGen("return arg | 2;").parse().opto().typeCheck().instSelect("x86_64_v2", "SystemV").GCM().localSched().regAlloc(); | ||
| CodeGen code_riscv = new CodeGen("return arg | 2;").parse().opto().typeCheck().instSelect("riscv", "SystemV").GCM().localSched().regAlloc(); | ||
| CodeGen code_arm = new CodeGen("return arg | 2;").parse().opto().typeCheck().instSelect("riscv", "SystemV").GCM().localSched().regAlloc(); |
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Probably meant "arm" here and below
| @@ -13,7 +13,7 @@ public class ParmRISC extends ParmNode implements MachNode { | |||
| ParmRISC(ParmNode parm) { | |||
| super(parm); | |||
| // Assume int | |||
| _rmask = riscv.callInMaskInt(_idx); | |||
| _rmask = riscv.callInMask(_idx); | |||
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ALl the callInMask have a TFP added in ch20_reg now, you'll need to rebase probably.
| static RegMask callInMaskFloat(int idx) { | ||
| return CALLINMASK_RISCV_FLOAT[idx]; | ||
| } | ||
| // static RegMask[] CALLINMASK_RISCV_FLOAT = new RegMask[] { |
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I dropped all the callInInt versions in favor of callInMask versions.
Also hacked in float regs based on TypeFunPtr
| public static int X16 = 16, X17 = 17, X18 = 18, X19 = 19, X20 = 20, X21 = 21, X22 = 22, X23 = 23; | ||
| public static int X24 = 24, X25 = 25, X26 = 26, X27 = 27, X28 = 28, X29 = 29, X30 = 30; | ||
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| public static int FLAGS = 31; |
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Unique register numbers for all. FLAGS==31 and D0==31 are not allowed
Also, RegMask currently only supports 64 bits. This is an internal limitation... will need to be lifted in the future, but probably also means creating a RegMask via a bit-mask has 64-bit limitiations.
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CastNode for x86
Added small explanation for addressing modes(Load, Store)
Worked on ARM port(Muli, Load, Store, Jmp) etc...
ARM callingarg-mask cleanup