RISC-V basic isel #156

Hels15 · 2025-02-08T22:52:16Z

Added basic risc0-v instruction selection.
Address modes are not complete and are mostly just copied from x86-64 to get a fast complete version.
Added float calling conv for both systemV and win64
Immediate bitwise ops for both riscv and x86-64.
Many minor cleanups

Major CodeGen cleanup; most static globals move into the CodeGen object.

Only "return 0;", no registers, no encoding, but yah gotta start somewhere

Parser bug fref in args Some new test cases.

Add calling convention basics to X86; con+ret RegMasks. GCM computes CFG for all users. Drop unused MultiUse. Pick up reg-pressure aware ListScheduler. Re-layout CodeGen file to get code & data chunks nearer each other. minor Ary extension

InstSel handles folding 2+ ideal ops into 1 machine op

Bool,If,CProj,Region,Phi Handle 2-op expansions Shuffle instSel graph walk back again.

mul-by-small constant opt. Some utilities.

Change inst sel walk again to pre-order, to set an early visit bit to stop cycles. CFGNode copies dom/loop info. Cmp not-immediate form. Ret/Fun lazy updates

* left shift codegen basic * sar codegen basic * merge * some basic ops * addf * divf, subf, mulf * rsp allowed in bitwise input, not output * formatting * left shift codegen basic * sar codegen basic * merge * some basic ops * addf * divf, subf, mulf * rsp allowed in bitwise input, not output * formatting * Remove non-exsting FP+imm ops * Handle first loop Change inst sel walk again to pre-order, to set an early visit bit to stop cycles. CFGNode copies dom/loop info. Cmp not-immediate form. Ret/Fun lazy updates * float ops without imm values * merge * merge * inst select for new struct allocation * left shift codegen basic * sar codegen basic * merge * some basic ops * addf * divf, subf, mulf * rsp allowed in bitwise input, not output * formatting * Remove non-exsting FP+imm ops * left shift codegen basic * sar codegen basic * merge * some basic ops * addf * divf, subf, mulf * rsp allowed in bitwise input, not output * formatting * float ops without imm values * merge * merge * Rebased on ch 19 * Update tests --------- Co-authored-by: Cliff Click <[email protected]>

alpha-sort helper fcns implicit test vs zero/null

asm print works on ideal nodes for all tests

Drop New taking inits; just follow with initializing stores. Simplifies inst selelection which otherwise needs to undo this optimization and emit following init stores. Basic load/store for now, op-to-mem comes later add same becomes Shl by 1. Drop DivF-immiedate

* merge2 * merge3

ld/st get size (but not signed/unsigned) Add unsigned LT for later range checks.

Common addressing mode print LEA can skip a base

A bunch of mem op patterns are missing, hopefully they are just cut-n-paste from the existing patterns.

Minor README updates

narrowing stores can bypass an AndMask Array length loads do not need control Some missing print info

at least for MemAdd

load-after-store zero/sign-extends if the store is truncating

cliffclick · 2025-02-08T23:11:46Z

No base+scaled+offset addressing modes in risc5.
No op+mem modes, i.e. cmp-vs-memory or add-from-memory or add-to-memory.
Please remove these non-existent matches.

cliffclick

Need a way to ld/st FP regs.
Ld & St need to extend MemOp.
Remove dead Lea.
Everything else is mostly cosmetic

cliffclick · 2025-02-09T19:28:03Z

chapter19/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java

+    // Using ABI names instead of register names
+    public static int ZERO =  0,  RA =  1,  SP =  2,  GP =  3,  TP =  4,  T0 =  5,  T1 =  6,  T2 =  7;
+    public static int s0   =  8,  s1 =  9,  A0 = 10,  A1 = 11,  A2 = 12,  A3 = 13,  A4 = 14,  A5 = 15;
+    public static int A6   = 16,  A7 = 17,  S2 = 18,  S3 = 19,  S4 = 20,  S5 = 21,  s6 = 22,  S7 = 23;


Capitalization of s0, s1, s7

cliffclick · 2025-02-09T19:28:38Z

chapter19/src/main/java/com/seaofnodes/simple/node/cpus/riscv/LoadRISC.java

+import com.seaofnodes.simple.type.TypeInteger;
+import java.io.ByteArrayOutputStream;
+
+public class LoadRISC extends MachConcreteNode implements MachNode{


Must extend MemOpNode; e.g. GCM uses this to insert anti-deps.

cliffclick · 2025-02-09T19:29:33Z

chapter19/src/main/java/com/seaofnodes/simple/node/cpus/riscv/LoadRISC.java

+        return riscv.RMASK;
+    }
+    // Register mask allowed as a result.  0 for no register.
+    @Override public RegMask outregmap() { return riscv.RMASK; }


How do we load into a float/FMask ?
2 different kinds of loads (one GPR, on FRegs?) or the same load but encoded differently (needs another encoding bit to tell 32 GPRs from 32 FPRs) ?

cliffclick · 2025-02-09T19:30:07Z

chapter19/src/main/java/com/seaofnodes/simple/node/cpus/riscv/StoreRISC.java

+
+
+// sw rs2,offset(rs1)
+public class StoreRISC extends MachConcreteNode implements MachNode {


Same-same Load; need to extend MemOpNode to pick up e.g. anti-deps.
Need a way to store FPRs.

cliffclick · 2025-02-09T19:30:31Z

chapter19/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java

+    private Node add(AddNode add) {
+        Node rhs = add.in(2);
+        if( rhs instanceof ConstantNode off && off._con instanceof TypeInteger toff ) {
+            if( toff.value()==0 ) return add;


Never see a 0 here, cleaned out by peeps earlier

cliffclick · 2025-02-09T19:32:11Z

chapter19/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java

+    }
+
+    private Node and(AndNode and) {
+        if( and.in(2) instanceof ConstantNode con && con._con instanceof TypeInteger ti )


Lower priority comment. Since add,and,or,xor,sub,mul,div, etc all look very similar, would like to see them boilerplated the same (or a some kind of helper fcn). Currently e.g. add has a rhs = add.in(2); if( rhs... whereas and just uses if( and.in(2)....

cliffclick · 2025-02-09T19:34:02Z

chapter19/src/main/java/com/seaofnodes/simple/node/cpus/riscv/LeaRISC.java

+import com.seaofnodes.simple.node.*;
+import java.io.ByteArrayOutputStream;
+
+public class LeaRISC extends MachConcreteNode implements MachNode {


Not used, delete ?

cliffclick

Looks good

cliffclick and others added 30 commits January 20, 2025 10:02

Initial push

8c2554d

Major CodeGen cleanup; most static globals move into the CodeGen object.

Minor progress bug with mutual recursion

92bc403

Add test from pr#148

a397ec8

First cut x86 "port"

813f23b

Only "return 0;", no registers, no encoding, but yah gotta start somewhere

Update README.md

2cfeb92

Update README.md

fa17a74

Update ListScheduler.java

95dce74

command line launcher for simple

c11815a

Parser bug fref in args Some new test cases.

ASM Printer

0c90c8c

InstSel handles folding 2+ ideal ops into 1 machine op

handle instSel for some control flow

ef1b9fd

Bool,If,CProj,Region,Phi Handle 2-op expansions Shuffle instSel graph walk back again.

Basic if-block inst selects and asm prints

20777fc

Add mul-by-coinstant to shift

3ce7fac

left shift codegen basic

01013d5

exclude RSP from *write* mask

62de8eb

2-arg add (not immediate)

e8c9e1e

mul-by-small constant opt. Some utilities.

Handle first loop

81bd158

Change inst sel walk again to pre-order, to set an early visit bit to stop cycles. CFGNode copies dom/loop info. Cmp not-immediate form. Ret/Fun lazy updates

inst select for new struct allocation

1bbb409

cleanup after merge

5eeef9f

alpha-sort helper fcns implicit test vs zero/null

Add LEA op

67c326e

asm print works on ideal nodes for all tests

Minor cleanup lea

53f2d26

merge2

73b7e87

merge3

446f7f2

GCM for float ops fixed, other cleanup - small extensions

57abd4b

call setup

d6ec46c

extended ch13, 14,15,16 (SeaOfNodes#153)

2b90949

* merge2 * merge3

Fix a few minor fuzzer bugs

3ff5bfc

Force array layout

f605577

ld/st get size (but not signed/unsigned) Add unsigned LT for later range checks.

Hels15 and others added 17 commits February 5, 2025 17:59

pulled

0f6147e

Add CmpMem form

1b30bba

Common addressing mode print LEA can skip a base

Add a AddFMemX86

7cced10

A bunch of mem op patterns are missing, hopefully they are just cut-n-paste from the existing patterns.

Docs

54ab71d

XMM reg mask fix

ba2130b

Minor README updates

Allow inverted cmp/mem

313686d

narrowing stores can bypass an AndMask Array length loads do not need control Some missing print info

Support "*ptr op= val"

9fbed8a

at least for MemAdd

missed golden rule update

370f0e2

Array len is u32

b125487

load-after-store zero/sign-extends if the store is truncating

One more missed case

01e0b9e

Merge branch 'ch19' of https://github.com/SeaOfNodes/Simple into new

21c85b9

riscv init

56e65cc

added not imm form bitwise shifts and ops plus test cases

3e72fef

addressing modes(high chance it'll get deleted)

c371bee

fix minor bug

2c86881

merge

9c45918

merge3

3ec5511

Hels15 added 3 commits February 9, 2025 12:40

delete non existing matches

3c5c3e0

Merge branch 'ch20_reg' of https://github.com/SeaOfNodes/Simple into new

00fd577

replace RegMask.Empty with null

19ba713

cliffclick reviewed Feb 9, 2025

View reviewed changes

Hels15 added 4 commits February 9, 2025 23:01

riscv handle store and load, fltRisch uses risc reg now

ce8017f

load float into GPR and then later in RA do hard split.

4d3a13f

Merge branch 'ch20_reg' of https://github.com/SeaOfNodes/Simple into new

239d8bc

minor changes

59cbd26

cliffclick approved these changes Feb 11, 2025

View reviewed changes

cliffclick added 2 commits February 11, 2025 09:22

turn off ch20 tests

0693b84

Update Chapter20Test.java

758dd44

cliffclick merged commit 47b405d into SeaOfNodes:ch20_reg Feb 11, 2025
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RISC-V basic isel #156

RISC-V basic isel #156

Hels15 commented Feb 8, 2025

cliffclick commented Feb 8, 2025

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cliffclick Feb 9, 2025

cliffclick Feb 9, 2025

cliffclick Feb 9, 2025

cliffclick Feb 9, 2025

cliffclick Feb 9, 2025

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		// sw rs2,offset(rs1)
		public class StoreRISC extends MachConcreteNode implements MachNode {

RISC-V basic isel #156

RISC-V basic isel #156

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