Compile some riscv codes

If SplitEmptyMask does not apply, fall back to normal split. Missing CmpFRISC. Renamed riscv flags. RetRISC handls FPR remove extra RegMask constructurs
SeaOfNodes · Feb 12, 2025 · b1756ef · b1756ef
1 parent 4cdb14b
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Showing 10 changed files with 74 additions and 39 deletions.
diff --git a/chapter20/src/main/java/com/seaofnodes/simple/codegen/RegAlloc.java b/chapter20/src/main/java/com/seaofnodes/simple/codegen/RegAlloc.java
@@ -173,7 +173,10 @@ boolean split( LRG lrg ) {
 
         // Register mask when empty; split around defs and uses with limited
         // register masks.
-        if( lrg._mask.isEmpty() )
+        if( lrg._mask.isEmpty() &&
+             lrg._1regDefCnt <= 1 &&
+             lrg._1regUseCnt <= 1 &&
+            (lrg._1regDefCnt + lrg._1regUseCnt) > 0 )
             return splitEmptyMask(lrg);
 
         if( lrg._selfConflicts != null )
@@ -189,17 +192,14 @@ boolean splitEmptyMask( LRG lrg ) {
         // Live range has a single-def single-register, and/or a single-use
         // single-register.  Split after the def and before the use.  Does not
         // require a full pass.
-        if( lrg._1regDefCnt<=1 && lrg._1regUseCnt<=1 && (lrg._1regDefCnt + lrg._1regUseCnt) > 0 ) {
-            // Split just after def
-            if( lrg._1regDefCnt==1 )
-                _code._mach.split().insertAfter((Node)lrg._machDef);
-            // Split just before use
-            if( lrg._1regUseCnt==1 )
-                _code._mach.split().insertBefore((Node)lrg._machUse, lrg._uidx);
-            return true;
-        }
-        // Needs a full pass to find all defs and all uses
-        throw Utils.TODO();
+
+        // Split just after def
+        if( lrg._1regDefCnt==1 )
+            _code._mach.split().insertAfter((Node)lrg._machDef);
+        // Split just before use
+        if( lrg._1regUseCnt==1 )
+            _code._mach.split().insertBefore((Node)lrg._machUse, lrg._uidx);
+        return true;
     }
 
     // Self conflicts require Phis (or two-address).

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/codegen/RegMask.java b/chapter20/src/main/java/com/seaofnodes/simple/codegen/RegMask.java
@@ -13,10 +13,7 @@ public class RegMask {
     public static final RegMask FULL = new RegMask(-1L);
 
     public RegMask(long x ) { _bits = x; }
-    public RegMask(long[] xs) { /*_bits = BitSet.valueOf(           xs); */ throw Utils.TODO(); }
-    // Internal constructor
-    RegMask() { /*_bits = new BitSet();*/ _bits = 0; }
-    //RegMask(BitSet bs) { _bits = bs; }
+    private RegMask() { _bits = 0; }
 
     // Copy-on-write
     RegMask and( RegMask mask ) {

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CBranchRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CBranchRISC.java
@@ -29,7 +29,7 @@ public class CBranchRISC extends IfNode implements MachNode{
             throw Utils.TODO();
     }
 
-    @Override public RegMask regmap(int i) { assert i==1; return riscv.RMASK; }
+    @Override public RegMask regmap(int i) { assert i==1; return riscv.FLAGS_MASK; }
     @Override public RegMask outregmap() { return null; }
 
     // Encoding is appended into the byte array; size is returned
@@ -40,7 +40,7 @@ public class CBranchRISC extends IfNode implements MachNode{
 
     @Override public void asm(CodeGen code, SB sb) {
         String src = code.reg(in(1));
-        if( src!="FLAGS" )  sb.p(src);
+        if( src!="flags" )  sb.p(src);
     }
 
     @Override public String op() { return "b"+_bop; }

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CmpFRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CmpFRISC.java
@@ -0,0 +1,32 @@
+package com.seaofnodes.simple.node.cpus.riscv;
+
+import com.seaofnodes.simple.*;
+import com.seaofnodes.simple.codegen.CodeGen;
+import com.seaofnodes.simple.codegen.RegMask;
+import com.seaofnodes.simple.node.*;
+import com.seaofnodes.simple.type.Type;
+import com.seaofnodes.simple.type.TypeFunPtr;
+import java.io.ByteArrayOutputStream;
+
+// Compare.  Sets flags.(RFLAGS)
+public class CmpFRISC extends  MachConcreteNode implements MachNode{
+    CmpFRISC( Node cmp ) { super(cmp); }
+
+    // Encoding is appended into the byte array; size is returned
+    @Override public int encoding(ByteArrayOutputStream bytes) {
+        throw Utils.TODO();
+    }
+
+
+    // General form: "cmp  rs1, rs2"
+    @Override public void asm(CodeGen code, SB sb) {
+        String dst = code.reg(this);
+        if( dst!="flags" )  sb.p(dst).p(" = ");
+        sb.p(code.reg(in(1))).p(", ").p(code.reg(in(2)));
+    }
+
+    @Override public RegMask regmap(int i) { assert i==1 || i==2; return riscv.FMASK; }
+    @Override public RegMask outregmap() { return riscv.FLAGS_MASK; }
+
+    @Override public String op() { return "cmpf"; }
+}
diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CmpIRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CmpIRISC.java
@@ -36,7 +36,7 @@ public class CmpIRISC extends MachConcreteNode implements MachNode{
     // General form: "cmp  rs1, 1"
     @Override public void asm(CodeGen code, SB sb) {
         String dst = code.reg(this);
-        if( dst!="FLAGS" )  sb.p(dst).p(" = ");
+        if( dst!="flags" )  sb.p(dst).p(" = ");
         sb.p(code.reg(in(1)));
         if( _imm != 0 ) sb.p(", #").p(_imm);
     }

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CmpRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/CmpRISC.java
@@ -21,7 +21,7 @@ public class CmpRISC extends  MachConcreteNode implements MachNode{
     // General form: "cmp  rs1, rs2"
     @Override public void asm(CodeGen code, SB sb) {
         String dst = code.reg(this);
-        if( dst!="FLAGS" )  sb.p(dst).p(" = ");
+        if( dst!="flags" )  sb.p(dst).p(" = ");
         sb.p(code.reg(in(1))).p(", ").p(code.reg(in(2)));
     }
 

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/DivFRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/DivFRISC.java
@@ -24,7 +24,7 @@ public class DivFRISC extends MachConcreteNode implements MachNode{
     // Default on double precision for now(64 bits)
     // General form: "fdiv.d  rd = src1 / src2
     @Override public void asm(CodeGen code, SB sb) {
-        sb.p(code.reg(this)).p(" = ").p(code.reg(in(1))).p(" + ").p(code.reg(in(2)));
+        sb.p(code.reg(this)).p(" = ").p(code.reg(in(1))).p(" / ").p(code.reg(in(2)));
     }
 
     @Override public String op() { return "divf"; }

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/MulFRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/MulFRISC.java
@@ -24,7 +24,7 @@ public class MulFRISC extends MachConcreteNode implements MachNode{
     // Default on double precision for now(64 bits)
     // General form: "fmul.d  rd = src1 * src2
     @Override public void asm(CodeGen code, SB sb) {
-        sb.p(code.reg(this)).p(" = ").p(code.reg(in(1))).p(" + ").p(code.reg(in(2)));
+        sb.p(code.reg(this)).p(" = ").p(code.reg(in(1))).p(" * ").p(code.reg(in(2)));
     }
 
     @Override public String op() { return "mulf"; }

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/RetRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/RetRISC.java
@@ -6,6 +6,7 @@
 import com.seaofnodes.simple.node.FunNode;
 import com.seaofnodes.simple.node.ReturnNode;
 import com.seaofnodes.simple.node.MachNode;
+import com.seaofnodes.simple.type.TypeFloat;
 
 import java.io.ByteArrayOutputStream;
 
@@ -16,11 +17,11 @@ public class RetRISC extends ReturnNode implements MachNode{
     // This is the normal calling convention
     @Override public RegMask regmap(int i) {
         return switch( i ) {
-            case 0 -> null;
-            case 1 -> null;
-            case 2 -> riscv.RET_MASK;
-            case 3 -> null; // RPC is always on stack
-            default -> throw Utils.TODO();
+        case 0 -> null;
+        case 1 -> null;
+        case 2 -> _fun.sig()._ret instanceof TypeFloat ? riscv.RET_FMASK : riscv.RET_MASK;
+        case 3 -> null; // RPC is always on stack
+        default -> throw Utils.TODO();
         };
     }
     // Register mask allowed as a result.  0 for no register.

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java
@@ -10,7 +10,7 @@ public class riscv extends Machine{
     @Override public String name() {return "riscv";}
 
     // Using ABI names instead of register names
-    public static int ZERO =  0,  RA =  1,  SP =  2,  GP =  3,  TP =  4,  T0 =  5,  T1 =  6,  T2 =  7;
+    public static int             RA =  1,  SP =  2,  GP =  3,  TP =  4,  T0 =  5,  T1 =  6,  T2 =  7;
     public static int S0   =  8,  S1 =  9,  A0 = 10,  A1 = 11,  A2 = 12,  A3 = 13,  A4 = 14,  A5 = 15;
     public static int A6   = 16,  A7 = 17,  S2 = 18,  S3 = 19,  S4 = 20,  S5 = 21,  S6 = 22,  S7 = 23;
     public static int S8   = 24,  S9 = 25,  S10 = 26, S11 = 27, T3 = 28,  T4 = 29,  T5 = 30,  T6 = 31;
@@ -21,7 +21,7 @@ public class riscv extends Machine{
     public static int FA6  = 48,  FA7 = 49,  FS2 = 50,  FS3 = 51,  FS4 = 52,  FS5 = 53,  FS6 = 54,  FS7  = 55;
     public static int FS8  = 56,  FS9 = 57,  FS10 = 58, FS11 = 59, FT8 = 60,  FT9 = 61,  FT10 = 62, FT11 = 63;
 
-    public static int FLAGS = 64;
+    public static int FLAGS = 0 ;
 
     // General purpose register mask: pointers and ints, not floats
     public static RegMask RMASK = new RegMask(0b11111111111111111111111111111110L);
@@ -33,7 +33,8 @@ public class riscv extends Machine{
 
 
     // Return single int/ptr register
-    public static RegMask RET_MASK = new RegMask(1<<A0);
+    public static RegMask RET_MASK  = new RegMask(1L<< A0);
+    public static RegMask RET_FMASK = new RegMask(1L<<FA0);
 
     // Arguments masks
     public static RegMask A0_MASK = new RegMask(1L<<A0);
@@ -141,15 +142,14 @@ static RegMask callInMaskFloat(int idx) {
     public int FLOAT_COUNT_CONV_RISCV = 7; // FA0, FA1, FA2, FA3, FA4, FA5, FA6, FA7
 
     public static final String[] REGS = new String[] {
-            "zero", "ra"  , "sp"  , "gp"  , "tp"  , "t0"  , "t1"  , "t2"  ,
+            "flags","ra"  , "sp"  , "gp"  , "tp"  , "t0"  , "t1"  , "t2"  ,
             "s0"  , "s1"  , "a0"  , "a1"  , "a2"  , "a3"  , "a4"  , "a5"  ,
             "a6"  , "a7"  , "s2"  , "s3"  , "s4"  , "s5"  , "s6"  , "s7"  ,
             "s8"  , "s9"  , "s10" , "s11" , "t3"  , "t4"  , "t5"  , "t6"  ,
             "f0"  , "f1"  , "f2"  , "f3"  , "f4"  , "f5"  , "f6"  , "f7"  ,
             "fs0" , "fs1" , "fa0" , "fa1" , "fa2" , "fa3" , "fa4" , "fa5" ,
             "fa6" , "fa7" , "fs2" , "fs3" , "fs4" , "fs5" , "fs6" , "fs7" ,
             "fs8" , "fs9" , "fs10", "fs11", "ft8" , "ft9" , "ft10", "ft11",
-            "flags"
     };
 
     // General purpose register mask:
@@ -227,21 +227,26 @@ private Node and(AndNode and) {
         return new AndRISC(and);
     }
 
-    private Node cmp(BoolNode bool) {
-        Node cmp = _cmp(bool);
-        return new SetRISC(cmp, bool.op());
-    }
-
     private Node call(CallNode call) {
         if( call.fptr() instanceof ConstantNode con && con._con instanceof TypeFunPtr tfp )
             return new CallRISC(call, tfp);
         return new CallRRISC(call);
     }
 
+    private Node cmp(BoolNode bool) {
+        Node cmp = _cmp(bool);
+        return new SetRISC(cmp, bool.op());
+    }
+
     private Node _cmp(BoolNode bool) {
-        Node rhs = bool.in(2);
+        // Float variant
+        if( bool instanceof BoolNode.EQF ||
+            bool instanceof BoolNode.LTF ||
+            bool instanceof BoolNode.LEF )
+            return new CmpFRISC(bool);
 
-        return rhs instanceof ConstantNode con && con._con instanceof TypeInteger ti
+        Node rhs = bool.in(2);
+        return bool.in(2) instanceof ConstantNode con && con._con instanceof TypeInteger ti
                 ? new CmpIRISC(bool, ti)
                 : new CmpRISC(bool);
     }