Push RISC WMASK

avoid writing to RSP
SeaOfNodes · Feb 14, 2025 · 8021e91 · 8021e91
1 parent 8d303df
commit 8021e91
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Showing 26 changed files with 38 additions and 29 deletions.
diff --git a/chapter20/src/main/java/com/seaofnodes/simple/codegen/LRG.java b/chapter20/src/main/java/com/seaofnodes/simple/codegen/LRG.java
@@ -134,7 +134,10 @@ void selfConflict( Node def ) {
     // Record intersection of all register masks.
     // True if still has registers
     boolean and( RegMask mask ) {
-        _mask = mask.and(_mask);
+        RegMask mask2 = mask.and(_mask);
+        if( mask2==null )
+            mask2 = _mask.copy().and(mask);
+        _mask = mask2;
         return !_mask.isEmpty();
     }
     // Remove this singular register

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/codegen/RegMask.java b/chapter20/src/main/java/com/seaofnodes/simple/codegen/RegMask.java
@@ -23,7 +23,7 @@ RegMask and( RegMask mask ) {
         if( bits==mask._bits ) return mask;
         if( bits==0 ) return EMPTY;
         // Update-in-place a mutable mask, or make a defensive copy
-        throw Utils.TODO();
+        return null;
     }
 
     // Fails if bit is set, because this is immutable
@@ -67,4 +67,9 @@ public SB toString(SB sb) {
 class RegMaskRW extends RegMask {
     public RegMaskRW(long x) { super(x);  }
     public boolean clr(int r) { _bits &= ~(1L<<r); return _bits!=0; }
+    @Override RegMaskRW and( RegMask mask ) {
+        if( mask==null ) return this;
+        _bits &= mask._bits;
+        return this;
+    }
 }
diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/ConstantNode.java b/chapter20/src/main/java/com/seaofnodes/simple/node/ConstantNode.java
@@ -50,7 +50,7 @@ StringBuilder _print1(StringBuilder sb, BitSet visited) {
         return sb.append(_con.print(new SB()));
     }
 
-    @Override public boolean isMultiTail() { return true; }
+    //@Override public boolean isMultiTail() { return true; }
     @Override public boolean isConst() { return true; }
 
     @Override

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AddIRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AddIRISC.java
@@ -20,7 +20,7 @@ public class AddIRISC extends MachConcreteNode implements MachNode {
         // assert i== i;
         return riscv.RMASK; }
     // Register mask allowed as a result.  0 for no register.
-    @Override public RegMask outregmap() { return riscv.RMASK; }
+    @Override public RegMask outregmap() { return riscv.WMASK; }
     // Output is same register as input#1
     @Override public int twoAddress() { return 0; }
 

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AddRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AddRISC.java
@@ -18,7 +18,7 @@ public class AddRISC extends MachConcreteNode implements MachNode {
          return riscv.RMASK;
     }
     // Register mask allowed as a result.  0 for no register.
-    @Override public RegMask outregmap() { return riscv.RMASK; }
+    @Override public RegMask outregmap() { return riscv.WMASK; }
     // Output is same register as input#1
     @Override public int twoAddress() { return 0; }
 

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AndIRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AndIRISC.java
@@ -21,7 +21,7 @@ public class AndIRISC extends MachConcreteNode implements MachNode{
     // This is the normal calling convention
     @Override public RegMask regmap(int i) { assert i==1 || i == 2; return riscv.RMASK; }
     // Register mask allowed as a result.  0 for no register.
-    @Override public RegMask outregmap() { return riscv.RMASK; }
+    @Override public RegMask outregmap() { return riscv.WMASK; }
 
     // Output is same register as input#1
     @Override public int twoAddress() { return 0; }

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AndRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/AndRISC.java
@@ -23,7 +23,7 @@ public class AndRISC extends MachConcreteNode implements MachNode{
     }
 
     // Register mask allowed as a result.  0 for no register.
-    @Override public RegMask outregmap() { return riscv.RMASK; }
+    @Override public RegMask outregmap() { return riscv.WMASK; }
 
     // Output is same register as input#1
     @Override public int twoAddress() { return 0; }

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/DivRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/DivRISC.java
@@ -15,7 +15,7 @@ public class DivRISC extends MachConcreteNode implements MachNode{
         assert i==1 || i==2;
         return riscv.FMASK; }
     // Register mask allowed as a result.  0 for no register.
-    @Override public RegMask outregmap() { return riscv.RMASK; }
+    @Override public RegMask outregmap() { return riscv.WMASK; }
     // Output is same register as input#1
     @Override public int twoAddress() { return 1; }
 

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/IntRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/IntRISC.java
@@ -18,7 +18,7 @@ public class IntRISC extends ConstantNode implements MachNode {
     // Register mask allowed on input i.  0 for no register.
     @Override public RegMask regmap(int i) { return null; }
     // General int registers
-    @Override public RegMask outregmap() { return riscv.RMASK; }
+    @Override public RegMask outregmap() { return riscv.WMASK; }
 
     // Encoding is appended into the byte array; size is returned
     @Override public int encoding(ByteArrayOutputStream bytes) {

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/MulIRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/MulIRISC.java
@@ -16,7 +16,7 @@ public class MulIRISC extends MachConcreteNode  implements MachNode {
     @Override public RegMask regmap(int i) {
         return riscv.RMASK; }
     // Register mask allowed as a result.  0 for no register.
-    @Override public RegMask outregmap() { return riscv.RMASK; }
+    @Override public RegMask outregmap() { return riscv.WMASK; }
 
 
     // Output is same register as input#1

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/MulRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/MulRISC.java
@@ -15,7 +15,7 @@ public class MulRISC extends MachConcreteNode implements MachNode{
     // Register mask allowed on input i.
     @Override public RegMask regmap(int i) { assert i==1 || i==2; return riscv.RMASK; }
     // Register mask allowed as a result.  0 for no register.
-    @Override public RegMask outregmap() { return riscv.RMASK; }
+    @Override public RegMask outregmap() { return riscv.WMASK; }
     // Output is same register as input#1
     @Override public int twoAddress() { return 1; }
 

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/OrIRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/OrIRISC.java
@@ -21,7 +21,7 @@ public class OrIRISC extends MachConcreteNode implements MachNode{
         return riscv.RMASK;
     }
     // Register mask allowed as a result.  0 for no register.
-    @Override public RegMask outregmap() { return riscv.RMASK; }
+    @Override public RegMask outregmap() { return riscv.WMASK; }
     // Output is same register as input#1
     @Override public int twoAddress() { return 0;}
 

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/OrRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/OrRISC.java
@@ -22,7 +22,7 @@ public class OrRISC extends MachConcreteNode implements MachNode {
     }
 
     // Register mask allowed as a result.  0 for no register.
-    @Override public RegMask outregmap() { return riscv.RMASK; }
+    @Override public RegMask outregmap() { return riscv.WMASK; }
 
     // Output is same register as input#1
     @Override public int twoAddress() { return 0; }

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SetRISC.java
@@ -20,7 +20,7 @@ public class SetRISC extends MachConcreteNode implements MachNode{
         _bop = bop;
     }
     @Override public RegMask regmap(int i) { assert i==1; return riscv.FLAGS_MASK; }
-    @Override public RegMask outregmap() { return riscv.RMASK; }
+    @Override public RegMask outregmap() { return riscv.WMASK; }
 
     // Encoding is appended into the byte array; size is returned
     @Override public int encoding(ByteArrayOutputStream bytes) {

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SllIRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SllIRISC.java
@@ -20,7 +20,7 @@ public class SllIRISC extends MachConcreteNode implements MachNode{
         return riscv.RMASK; }
 
     // Register mask allowed as a result.  0 for no register.
-    @Override public RegMask outregmap() { return riscv.RMASK; }
+    @Override public RegMask outregmap() { return riscv.WMASK; }
 
     // Output is same register as input#1
     @Override public int twoAddress() { return 0; }

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SllRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SllRISC.java
@@ -18,7 +18,7 @@ public class SllRISC extends MachConcreteNode implements MachNode{
         //assert i==1;
         return riscv.RMASK; }
     // Register mask allowed as a result.  0 for no register.
-    @Override public RegMask outregmap() { return riscv.RMASK; }
+    @Override public RegMask outregmap() { return riscv.WMASK; }
 
     // Output is same register as input#1
     @Override public int twoAddress() { return 1; }

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SplitRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SplitRISC.java
@@ -11,9 +11,9 @@ public class SplitRISC extends MachConcreteNode implements MachNode {
     SplitRISC( ) { super(new Node[2]); }
 
     // Register mask allowed on input i.
-    @Override public RegMask regmap(int i) { return RegMask.FULL; }
+    @Override public RegMask regmap(int i) { return riscv.MEM_MASK; }
     // Register mask allowed as a result.  0 for no register.
-    @Override public RegMask outregmap() { return RegMask.FULL; }
+    @Override public RegMask outregmap() { return riscv.MEM_MASK; }
 
     @Override public boolean isSplit() { return true; }
 

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SraIRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SraIRISC.java
@@ -23,7 +23,7 @@ public class SraIRISC extends MachConcreteNode implements MachNode{
         return riscv.RMASK; }
 
     // Register mask allowed as a result.  0 for no register.
-    @Override public RegMask outregmap() { return riscv.RMASK; }
+    @Override public RegMask outregmap() { return riscv.WMASK; }
 
     // Output is same register as input#1
     @Override public int twoAddress() { return 0; }

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SraRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SraRISC.java
@@ -21,7 +21,7 @@ public class SraRISC extends MachConcreteNode implements MachNode {
         // assert i==1;
         return riscv.RMASK; }
     // Register mask allowed as a result.  0 for no register.
-    @Override public RegMask outregmap() { return riscv.RMASK; }
+    @Override public RegMask outregmap() { return riscv.WMASK; }
 
     // Output is same register as input#1
     @Override public int twoAddress() { return 1; }

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SrlIRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SrlIRISC.java
@@ -23,7 +23,7 @@ public class SrlIRISC extends MachConcreteNode implements MachNode {
         // assert i==1;
         return riscv.RMASK; }
     // Register mask allowed as a result.  0 for no register.
-    @Override public RegMask outregmap() { return riscv.RMASK; }
+    @Override public RegMask outregmap() { return riscv.WMASK; }
 
     // Output is same register as input#1
     @Override public int twoAddress() { return 1; }

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SrlRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SrlRISC.java
@@ -20,7 +20,7 @@ public class SrlRISC extends MachConcreteNode implements MachNode {
         // assert i==1;
         return riscv.RMASK; }
     // Register mask allowed as a result.  0 for no register.
-    @Override public RegMask outregmap() { return riscv.RMASK; }
+    @Override public RegMask outregmap() { return riscv.WMASK; }
 
     // Output is same register as input#1
     @Override public int twoAddress() { return 1; }

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SubRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/SubRISC.java
@@ -13,7 +13,7 @@ public class SubRISC extends MachConcreteNode implements MachNode {
     // Register mask allowed on input i.
     @Override public RegMask regmap(int i) { assert i==1 || i==2; return riscv.RMASK; }
     // Register mask allowed as a result.  0 for no register.
-    @Override public RegMask outregmap() { return riscv.RMASK; }
+    @Override public RegMask outregmap() { return riscv.WMASK; }
     // Output is same register as input#1
     @Override public int twoAddress() { return 0; }
 

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/TFPRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/TFPRISC.java
@@ -14,7 +14,7 @@ public class TFPRISC extends ConstantNode implements MachNode{
     // Register mask allowed on input i.  0 for no register.
     @Override public RegMask regmap(int i) { return null; }
     // General int registers
-    @Override public RegMask outregmap() { return riscv.RMASK; }
+    @Override public RegMask outregmap() { return riscv.WMASK; }
 
     // Encoding is appended into the byte array; size is returned
     @Override public int encoding(ByteArrayOutputStream bytes) {

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/XorIRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/XorIRISC.java
@@ -22,7 +22,7 @@ public class XorIRISC extends MachConcreteNode implements MachNode{
         return riscv.RMASK; }
 
     // Register mask allowed as a result.  0 for no register.
-    @Override public RegMask outregmap() { return riscv.RMASK; }
+    @Override public RegMask outregmap() { return riscv.WMASK; }
 
     // Output is same register as input#1
     @Override public int twoAddress() { return 1; }

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/XorRISC.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/XorRISC.java
@@ -24,7 +24,7 @@ public class XorRISC extends MachConcreteNode implements MachNode {
     }
 
     // Register mask allowed as a result.  0 for no register.
-    @Override public RegMask outregmap() { return riscv.RMASK; }
+    @Override public RegMask outregmap() { return riscv.WMASK; }
 
     // Output is same register as input#1
     @Override public int twoAddress() { return 0; }

diff --git a/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java b/chapter20/src/main/java/com/seaofnodes/simple/node/cpus/riscv/riscv.java
@@ -10,7 +10,7 @@ public class riscv extends Machine{
     @Override public String name() {return "riscv";}
 
     // Using ABI names instead of register names
-    public static int             RA =  1,  SP =  2,  GP =  3,  TP =  4,  T0 =  5,  T1 =  6,  T2 =  7;
+    public static int             RPC=  1,  SP =  2,  GP =  3,  TP =  4,  T0 =  5,  T1 =  6,  T2 =  7;
     public static int S0   =  8,  S1 =  9,  A0 = 10,  A1 = 11,  A2 = 12,  A3 = 13,  A4 = 14,  A5 = 15;
     public static int A6   = 16,  A7 = 17,  S2 = 18,  S3 = 19,  S4 = 20,  S5 = 21,  S6 = 22,  S7 = 23;
     public static int S8   = 24,  S9 = 25,  S10 = 26, S11 = 27, T3 = 28,  T4 = 29,  T5 = 30,  T6 = 31;
@@ -25,11 +25,12 @@ public class riscv extends Machine{
 
     // General purpose register mask: pointers and ints, not floats
     public static RegMask RMASK = new RegMask(0b11111111111111111111111111111110L);
+    public static RegMask WMASK = new RegMask(0b11111111111111111111111111111010L);
     // Float mask from(ft0–ft11)
     public static RegMask FMASK = new RegMask(0b11111111111111111111111111111111L<<F0);
 
     // Load/store mask; both GPR and FPR
-    public static RegMask MEM_MASK = new RegMask(-1L);
+    public static RegMask MEM_MASK = new RegMask(0b11111111111111111111111111111010L | (0b11111111111111111111111111111111L<<F0));
 
 
     // Return single int/ptr register
@@ -142,7 +143,7 @@ static RegMask callInMaskFloat(int idx) {
     public int FLOAT_COUNT_CONV_RISCV = 7; // FA0, FA1, FA2, FA3, FA4, FA5, FA6, FA7
 
     public static final String[] REGS = new String[] {
-            "flags","ra"  , "sp"  , "gp"  , "tp"  , "t0"  , "t1"  , "t2"  ,
+            "flags","rpc" , "sp"  , "gp"  , "tp"  , "t0"  , "t1"  , "t2"  ,
             "s0"  , "s1"  , "a0"  , "a1"  , "a2"  , "a3"  , "a4"  , "a5"  ,
             "a6"  , "a7"  , "s2"  , "s3"  , "s4"  , "s5"  , "s6"  , "s7"  ,
             "s8"  , "s9"  , "s10" , "s11" , "t3"  , "t4"  , "t5"  , "t6"  ,