Update and rename Assignment_5.out to CMOS Inverter with capacitive l…

…oad.out
Saptarshi-prog · Oct 22, 2022 · fc6baae · fc6baae
1 parent 107b8f7
commit fc6baae
Showing 1 changed file with 1 addition and 5 deletions.
diff --git a/Assignment_5.out → CMOS Inverter with capacitive load.out b/Assignment_5.out → CMOS Inverter with capacitive load.out
@@ -1,8 +1,4 @@
-* Key: 572ffdb45f4d1fef93fa674a440d8e7a
-* T-Spice Demo 9.12 Simulation	Sat Oct 22 13:43:10 2022	F:\IIT Dhanbad\1st Semester\Digital VLSI Lab\Day 1\Assignment_5.sp
-* Command line: tspice -o "F:\IIT Dhanbad\1st Semester\Digital VLSI Lab\Day 1\Assignment_5.out" "F:\IIT Dhanbad\1st Semester\Digital VLSI Lab\Day 1\Assignment_5.sp" 
-* T-Spice Win32 Demo 9.12.20040112.04:26:10
-* Operating System: Windows NT/95
+
 * Warning : Source perimeter (PS) is zero for MOSFET device M1
 * Warning : Drain perimeter (PD) is zero for MOSFET device M1
 * Warning : Source perimeter (PS) is zero for MOSFET device M2