This project aims to implement a compact 8-bit RISC-V processor core, suitable for Tiny Tapeout. The processor is based on a simplified version of the RISC-V architecture, utilizing a customized instruction set inspired by the RISC-V Compressed (RVC) instruction set. The design focuses on minimizing area and power, making it ideal for Tiny Tapeout’s educational IC fabrication platform. The CPU is implemented in Verilog and is designed to support basic computational, control-flow, and load/store operations efficiently.