[hw,i2c,racl] Add RACL support to I2C

Signed-off-by: Robert Schilling <[email protected]>
Razer6 · Jan 1, 2025 · 7af69ad · 7af69ad
1 parent cf72469
commit 7af69ad
Show file tree

Hide file tree

Showing 10 changed files with 584 additions and 109 deletions.
diff --git a/hw/ip/i2c/data/i2c.hjson b/hw/ip/i2c/data/i2c.hjson
@@ -30,7 +30,7 @@
   ]
   clocking: [{clock: "clk_i", reset: "rst_ni"}],
   bus_interfaces: [
-    { protocol: "tlul", direction: "device" }
+    { protocol: "tlul", direction: "device", racl_support: true }
   ],
   // INPUT pins
   available_inout_list: [
@@ -130,6 +130,35 @@
       '''
       act:    "req"
     }
+    { struct:  "racl_policy_vec",
+      type:    "uni",
+      name:    "racl_policies",
+      act:     "rcv",
+      package: "top_racl_pkg",
+      desc:    '''
+        Policy vector distributed to the subscribing RACL IPs.
+      '''
+    }
+    { struct:  "logic",
+      type:    "uni",
+      name:    "racl_error",
+      act:     "req",
+      width  : "1",
+      desc:    '''
+        RACL error indication signal.
+        If 1, the error log contains valid information.
+      '''
+    }
+    { struct:  "racl_error_log",
+      type:    "uni",
+      name:    "racl_error_log",
+      act:     "req",
+      width:   "1"
+      package: "top_racl_pkg",
+      desc:    '''
+        RACL error log information of this module.
+      '''
+    }
   ]
   param_list: [
     { name: "FifoDepth",

diff --git a/hw/ip/i2c/doc/interfaces.md b/hw/ip/i2c/doc/interfaces.md
@@ -16,12 +16,15 @@ Referring to the [Comportable guideline for peripheral device functionality](htt
 
 ## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling)
 
-| Port Name    | Package::Struct                 | Type    | Act   |   Width | Description                                                                                                                              |
-|:-------------|:--------------------------------|:--------|:------|--------:|:-----------------------------------------------------------------------------------------------------------------------------------------|
-| ram_cfg      | prim_ram_1p_pkg::ram_1p_cfg     | uni     | rcv   |       1 |                                                                                                                                          |
-| ram_cfg_rsp  | prim_ram_1p_pkg::ram_1p_cfg_rsp | uni     | req   |       1 |                                                                                                                                          |
-| lsio_trigger | logic                           | uni     | req   |       1 | Self-clearing status trigger for the DMA. Set when RX TX FIFO is past their configured watermark matching watermark interrupt behaviour. |
-| tl           | tlul_pkg::tl                    | req_rsp | rsp   |       1 |                                                                                                                                          |
+| Port Name      | Package::Struct                 | Type    | Act   |   Width | Description                                                                                                                              |
+|:---------------|:--------------------------------|:--------|:------|--------:|:-----------------------------------------------------------------------------------------------------------------------------------------|
+| ram_cfg        | prim_ram_1p_pkg::ram_1p_cfg     | uni     | rcv   |       1 |                                                                                                                                          |
+| ram_cfg_rsp    | prim_ram_1p_pkg::ram_1p_cfg_rsp | uni     | req   |       1 |                                                                                                                                          |
+| lsio_trigger   | logic                           | uni     | req   |       1 | Self-clearing status trigger for the DMA. Set when RX TX FIFO is past their configured watermark matching watermark interrupt behaviour. |
+| racl_policies  | top_racl_pkg::racl_policy_vec   | uni     | rcv   |       1 | Policy vector distributed to the subscribing RACL IPs.                                                                                   |
+| racl_error     | logic                           | uni     | req   |       1 | RACL error indication signal. If 1, the error log contains valid information.                                                            |
+| racl_error_log | top_racl_pkg::racl_error_log    | uni     | req   |       1 | RACL error log information of this module.                                                                                               |
+| tl             | tlul_pkg::tl                    | req_rsp | rsp   |       1 |                                                                                                                                          |
 
 ## Interrupts
 

diff --git a/hw/ip/i2c/i2c.core b/hw/ip/i2c/i2c.core
@@ -13,6 +13,7 @@ filesets:
       - lowrisc:prim:ram_1p_adv
       - lowrisc:ip:tlul
       - lowrisc:ip:i2c_pkg
+      - lowrisc:systems:top_racl_pkg
     files:
       - rtl/i2c_reg_pkg.sv
       - rtl/i2c_reg_top.sv
@@ -48,6 +49,9 @@ filesets:
       # common waivers
       - lowrisc:lint:common
       - lowrisc:lint:comportable
+    files:
+      - lint/pwm.vbl
+    file_type: veribleLintWaiver
 
 parameters:
   SYNTHESIS:

diff --git a/hw/ip/i2c/lint/i2c.vbl b/hw/ip/i2c/lint/i2c.vbl
@@ -0,0 +1,6 @@
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# These lines are too long due to generated code
+waive --rule=line-length --location="i2c_reg_top.sv"
diff --git a/hw/ip/i2c/rtl/i2c.sv b/hw/ip/i2c/rtl/i2c.sv
@@ -9,8 +9,11 @@
 module i2c
   import i2c_reg_pkg::*;
 #(
-  parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}},
-  parameter int unsigned InputDelayCycles = 0
+  parameter logic [NumAlerts-1:0] AlertAsyncOn         = {NumAlerts{1'b1}},
+  parameter int unsigned          InputDelayCycles     = 0,
+  parameter bit                   EnableRacl           = 1'b0,
+  parameter bit                   RaclErrorRsp         = 1'b1,
+  parameter int unsigned          RaclPolicySelVec[23] = '{32{0}},
 ) (
   input                                    clk_i,
   input                                    rst_ni,
@@ -25,6 +28,11 @@ module i2c
   input  prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
   output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
 
+  // RACL interface
+  input  top_racl_pkg::racl_policy_vec_t  racl_policies_i,
+  output logic                            racl_error_o,
+  output top_racl_pkg::racl_error_log_t   racl_error_log_o,
+
   // Generic IO
   input                     cio_scl_i,
   output logic              cio_scl_o,
@@ -58,13 +66,20 @@ module i2c
 
   logic [NumAlerts-1:0] alert_test, alerts;
 
-  i2c_reg_top u_reg (
+  i2c_reg_top #(
+    .EnableRacl(EnableRacl),
+    .RaclErrorRsp(RaclErrorRsp),
+    .RaclPolicySelVec(RaclPolicySelVec)
+  ) u_reg (
     .clk_i,
     .rst_ni,
     .tl_i,
     .tl_o,
     .reg2hw,
     .hw2reg,
+    .racl_policies_i,
+    .racl_error_o,
+    .racl_error_log_o,
     // SEC_CM: BUS.INTEGRITY
     .intg_err_o(alerts[0])
   );