unzipped files

ALU.sv

@@ -0,0 +1,38 @@
+`timescale 1ns / 1ps
+
+module ALU_HW_4(ALU_A, ALU_B, ALU_FUN, RESULT);
+    input signed [31:0] ALU_A;
+    input signed [31:0] ALU_B; //Two inputs from MUX outputs, output A and B
+    input logic [3:0] ALU_FUN; //4-bit input for option for ALU
+    output logic [31:0] RESULT; //32-bit output of ALU
+
+   always_comb //Combinational logic (asynchronous clock)
+   begin
+
+    case (ALU_FUN) //Case statement for different cases of ALU_fun
+        1'b0 :   RESULT = ALU_A + ALU_B; //ALU_FUN operation: add A and B
+        4'b1000: RESULT = ALU_A - ALU_B; //ALU_FUN operation: subtract A from B
+        4'b0110: RESULT = ALU_A | ALU_B; //ALU_FUN operation: OR A and B
+        4'b0111: RESULT = ALU_A & ALU_B; //ALU_FUN operation: AND A and B
+        4'b0100: RESULT = ALU_A ^ ALU_B; //ALU_FUN operation: XOR A and B
+        4'b0101: RESULT = ALU_A >> ALU_B[4:0]; //ALU_FUN operation: Right-shift ALU_A the amount indicated by ALU_B, store in RESULT
+        4'b0001: RESULT = ALU_A << ALU_B[4:0]; //ALU_FUN operation: Left-shift ALU_A the amount indicated by ALU_B, store in RESULT
+        4'b1101: RESULT = ALU_A >>> ALU_B[4:0]; //ALU_FUN operation: Arithmetic right-shift ALU_A the amount indicated by ALU_B, store in RESULT
+        4'b0010: if (ALU_A < ALU_B) RESULT  = 1'b1; else RESULT = 1'b0;
+        //Statement above used when ALU_FUN is set to 1101 (set less than)
+        // When ALU_A < ALU_B, set RESULT equal to 1, else set it to 0
+        4'b0011: 
+        begin //When ALU_FUN is set to 0011 (set less than unsigned), we need to recast the 
+        // as unsigned values before we begin to compare them
+        //Once this is done, it's just a matter of following the same format as slt
+        if ($unsigned(ALU_A) < $unsigned(ALU_B)) RESULT = 1'b1; else RESULT = 1'b0;
+        end
+        4'b1001: RESULT = ALU_A; 
+        // For option 1001 (lui-copy), the ALU will grab the value provided
+        //by the 1st MUX (ALU_A). 
+        default: RESULT = 0;
+        //Since we don't want default to do anything, we just let the default case do nothing (set to 0)
+     endcase
+    end
+
+endmodule

ALU_MUX_srcA.sv

@@ -0,0 +1,13 @@
+module ALU_MUX_srcA(alu_srcA, REG_rs1, IMM_GEN_U_Type, srcA);
+
+    input [31:0] REG_rs1, IMM_GEN_U_Type;
+    input alu_srcA;
+    output logic [31:0] srcA;
+
+    always_comb begin
+        case (alu_srcA)
+            1'b0: begin srcA = REG_rs1; end
+            1'b1: begin srcA = IMM_GEN_U_Type; end
+        endcase
+    end         
+endmodule

ALU_MUX_srcB.sv

@@ -0,0 +1,17 @@
+`timescale 1ns / 1ps
+
+module ALU_MUX_srcB(REG_rs2, IMM_GEN_I_Type, IMM_GEN_S_Type, PC_OUT, alu_srcB, srcB);
+
+    input [31:0] REG_rs2, IMM_GEN_I_Type, IMM_GEN_S_Type, PC_OUT;
+    input [1:0] alu_srcB;
+    output logic [31:0] srcB;
+
+    always_comb begin
+        case (alu_srcB)
+            1'b0: begin srcB = REG_rs2; end
+            1'b1: begin srcB = IMM_GEN_I_Type; end
+            2'b10: begin srcB = IMM_GEN_S_Type; end
+            2'b11: begin srcB = PC_OUT; end
+        endcase
+   end
+endmodule

ALU_with_MUX.sv

@@ -0,0 +1,33 @@
+`timescale 1ns / 1ps
+
+module ALU_with_MUX(REG_rs1, IMM_GEN_U_Type, alu_srcA, REG_rs2, IMM_GEN_I_Type, 
+                    IMM_GEN_S_Type, PC_OUT, alu_srcB, alu_fun, ALU_RESULT);
+
+    // Inputs for MUX source A
+    input [31:0] REG_rs1, IMM_GEN_U_Type;
+    input alu_srcA;
+    // Logic for output of MUX_A to ALU
+    logic [31:0] srcA_to_ALU;
+
+    //Inputs for MUX source B
+    input [31:0] REG_rs2, IMM_GEN_I_Type, IMM_GEN_S_Type, PC_OUT;
+    input [1:0] alu_srcB;
+    // Logic for output of MUX_B to ALU
+    logic [31:0] srcB_to_ALU;
+
+    // Input for ALU_fun
+    input [3:0] alu_fun;
+    // Output for ALU
+    output logic [31:0] ALU_RESULT;
+
+    ALU_MUX_srcA MUX_A (.REG_rs1(REG_rs1), .IMM_GEN_U_Type(IMM_GEN_U_Type), 
+                        .alu_srcA(alu_srcA), .srcA(srcA_to_ALU));
+
+    ALU_MUX_srcB MUX_B (.REG_rs2(REG_rs2), .IMM_GEN_I_Type(IMM_GEN_I_Type), 
+                        .IMM_GEN_S_Type(IMM_GEN_S_Type), .PC_OUT(PC_OUT),
+                        .alu_srcB(alu_srcB), .srcB(srcB_to_ALU));
+
+    ALU_HW_4 ALU_with_MUXes (.ALU_A(srcA_to_ALU), .ALU_B(srcB_to_ALU), .ALU_FUN(alu_fun),
+                        .RESULT(ALU_RESULT));
+
+endmodule

Branch_Addr_Gen_HW_5.sv

@@ -0,0 +1,18 @@
+`timescale 1ns / 1ps
+
+module Branch_Addr_Gen_HW_5(PC_COUNT, J_INPUT, B_INPUT,
+ I_INPUT, RS1_INPUT, JALR_OUT, BRANCH_OUT, JAL_OUT);
+
+ input [31:0] PC_COUNT, J_INPUT, B_INPUT, I_INPUT, RS1_INPUT;
+ output logic [31:0] JALR_OUT, BRANCH_OUT, JAL_OUT;
+
+ always_comb begin
+
+ BRANCH_OUT = PC_COUNT + B_INPUT;
+
+ JAL_OUT = PC_COUNT + J_INPUT;
+
+ JALR_OUT = RS1_INPUT + I_INPUT;
+
+ end
+endmodule

Brand_Cond_Gen.sv

@@ -0,0 +1,92 @@
+`timescale 1ns / 1ps
+
+module Brand_Cond_Gen (REG_INPUTA, REG_INPUTB, DR_MEM_OUT, PC_SOURCE_OUT);
+
+    // Inputs of Branch Condition Generator: RS1, RS2, Memory Dout1
+    input logic [31:0] REG_INPUTA, REG_INPUTB, DR_MEM_OUT;
+    // Output of Branch Condition Generator: PC_SOURCE_OUT
+    output logic [1:0] PC_SOURCE_OUT;
+
+    // Asynchronous, use always_comb
+
+always_comb begin
+
+     // Look at current option code for program being executed
+     case (DR_MEM_OUT[6:0])
+
+
+     7'b1100011: // First case: Branch instruction (Same OP Code, different funct3) or Jalr
+        begin
+
+            case(DR_MEM_OUT[14:12])  // Check funct3
+
+                3'b000: begin // Beq (Branch if equal)
+                    // Check to see if current rs1 is equal to rs2. If so, set pcSource to 2. Otherwise, set to 0
+                    if (REG_INPUTA == REG_INPUTB) begin
+                        PC_SOURCE_OUT = 2'b10; end
+                    else begin PC_SOURCE_OUT = 1'b0; end
+                end
+
+                3'b101: begin // Bge (Branch if greater than or equal to)
+                    // Check to see if inverse of blt is true. If so, set pcSource to 2. Otherwise, set to 0
+                    if (!($signed(REG_INPUTA) < $signed(REG_INPUTB))) begin
+                        PC_SOURCE_OUT = 2'b10; end
+                    else begin PC_SOURCE_OUT = 1'b0; end
+                end
+
+                3'b111: begin // Bgeu (Branch if greater than or equal to unsigned)
+                    // Check to see if inverse of bltu is true. If so, set pcSource to 2. Otherwise, set to 0
+                    if (!(REG_INPUTA < REG_INPUTB)) begin
+                        PC_SOURCE_OUT = 2'b10; end
+                    else begin PC_SOURCE_OUT = 1'b0; end
+                end
+
+                3'b100: begin // Blt (Branch if less than)
+                    // Check to see if less than is true. If so, set pcSource to 2. Otherwise, set to 0
+                    if ($signed(REG_INPUTA) < $signed(REG_INPUTB)) begin
+                           PC_SOURCE_OUT = 2'b10; end
+                    else begin PC_SOURCE_OUT = 1'b0; end
+                end
+
+                3'b110: begin // Bltu (Branch if less than unsigned)
+                    // Check to see if less than unsigned is true. If so, set pcSource to 2. Otherwise, set to 0
+                    if (REG_INPUTA < REG_INPUTB) begin
+                     PC_SOURCE_OUT = 2'b10; end
+                    else begin PC_SOURCE_OUT = 1'b0; end
+                end
+
+                3'b001: begin // Bne (Branch if not equal)
+                // Check to see if inverse of equals is true. If so, set pcSource to 2. Otherwise, set to 0
+                    if(!(REG_INPUTA == REG_INPUTB)) begin
+                        PC_SOURCE_OUT = 2'b10; end
+                    else begin PC_SOURCE_OUT = 1'b0; end
+                end
+
+                3'b000: begin // jalr (Jump and link at register)
+                    // Set pcSource to 1
+                    PC_SOURCE_OUT = 1'b1;
+                end
+
+                default: begin // For all other cases: Default to 0
+                    PC_SOURCE_OUT =1'b0;
+                end
+
+            endcase
+
+        end
+
+     7'b1101111: begin // Second case: jal (Jump and link) 
+        // Set pcSource to 3 
+            PC_SOURCE_OUT = 2'b11;
+     end
+
+     default: begin// Default case: pcSource is set to 0 (PC + 4)
+        PC_SOURCE_OUT = 1'b0;
+        end
+
+     endcase
+
+end
+
+
+endmodule

CSR.sv

@@ -0,0 +1,79 @@
+`timescale 1ns / 1ps
+
+module CSR_HW_8(RST, INT_TAKEN, ADDR, WR_EN, PC_ADDR, WD, CLK, CSR_MIE, CSR_MEPC, CSR_MTVEC, RD);
+
+    input RST;
+    input INT_TAKEN;
+    input [11:0] ADDR;
+    input WR_EN;
+    input [31:0] PC_ADDR, WD;
+    input CLK;
+    output logic CSR_MIE;
+    output logic [31:0] CSR_MEPC, CSR_MTVEC, RD;
+
+
+    // Initialize CSR registers, 3 32-bit addresses
+    logic [31:0]CSR[0:2];
+
+    always_ff @ (posedge CLK) begin //Writing is synchronous, first check if reset is high
+
+        if (RST) //On high Reset, set current CSRs to 0
+
+            begin 
+                CSR[0] <= 1'b0;
+                CSR[1] <= 1'b0;
+                CSR[2] <= 1'b0;
+            end
+
+       else
+
+        if (WR_EN) begin//Now, check if csr_we is high. If so, check input addr to see where to write data
+            case(ADDR)
+                12'h305: begin //Write input WD to mtvec register (CSR[1])
+                CSR[1] <= WD; 
+                end
+
+                12'h341: begin //Write current PC to mepc register (CSR[0])
+                CSR[0] <= PC_ADDR;
+                end
+
+                12'h304: begin //Set mie to high (only consider bit 0) (CSR[2])
+                CSR[2][0] <= WD[0];
+                end
+
+                default:
+                CSR[2] <= 1'b0;
+            endcase
+        end
+
+        if (INT_TAKEN) begin //If an interrupt is taken, set mie back to 0
+            CSR[0] <= PC_ADDR;
+            CSR[2][0] <= 1'b0;
+        end
+
+     end
+
+   always_comb begin //Reading is asynchronous
+
+        CSR_MIE = CSR[2][0];
+        CSR_MEPC = CSR[0];
+        CSR_MTVEC = CSR[1];
+        RD = 0; // :Initialized output
+
+        case (ADDR) //Case for RD based on ADDR
+
+            12'h00000305: begin //RD mtvec register
+            RD = CSR[1]; end
+
+            12'h00000341: begin //RD mepc register
+            RD = CSR[0]; end
+
+            12'h00000304: begin //RD bit 0 of mie
+            RD = CSR[2][0]; end
+
+            default: begin //Default to remove any latches
+            RD = 1'b0; end
+
+        endcase
+    end
+endmodule

Decode_State.sv

@@ -58,7 +58,7 @@ module Decode_State(REG_CLOCK, REG_RESET, FR_MEM, FR_PC, FR_PC_4, DEC_PC_OUT, DE
 
     // ----------------------------------- Register File Setup -----------------------------------------------
 
-   Register_File_HW_3 Reg_File (.CLOCK(REG_CLOCK), .WD(FR_MEM), .RF_RS1(REG_FILE_RS1), .RF_RS2(REG_FILE_RS2));
+   Register_File_HW_3 Reg_File (.CLOCK(REG_CLOCK), .input_reg(FR_MEM), .RF_RS1(REG_FILE_RS1), .RF_RS2(REG_FILE_RS2));
 
        // ----------------------------------- Immediate Generator Setup -----------------------------------------------
 

Execute_State.sv

@@ -21,7 +21,8 @@
 
 
 module Execute_State(EXECUTE_CLOCK, EXECUTE_RESET, DR_J_TYPE, DR_B_TYPE, DR_I_TYPE, DR_PC_MEM, DR_RS1, DR_RS2, DR_ALU_FUN, JALR_TO_PC, BRANCH_TO_PC,
-                     JAL_TO_PC, PCSOURCE_TO_PC, DR_REG_WRITE, DR_MEM_WRITE, DR_MEM_READ2, DR_RF_WR_SEL, DR_PC_4);
+                     JAL_TO_PC, PCSOURCE_TO_PC, DR_REG_WRITE, DR_MEM_WRITE, DR_MEM_READ2, DR_RF_WR_SEL, DR_PC_4, EXEC_PC_4,
+                     EXEC_PC_MEM, EXEC_ALU_RESULT, EXEC_RS2, EXEC_RF_WR_SEL, EXEC_REGWRITE, EXEC_MEMWRITE, EXEC_MEMREAD2);
 
 // Inputs for clock and reset signals
     input EXECUTE_CLOCK, EXECUTE_RESET;
@@ -68,9 +69,9 @@ module Execute_State(EXECUTE_CLOCK, EXECUTE_RESET, DR_J_TYPE, DR_B_TYPE, DR_I_TY
     // 2-bit: rf_wr_sel from Decode register
     // 1-bit from Decode register: regWrite, memWrite, memRead2
 
-    logic [31:0] EXECUTE_REG1[0:3];  // 32-bit values
-    logic [1:0] EXECUTE_REG2;  // 2-bit value
-    logic EXECUTE_REG3[0:2];  // 1-bit values
+    logic [31:0] EXECUTE_REG_1[0:3];  // 32-bit values
+    logic [1:0] EXECUTE_REG_2;  // 2-bit value
+    logic EXECUTE_REG_3[0:2];  // 1-bit values
 
       // Save the various outputs on the negative edge of the clock cycle
     always_ff @ (negedge EXECUTE_CLOCK) begin
@@ -82,12 +83,12 @@ module Execute_State(EXECUTE_CLOCK, EXECUTE_RESET, DR_J_TYPE, DR_B_TYPE, DR_I_TY
     EXECUTE_REG_1[3] <= DR_RS2;         // rs2 from Decode register
 
     // 2- bit value
-    EXECUTE_REG2 <= DR_RF_WR_SEL;       // RF_WR_SEL from Decode register
+    EXECUTE_REG_2 <= DR_RF_WR_SEL;       // RF_WR_SEL from Decode register
 
     // 1-bit values
-    EXECUTE_REG3[0] <= DR_REG_WRITE;    // regWrite from Decode register
-    EXECUTE_REG3[1] <= DR_MEM_WRITE;    // memWrite from Decode register
-    EXECUTE_REG3[2] <= DR_MEM_READ2;    // memRead2 from Decode register
+    EXECUTE_REG_3[0] <= DR_REG_WRITE;    // regWrite from Decode register
+    EXECUTE_REG_3[1] <= DR_MEM_WRITE;    // memWrite from Decode register
+    EXECUTE_REG_3[2] <= DR_MEM_READ2;    // memRead2 from Decode register
 
     end
 

Imm_Gen.sv

@@ -0,0 +1,31 @@
+`timescale 1ns / 1ps
+
+
+module Imm_Gen(IR_INPUT, U_TYPE_OUT, I_TYPE_OUT, S_TYPE_OUT,
+                J_TYPE_OUT, B_TYPE_OUT);
+
+    input [31:0] IR_INPUT; //Input of IR that will undergo concatenation
+    output [31:0] U_TYPE_OUT, I_TYPE_OUT, S_TYPE_OUT, 
+    J_TYPE_OUT, B_TYPE_OUT; //32-bit outputs of each type
+
+    //Now, concatenate and replicate values for output
+
+
+    assign U_TYPE_OUT = {{IR_INPUT [31:12]}, {12'b0}};
+    //Concatenated output of U_TYPE_OUT
+    assign I_TYPE_OUT = { {21{IR_INPUT[31]}}, IR_INPUT[30:20]};
+    //Concatenated output of I_TYPE_OUT
+    assign S_TYPE_OUT = {{21{IR_INPUT[31]}}, IR_INPUT[30:25],
+    IR_INPUT[11:7]};
+    //Concatenated output of S_TYPE_OUT
+    assign B_TYPE_OUT = {{20{IR_INPUT[31]}}, IR_INPUT[7], IR_INPUT[30:25],
+    IR_INPUT[11:8], 1'b0};
+    //Concatenated output of B_TYPE_OUT
+    assign J_TYPE_OUT = {{12{IR_INPUT[31]}}, IR_INPUT[19:12],
+    IR_INPUT[20], IR_INPUT[30:21], 1'b0};
+    //Concatenated output of J_TYPE_OUT
+
+    //Concatenations above were done based on the Hardware 4
+    // lab manual
+
+endmodule