Create README.md

README.md

@@ -0,0 +1,25 @@
+# 6_Ball_Pool
+## Made for NUS Module EE2026 - Digital Design
+## Coded in HDL: Verilog
+Refer to the source files for more info!
+
+#### Project done by: 
+1) Tan Bingxue Gerard
+2) Tan Yixin
+3) Ian Freda Hariyanto
+4) Gandhi Parth Sanjay
+
+Feel free to reach out to me @ [email protected] if you wanna know more!
+
+
+## Pictures of the Project:
+![image](https://github.com/ParthGandhiNUS/EE2026-6_Ball_Pool/assets/111232955/4f852c7b-cc0f-4ac3-a212-f0ca2bc11b5d)
+![image](https://github.com/ParthGandhiNUS/EE2026-6_Ball_Pool/assets/111232955/b3c68564-2134-4c44-a5e9-f84dd42af3e3)
+![image](https://github.com/ParthGandhiNUS/EE2026-6_Ball_Pool/assets/111232955/3d822452-723c-4e2f-9e24-4bc14fbf7982)
+![image](https://github.com/ParthGandhiNUS/EE2026-6_Ball_Pool/assets/111232955/2e3d4bbe-2291-48f9-ac1c-5635c9e38fcb)
+
+### Receiver's Connection:
+![image](https://github.com/ParthGandhiNUS/EE2026-6_Ball_Pool/assets/111232955/714473c1-240f-4325-b09e-af46e22c2138)
+
+### Transmitter's Connection:
+![image](https://github.com/ParthGandhiNUS/EE2026-6_Ball_Pool/assets/111232955/e57b9aa5-5694-408d-8e3a-ff6cfe74b1fc)