grammar and header changes for SPV_INTEL_subgroup_matrix_multiply_acc…

…umulate
KhronosGroup · Dec 12, 2024 · 15a2f0b · 15a2f0b
1 parent 3f17b2a
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diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf
@@ -1284,6 +1284,7 @@ namespace Spv
             GlobalVariableHostAccessINTEL = 6187,
             GlobalVariableFPGADecorationsINTEL = 6189,
             SubgroupBufferPrefetchINTEL = 6220,
+            SubgroupMatrixMultiplyAccumulateINTEL = 6236,
             GroupUniformArithmeticKHR = 6400,
             MaskedGatherScatterINTEL = 6427,
             CacheControlsINTEL = 6441,
@@ -1524,6 +1525,44 @@ namespace Spv
             Max = 0x7fffffff,
         }
 
+        [AllowDuplicates, CRepr] public enum MatrixMultiplyAccumulateOperandsShift
+        {
+            MatrixASignedComponentsINTEL = 0,
+            MatrixBSignedComponentsINTEL = 1,
+            MatrixCBFloat16INTEL = 2,
+            MatrixResultBFloat16INTEL = 3,
+            MatrixAPackedInt8INTEL = 4,
+            MatrixBPackedInt8INTEL = 5,
+            MatrixAPackedInt4INTEL = 6,
+            MatrixBPackedInt4INTEL = 7,
+            MatrixATF32INTEL = 8,
+            MatrixBTF32INTEL = 9,
+            MatrixAPackedFloat16INTEL = 10,
+            MatrixBPackedFloat16INTEL = 11,
+            MatrixAPackedBFloat16INTEL = 12,
+            MatrixBPackedBFloat16INTEL = 13,
+            Max = 0x7fffffff,
+        }
+
+        [AllowDuplicates, CRepr] public enum MatrixMultiplyAccumulateOperandsMask
+        {
+            MaskNone = 0,
+            MatrixASignedComponentsINTEL = 0x00000001,
+            MatrixBSignedComponentsINTEL = 0x00000002,
+            MatrixCBFloat16INTEL = 0x00000004,
+            MatrixResultBFloat16INTEL = 0x00000008,
+            MatrixAPackedInt8INTEL = 0x00000010,
+            MatrixBPackedInt8INTEL = 0x00000020,
+            MatrixAPackedInt4INTEL = 0x00000040,
+            MatrixBPackedInt4INTEL = 0x00000080,
+            MatrixATF32INTEL = 0x00000100,
+            MatrixBTF32INTEL = 0x00000200,
+            MatrixAPackedFloat16INTEL = 0x00000400,
+            MatrixBPackedFloat16INTEL = 0x00000800,
+            MatrixAPackedBFloat16INTEL = 0x00001000,
+            MatrixBPackedBFloat16INTEL = 0x00002000,
+        }
+
         [AllowDuplicates, CRepr] public enum RawAccessChainOperandsShift
         {
             RobustnessPerComponentNV = 0,
@@ -2305,6 +2344,7 @@ namespace Spv
             OpControlBarrierWaitINTEL = 6143,
             OpArithmeticFenceEXT = 6145,
             OpSubgroupBlockPrefetchINTEL = 6221,
+            OpSubgroupMatrixMultiplyAccumulateINTEL = 6237,
             OpGroupIMulKHR = 6401,
             OpGroupFMulKHR = 6402,
             OpGroupBitwiseAndKHR = 6403,

diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json
@@ -10131,6 +10131,22 @@
       "capabilities" : [ "SubgroupBufferPrefetchINTEL" ],
       "version" : "None"
     },
+    {
+      "opname" : "OpSubgroupMatrixMultiplyAccumulateINTEL",
+      "class"  : "Group",
+      "opcode" : 6237,
+      "operands" : [
+        { "kind" : "IdResultType" },
+        { "kind" : "IdResult" },
+        { "kind" : "IdRef", "name" : "'K Dim'" },
+        { "kind" : "IdRef", "name" : "'Matrix A'" },
+        { "kind" : "IdRef", "name" : "'Matrix B'" },
+        { "kind" : "IdRef", "name" : "'Matrix C'" },
+        { "kind" : "MatrixMultiplyAccumulateOperands", "quantifier" : "?" }
+      ],
+      "capabilities" : [ "SubgroupMatrixMultiplyAccumulateINTEL" ],
+      "version" : "None"
+    },
     {
       "opname" : "OpGroupIMulKHR",
       "class"  : "Group",
@@ -16588,6 +16604,12 @@
           "extensions": [ "SPV_INTEL_subgroup_buffer_prefetch" ],
           "version" : "None"
         },
+        {
+          "enumerant" : "SubgroupMatrixMultiplyAccumulateINTEL",
+          "value" : 6236,
+          "extensions": [ "SPV_INTEL_subgroup_matrix_multiply_accumulate" ],
+          "version" : "None"
+        },
         {
           "enumerant" : "GroupUniformArithmeticKHR",
           "value" : 6400,
@@ -16947,6 +16969,87 @@
         }
       ]
     },
+    {
+      "category" : "BitEnum",
+      "kind" : "MatrixMultiplyAccumulateOperands",
+      "enumerants" : [
+        {
+          "enumerant" : "None",
+          "value" : "0x0",
+          "version" : "None"
+        },
+        {
+          "enumerant" : "MatrixASignedComponentsINTEL",
+          "value" : "0x1",
+          "version" : "None"
+        },
+        {
+          "enumerant" : "MatrixBSignedComponentsINTEL",
+          "value" : "0x2",
+          "version" : "None"
+        },
+        {
+          "enumerant" : "MatrixCBFloat16INTEL",
+          "value" : "0x4",
+          "version" : "None"
+        },
+        {
+          "enumerant" : "MatrixResultBFloat16INTEL",
+          "value" : "0x8",
+          "version" : "None"
+        },
+        {
+          "enumerant" : "MatrixAPackedInt8INTEL",
+          "value" : "0x10",
+          "version" : "None"
+        },
+        {
+          "enumerant" : "MatrixBPackedInt8INTEL",
+          "value" : "0x20",
+          "version" : "None"
+        },
+        {
+          "enumerant" : "MatrixAPackedInt4INTEL",
+          "value" : "0x40",
+          "version" : "None"
+        },
+        {
+          "enumerant" : "MatrixBPackedInt4INTEL",
+          "value" : "0x80",
+          "version" : "None"
+        },
+        {
+          "enumerant" : "MatrixATF32INTEL",
+          "value" : "0x100",
+          "version" : "None"
+        },
+        {
+          "enumerant" : "MatrixBTF32INTEL",
+          "value" : "0x200",
+          "version" : "None"
+        },
+        {
+          "enumerant" : "MatrixAPackedFloat16INTEL",
+          "value" : "0x400",
+          "version" : "None"
+        },
+        {
+          "enumerant" : "MatrixBPackedFloat16INTEL",
+          "value" : "0x800",
+          "version" : "None"
+        },
+        {
+          "enumerant" : "MatrixAPackedBFloat16INTEL",
+          "value" : "0x1000",
+          "version" : "None"
+        },
+        {
+          "enumerant" : "MatrixBPackedBFloat16INTEL",
+          "value" : "0x2000",
+          "version" : "None"
+        }
+      ]
+    },
     {
       "category" : "ValueEnum",
       "kind" : "FPEncoding",

diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs
@@ -1283,6 +1283,7 @@ public enum Capability
             GlobalVariableHostAccessINTEL = 6187,
             GlobalVariableFPGADecorationsINTEL = 6189,
             SubgroupBufferPrefetchINTEL = 6220,
+            SubgroupMatrixMultiplyAccumulateINTEL = 6236,
             GroupUniformArithmeticKHR = 6400,
             MaskedGatherScatterINTEL = 6427,
             CacheControlsINTEL = 6441,
@@ -1523,6 +1524,44 @@ public enum NamedMaximumNumberOfRegisters
             Max = 0x7fffffff,
         }
 
+        public enum MatrixMultiplyAccumulateOperandsShift
+        {
+            MatrixASignedComponentsINTEL = 0,
+            MatrixBSignedComponentsINTEL = 1,
+            MatrixCBFloat16INTEL = 2,
+            MatrixResultBFloat16INTEL = 3,
+            MatrixAPackedInt8INTEL = 4,
+            MatrixBPackedInt8INTEL = 5,
+            MatrixAPackedInt4INTEL = 6,
+            MatrixBPackedInt4INTEL = 7,
+            MatrixATF32INTEL = 8,
+            MatrixBTF32INTEL = 9,
+            MatrixAPackedFloat16INTEL = 10,
+            MatrixBPackedFloat16INTEL = 11,
+            MatrixAPackedBFloat16INTEL = 12,
+            MatrixBPackedBFloat16INTEL = 13,
+            Max = 0x7fffffff,
+        }
+
+        public enum MatrixMultiplyAccumulateOperandsMask
+        {
+            MaskNone = 0,
+            MatrixASignedComponentsINTEL = 0x00000001,
+            MatrixBSignedComponentsINTEL = 0x00000002,
+            MatrixCBFloat16INTEL = 0x00000004,
+            MatrixResultBFloat16INTEL = 0x00000008,
+            MatrixAPackedInt8INTEL = 0x00000010,
+            MatrixBPackedInt8INTEL = 0x00000020,
+            MatrixAPackedInt4INTEL = 0x00000040,
+            MatrixBPackedInt4INTEL = 0x00000080,
+            MatrixATF32INTEL = 0x00000100,
+            MatrixBTF32INTEL = 0x00000200,
+            MatrixAPackedFloat16INTEL = 0x00000400,
+            MatrixBPackedFloat16INTEL = 0x00000800,
+            MatrixAPackedBFloat16INTEL = 0x00001000,
+            MatrixBPackedBFloat16INTEL = 0x00002000,
+        }
+
         public enum RawAccessChainOperandsShift
         {
             RobustnessPerComponentNV = 0,
@@ -2304,6 +2343,7 @@ public enum Op
             OpControlBarrierWaitINTEL = 6143,
             OpArithmeticFenceEXT = 6145,
             OpSubgroupBlockPrefetchINTEL = 6221,
+            OpSubgroupMatrixMultiplyAccumulateINTEL = 6237,
             OpGroupIMulKHR = 6401,
             OpGroupFMulKHR = 6402,
             OpGroupBitwiseAndKHR = 6403,

diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h
@@ -1254,6 +1254,7 @@ typedef enum SpvCapability_ {
     SpvCapabilityGlobalVariableHostAccessINTEL = 6187,
     SpvCapabilityGlobalVariableFPGADecorationsINTEL = 6189,
     SpvCapabilitySubgroupBufferPrefetchINTEL = 6220,
+    SpvCapabilitySubgroupMatrixMultiplyAccumulateINTEL = 6236,
     SpvCapabilityGroupUniformArithmeticKHR = 6400,
     SpvCapabilityMaskedGatherScatterINTEL = 6427,
     SpvCapabilityCacheControlsINTEL = 6441,
@@ -1468,6 +1469,42 @@ typedef enum SpvNamedMaximumNumberOfRegisters_ {
     SpvNamedMaximumNumberOfRegistersMax = 0x7fffffff,
 } SpvNamedMaximumNumberOfRegisters;
 
+typedef enum SpvMatrixMultiplyAccumulateOperandsShift_ {
+    SpvMatrixMultiplyAccumulateOperandsMatrixASignedComponentsINTELShift = 0,
+    SpvMatrixMultiplyAccumulateOperandsMatrixBSignedComponentsINTELShift = 1,
+    SpvMatrixMultiplyAccumulateOperandsMatrixCBFloat16INTELShift = 2,
+    SpvMatrixMultiplyAccumulateOperandsMatrixResultBFloat16INTELShift = 3,
+    SpvMatrixMultiplyAccumulateOperandsMatrixAPackedInt8INTELShift = 4,
+    SpvMatrixMultiplyAccumulateOperandsMatrixBPackedInt8INTELShift = 5,
+    SpvMatrixMultiplyAccumulateOperandsMatrixAPackedInt4INTELShift = 6,
+    SpvMatrixMultiplyAccumulateOperandsMatrixBPackedInt4INTELShift = 7,
+    SpvMatrixMultiplyAccumulateOperandsMatrixATF32INTELShift = 8,
+    SpvMatrixMultiplyAccumulateOperandsMatrixBTF32INTELShift = 9,
+    SpvMatrixMultiplyAccumulateOperandsMatrixAPackedFloat16INTELShift = 10,
+    SpvMatrixMultiplyAccumulateOperandsMatrixBPackedFloat16INTELShift = 11,
+    SpvMatrixMultiplyAccumulateOperandsMatrixAPackedBFloat16INTELShift = 12,
+    SpvMatrixMultiplyAccumulateOperandsMatrixBPackedBFloat16INTELShift = 13,
+    SpvMatrixMultiplyAccumulateOperandsMax = 0x7fffffff,
+} SpvMatrixMultiplyAccumulateOperandsShift;
+
+typedef enum SpvMatrixMultiplyAccumulateOperandsMask_ {
+    SpvMatrixMultiplyAccumulateOperandsMaskNone = 0,
+    SpvMatrixMultiplyAccumulateOperandsMatrixASignedComponentsINTELMask = 0x00000001,
+    SpvMatrixMultiplyAccumulateOperandsMatrixBSignedComponentsINTELMask = 0x00000002,
+    SpvMatrixMultiplyAccumulateOperandsMatrixCBFloat16INTELMask = 0x00000004,
+    SpvMatrixMultiplyAccumulateOperandsMatrixResultBFloat16INTELMask = 0x00000008,
+    SpvMatrixMultiplyAccumulateOperandsMatrixAPackedInt8INTELMask = 0x00000010,
+    SpvMatrixMultiplyAccumulateOperandsMatrixBPackedInt8INTELMask = 0x00000020,
+    SpvMatrixMultiplyAccumulateOperandsMatrixAPackedInt4INTELMask = 0x00000040,
+    SpvMatrixMultiplyAccumulateOperandsMatrixBPackedInt4INTELMask = 0x00000080,
+    SpvMatrixMultiplyAccumulateOperandsMatrixATF32INTELMask = 0x00000100,
+    SpvMatrixMultiplyAccumulateOperandsMatrixBTF32INTELMask = 0x00000200,
+    SpvMatrixMultiplyAccumulateOperandsMatrixAPackedFloat16INTELMask = 0x00000400,
+    SpvMatrixMultiplyAccumulateOperandsMatrixBPackedFloat16INTELMask = 0x00000800,
+    SpvMatrixMultiplyAccumulateOperandsMatrixAPackedBFloat16INTELMask = 0x00001000,
+    SpvMatrixMultiplyAccumulateOperandsMatrixBPackedBFloat16INTELMask = 0x00002000,
+} SpvMatrixMultiplyAccumulateOperandsMask;
+
 typedef enum SpvRawAccessChainOperandsShift_ {
     SpvRawAccessChainOperandsRobustnessPerComponentNVShift = 0,
     SpvRawAccessChainOperandsRobustnessPerElementNVShift = 1,
@@ -2245,6 +2282,7 @@ typedef enum SpvOp_ {
     SpvOpControlBarrierWaitINTEL = 6143,
     SpvOpArithmeticFenceEXT = 6145,
     SpvOpSubgroupBlockPrefetchINTEL = 6221,
+    SpvOpSubgroupMatrixMultiplyAccumulateINTEL = 6237,
     SpvOpGroupIMulKHR = 6401,
     SpvOpGroupFMulKHR = 6402,
     SpvOpGroupBitwiseAndKHR = 6403,
@@ -3015,6 +3053,7 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
     case SpvOpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
     case SpvOpArithmeticFenceEXT: *hasResult = true; *hasResultType = true; break;
     case SpvOpSubgroupBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
+    case SpvOpSubgroupMatrixMultiplyAccumulateINTEL: *hasResult = true; *hasResultType = true; break;
     case SpvOpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
     case SpvOpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
     case SpvOpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break;
@@ -3946,6 +3985,7 @@ inline const char* SpvCapabilityToString(SpvCapability value) {
     case SpvCapabilityGlobalVariableHostAccessINTEL: return "GlobalVariableHostAccessINTEL";
     case SpvCapabilityGlobalVariableFPGADecorationsINTEL: return "GlobalVariableFPGADecorationsINTEL";
     case SpvCapabilitySubgroupBufferPrefetchINTEL: return "SubgroupBufferPrefetchINTEL";
+    case SpvCapabilitySubgroupMatrixMultiplyAccumulateINTEL: return "SubgroupMatrixMultiplyAccumulateINTEL";
     case SpvCapabilityGroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR";
     case SpvCapabilityMaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL";
     case SpvCapabilityCacheControlsINTEL: return "CacheControlsINTEL";
@@ -4859,6 +4899,7 @@ inline const char* SpvOpToString(SpvOp value) {
     case SpvOpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL";
     case SpvOpArithmeticFenceEXT: return "OpArithmeticFenceEXT";
     case SpvOpSubgroupBlockPrefetchINTEL: return "OpSubgroupBlockPrefetchINTEL";
+    case SpvOpSubgroupMatrixMultiplyAccumulateINTEL: return "OpSubgroupMatrixMultiplyAccumulateINTEL";
     case SpvOpGroupIMulKHR: return "OpGroupIMulKHR";
     case SpvOpGroupFMulKHR: return "OpGroupFMulKHR";
     case SpvOpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR";