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Possible fix to BRAM uint0_t size issue... #201

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Possible fix to BRAM uint0_t size issue... #201

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7ec0bcf
Possible fix to uint0_t RAM function
Paulo-D2000 Jul 2, 2024
5b336f3
Merge pull request #1 from Paulo-D2000/Paulo-D2000-patch-1
Paulo-D2000 Jul 2, 2024
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6 changes: 3 additions & 3 deletions src/SW_LIB.py
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Original file line number Diff line number Diff line change
Expand Up @@ -1756,7 +1756,7 @@ def GET_MEM_H_LOGIC_LOOKUP(parser_state):
dim = dims[i]
addr_t = (
"uint"
+ str(int(math.ceil(math.log(dim, 2))))
+ str(int(math.ceil(math.log(dim, 2)))+1) #round up by 1
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@JulianKemmerer JulianKemmerer Jul 2, 2024 •
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Reasonable, but I prefer to keep the width exact as needed

For ex. you need two address bits to address four things
but the round up by one makes it 3 bits for dim=4

hmm maybe just need a simple 'its uint1 unless >1 then do math as is'

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There is another place this math occurs at for sizing muxes in this same file

PipelineC/src/SW_LIB.py

Line 2060 in bf7e57f

sel_width = int(math.ceil(math.log(n, 2)))

mind changing there too?

And searching repo I found one more place

PipelineC/src/C_TO_LOGIC.py

Line 2307 in bf7e57f

"uint" + str(int(math.ceil(math.log(first_dim, 2)))) + "_t"

could maybe make a common helper func in https://github.com/JulianKemmerer/PipelineC/blob/master/src/utilities.py
but not critical

+ "_t"
)
text += addr_t + " addr" + str(i) + ", "
Expand All @@ -1766,7 +1766,7 @@ def GET_MEM_H_LOGIC_LOOKUP(parser_state):
dim = dims[i]
addr_t = (
"uint"
+ str(int(math.ceil(math.log(dim, 2))))
+ str(int(math.ceil(math.log(dim, 2)))+1) #round up by 1
+ "_t"
)
text += (
Expand Down Expand Up @@ -8358,4 +8358,4 @@ def GET_BIN_OP_DIV_INT_N_C_CODE(partially_complete_logic, out_dir, parser_state)
# print(text)
# sys.exit(-1)

return text
return text