RISC-V Pipelined CPU

Homework of the course Computer Architecture, 2021 Fall, NTUCSIE.

The CPU has following features,

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
ALU.v		ALU.v
ALU_Control.v		ALU_Control.v
Branch_PC.v		Branch_PC.v
CPU.v		CPU.v
Control.v		Control.v
Data_Memory.v		Data_Memory.v
Forwarding.v		Forwarding.v
Hazard_Detection.v		Hazard_Detection.v
Instruction_Memory.v		Instruction_Memory.v
Mux32.v		Mux32.v
PC.v		PC.v
Pipeline_Reg.v		Pipeline_Reg.v
README.md		README.md
Registers.v		Registers.v
Sign_Extend.v		Sign_Extend.v
cache.txt		cache.txt
dcache_controller.v		dcache_controller.v
dcache_sram.v		dcache_sram.v
header.v		header.v
instruction.txt		instruction.txt
testbench.v		testbench.v

Provide feedback