ddr4_sdram_model_wrapper.sv

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//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor             : Xilinx
// \   \   \/     Version            : 1.0
//  \   \         Application        : MIG
//  /   /         Filename           : ddr4_sdram_model_wrapper.sv
// /___/   /\     Date Last Modified : $Date: $
// \   \  /  \    Date Created       : Fri Nov 14 2014
//  \___\/\___\
//
// Device           : UltraScale
// Design Name      : Model_wrapper
// Purpose          :
// Reference        :
// Revision History :
//*****************************************************************************


`define DDR4_4G_X8 
`define DDR4_750_Timing
// Added define SILENT to avoid timeset setting display messages in transcript
`define SILENT
`define FIXED_2666

// `include "arch_package.sv"
// `include "proj_package.sv"
// `include "interface.sv"
// `include "ddr4_model.sv"