Comment out unneeded clock driving circuitry in the testbench.

FavoritoHJS · Aug 27, 2024 · f8e0d8a · f8e0d8a
1 parent 6e3b9c3
commit f8e0d8a
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/test/tb.v b/test/tb.v
@@ -23,7 +23,8 @@ module tb ();
   wire [7:0] uio_out;
   wire [7:0] uio_oe;
   //https://www.chipverify.com/verilog/verilog-testbench-simulation
-  always #1 clk = ~clk;
+  //Clock is driven from the testbench.
+  //always #1 clk = ~clk;
 
   // Replace tt_um_example with your module name:
   tt_um_favoritohjs_scroller user_project (