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Optimize lock dec #3475

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merged 2 commits into from
Feb 29, 2024
Merged

Optimize lock dec #3475

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fed5e6d
OpcodeDispatcher: use fetchadd for atomic DEC
alyssarosenzweig Feb 29, 2024
1ab234f
InstCountCI: Update
alyssarosenzweig Feb 29, 2024
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4 changes: 3 additions & 1 deletion FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3571,7 +3571,9 @@ void OpDispatchBuilder::DECOp(OpcodeArgs) {
HandledLock = true;
auto DestAddress = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, {.LoadData = false});
DestAddress = AppendSegmentOffset(DestAddress, Op->Flags);
Dest = _AtomicFetchSub(OpSizeFromSrc(Op), OneConst, DestAddress);

// Use Add instead of Sub to avoid a NEG
Dest = _AtomicFetchAdd(OpSizeFromSrc(Op), _Constant(Size, -1), DestAddress);
} else {
Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, {.AllowUpperGarbage = Size >= 32});
}
Expand Down
22 changes: 10 additions & 12 deletions unittests/InstructionCountCI/Atomics.json
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Original file line number Diff line number Diff line change
Expand Up @@ -1431,8 +1431,8 @@
"Comment": "GROUP3 0xfe /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"neg w1, w20",
"ldaddalb w1, w27, [x4]",
"mov w21, #0xff",
"ldaddalb w21, w27, [x4]",
"cset w21, hs",
"lsl w0, w27, #24",
"cmp w0, w20, lsl #24",
Expand Down Expand Up @@ -1541,8 +1541,8 @@
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"neg w1, w20",
"ldaddalh w1, w27, [x4]",
"mov w21, #0xffff",
"ldaddalh w21, w27, [x4]",
"cset w21, hs",
"lsl w0, w27, #16",
"cmp w0, w20, lsl #16",
Expand All @@ -1553,12 +1553,11 @@
]
},
"lock dec dword [rax]": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"neg w1, w20",
"ldaddal w1, w27, [x4]",
"mov w20, #0xffffffff",
"ldaddal w20, w27, [x4]",
"cset w20, hs",
"subs w26, w27, #0x1 (1)",
"mrs x21, nzcv",
Expand All @@ -1569,12 +1568,11 @@
]
},
"lock dec qword [rax]": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"neg x1, x20",
"ldaddal x1, x27, [x4]",
"mov x20, #0xffffffffffffffff",
"ldaddal x20, x27, [x4]",
"cset w20, hs",
"subs x26, x27, #0x1 (1)",
"mrs x21, nzcv",
Expand Down
22 changes: 10 additions & 12 deletions unittests/InstructionCountCI/FlagM/Atomics.json
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Original file line number Diff line number Diff line change
Expand Up @@ -1300,8 +1300,8 @@
"Comment": "GROUP3 0xfe /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"neg w1, w20",
"ldaddalb w1, w27, [x4]",
"mov w21, #0xff",
"ldaddalb w21, w27, [x4]",
"cset w21, hs",
"lsl w0, w27, #24",
"cmp w0, w20, lsl #24",
Expand Down Expand Up @@ -1400,8 +1400,8 @@
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"neg w1, w20",
"ldaddalh w1, w27, [x4]",
"mov w21, #0xffff",
"ldaddalh w21, w27, [x4]",
"cset w21, hs",
"lsl w0, w27, #16",
"cmp w0, w20, lsl #16",
Expand All @@ -1410,24 +1410,22 @@
]
},
"lock dec dword [rax]": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 5,
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"neg w1, w20",
"ldaddal w1, w27, [x4]",
"mov w20, #0xffffffff",
"ldaddal w20, w27, [x4]",
"cset w20, hs",
"subs w26, w27, #0x1 (1)",
"rmif x20, #63, #nzCv"
]
},
"lock dec qword [rax]": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 5,
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"neg x1, x20",
"ldaddal x1, x27, [x4]",
"mov x20, #0xffffffffffffffff",
"ldaddal x20, x27, [x4]",
"cset w20, hs",
"subs x26, x27, #0x1 (1)",
"rmif x20, #63, #nzCv"
Expand Down
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