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instcount: Ensure predicate cache is reset when control flow leaves b…
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@pmatos
pmatos committed Jan 22, 2025
1 parent 41f51a7 commit bfd3a81
Showing 1 changed file with 44 additions and 44 deletions.
88 changes: 44 additions & 44 deletions unittests/InstructionCountCI/X87ldst-SVE.json
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Original file line number Diff line number Diff line change
Expand Up @@ -20,8 +20,8 @@
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ptrue p2.h, vl5",
"st1h {z2.h}, p2, [x4]",
"ptrue p5.h, vl5",
"st1h {z2.h}, p5, [x4]",
"ldrb w21, [x28, #1298]",
"mov w22, #0x1",
"lsl w22, w22, w20",
Expand All @@ -43,8 +43,8 @@
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ptrue p2.h, vl5",
"st1h {z2.h}, p2, [x4]",
"ptrue p5.h, vl5",
"st1h {z2.h}, p5, [x4]",
"ldrb w21, [x28, #1298]",
"mov w22, #0x1",
"lsl w23, w22, w20",
Expand All @@ -55,9 +55,9 @@
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ptrue p2.h, vl5",
"ptrue p5.h, vl5",
"add x21, x4, #0xa (10)",
"st1h {z2.h}, p2, [x21]",
"st1h {z2.h}, p5, [x21]",
"ldrb w21, [x28, #1298]",
"lsl w22, w22, w20",
"bic w21, w21, w22",
Expand All @@ -84,8 +84,8 @@
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ptrue p2.h, vl5",
"st1h {z2.h}, p2, [x4]",
"ptrue p5.h, vl5",
"st1h {z2.h}, p5, [x4]",
"ldrb w21, [x28, #1298]",
"mov w22, #0x1",
"lsl w23, w22, w20",
Expand All @@ -96,9 +96,9 @@
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ptrue p2.h, vl5",
"ptrue p5.h, vl5",
"add x21, x4, #0xa (10)",
"st1h {z2.h}, p2, [x21]",
"st1h {z2.h}, p5, [x21]",
"ldrb w21, [x28, #1298]",
"lsl w23, w22, w20",
"bic w21, w21, w23",
Expand All @@ -108,9 +108,9 @@
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ptrue p2.h, vl5",
"ptrue p5.h, vl5",
"add x21, x4, #0x14 (20)",
"st1h {z2.h}, p2, [x21]",
"st1h {z2.h}, p5, [x21]",
"ldrb w21, [x28, #1298]",
"lsl w23, w22, w20",
"bic w21, w21, w23",
Expand All @@ -120,9 +120,9 @@
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ptrue p2.h, vl5",
"ptrue p5.h, vl5",
"add x21, x4, #0x1e (30)",
"st1h {z2.h}, p2, [x21]",
"st1h {z2.h}, p5, [x21]",
"ldrb w21, [x28, #1298]",
"lsl w23, w22, w20",
"bic w21, w21, w23",
Expand All @@ -132,9 +132,9 @@
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ptrue p2.h, vl5",
"ptrue p5.h, vl5",
"add x21, x4, #0x28 (40)",
"st1h {z2.h}, p2, [x21]",
"st1h {z2.h}, p5, [x21]",
"ldrb w21, [x28, #1298]",
"lsl w23, w22, w20",
"bic w21, w21, w23",
Expand All @@ -144,9 +144,9 @@
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ptrue p2.h, vl5",
"ptrue p5.h, vl5",
"add x21, x4, #0x32 (50)",
"st1h {z2.h}, p2, [x21]",
"st1h {z2.h}, p5, [x21]",
"ldrb w21, [x28, #1298]",
"lsl w23, w22, w20",
"bic w21, w21, w23",
Expand All @@ -156,9 +156,9 @@
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ptrue p2.h, vl5",
"ptrue p5.h, vl5",
"add x21, x4, #0x3c (60)",
"st1h {z2.h}, p2, [x21]",
"st1h {z2.h}, p5, [x21]",
"ldrb w21, [x28, #1298]",
"lsl w23, w22, w20",
"bic w21, w21, w23",
Expand All @@ -168,9 +168,9 @@
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"ptrue p2.h, vl5",
"ptrue p5.h, vl5",
"add x21, x4, #0x46 (70)",
"st1h {z2.h}, p2, [x21]",
"st1h {z2.h}, p5, [x21]",
"ldrb w21, [x28, #1298]",
"lsl w22, w22, w20",
"bic w21, w21, w22",
Expand All @@ -184,8 +184,8 @@
"ExpectedInstructionCount": 13,
"Comment": "Single 80-bit store.",
"ExpectedArm64ASM": [
"ptrue p2.h, vl5",
"ld1h {z2.h}, p2/z, [x4]",
"ptrue p5.h, vl5",
"ld1h {z2.h}, p5/z, [x4]",
"ldrb w20, [x28, #1019]",
"mov w21, #0x1",
"sub w20, w20, #0x1 (1)",
Expand All @@ -207,11 +207,11 @@
"fld tword [rax+10]"
],
"ExpectedArm64ASM": [
"ptrue p2.h, vl5",
"ld1h {z2.h}, p2/z, [x4]",
"ptrue p5.h, vl5",
"ld1h {z2.h}, p5/z, [x4]",
"add x20, x4, #0xa (10)",
"ptrue p2.h, vl5",
"ld1h {z3.h}, p2/z, [x20]",
"ptrue p5.h, vl5",
"ld1h {z3.h}, p5/z, [x20]",
"ldrb w20, [x28, #1019]",
"sub w20, w20, #0x2 (2)",
"and w20, w20, #0x7",
Expand Down Expand Up @@ -245,29 +245,29 @@
"fld tword [rax+70]"
],
"ExpectedArm64ASM": [
"ptrue p2.h, vl5",
"ld1h {z2.h}, p2/z, [x4]",
"ptrue p5.h, vl5",
"ld1h {z2.h}, p5/z, [x4]",
"add x20, x4, #0xa (10)",
"ptrue p2.h, vl5",
"ld1h {z3.h}, p2/z, [x20]",
"ptrue p5.h, vl5",
"ld1h {z3.h}, p5/z, [x20]",
"add x20, x4, #0x14 (20)",
"ptrue p2.h, vl5",
"ld1h {z4.h}, p2/z, [x20]",
"ptrue p5.h, vl5",
"ld1h {z4.h}, p5/z, [x20]",
"add x20, x4, #0x1e (30)",
"ptrue p2.h, vl5",
"ld1h {z5.h}, p2/z, [x20]",
"ptrue p5.h, vl5",
"ld1h {z5.h}, p5/z, [x20]",
"add x20, x4, #0x28 (40)",
"ptrue p2.h, vl5",
"ld1h {z6.h}, p2/z, [x20]",
"ptrue p5.h, vl5",
"ld1h {z6.h}, p5/z, [x20]",
"add x20, x4, #0x32 (50)",
"ptrue p2.h, vl5",
"ld1h {z7.h}, p2/z, [x20]",
"ptrue p5.h, vl5",
"ld1h {z7.h}, p5/z, [x20]",
"add x20, x4, #0x3c (60)",
"ptrue p2.h, vl5",
"ld1h {z8.h}, p2/z, [x20]",
"ptrue p5.h, vl5",
"ld1h {z8.h}, p5/z, [x20]",
"add x20, x4, #0x46 (70)",
"ptrue p2.h, vl5",
"ld1h {z9.h}, p2/z, [x20]",
"ptrue p5.h, vl5",
"ld1h {z9.h}, p5/z, [x20]",
"ldrb w20, [x28, #1019]",
"sub w20, w20, #0x8 (8)",
"and w20, w20, #0x7",
Expand Down

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