OpcodeDispatcher: Fixes disabling TSO access on RSP SIB stores

GPR Direct/Indirect already had this and SIB version also already
supported on the load side. Fixes this missed behaviour.

FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp

@@ -4475,9 +4475,6 @@ OrderedNode *OpDispatchBuilder::LoadSource_WithOpSize(RegisterClassType Class, X
           auto Constant = _Constant(GPRSize * 8, Operand.Data.SIB.Scale);
           Tmp = _Mul(IR::SizeToOpSize(GPRSize), Tmp, Constant);
         }
-        if (Operand.Data.SIB.Index == FEXCore::X86State::REG_RSP && AccessType == MemoryAccessType::DEFAULT) {
-          AccessType = MemoryAccessType::NONTSO;
-        }
       }
 
       if (Operand.Data.SIB.Base != FEXCore::X86State::REG_INVALID) {
@@ -4489,10 +4486,6 @@ OrderedNode *OpDispatchBuilder::LoadSource_WithOpSize(RegisterClassType Class, X
         else {
           Tmp = GPR;
         }
-
-        if (Operand.Data.SIB.Base == FEXCore::X86State::REG_RSP && AccessType == MemoryAccessType::DEFAULT) {
-          AccessType = MemoryAccessType::NONTSO;
-        }
       }
     }
 
@@ -4513,6 +4506,12 @@ OrderedNode *OpDispatchBuilder::LoadSource_WithOpSize(RegisterClassType Class, X
       }
     }
 
+    if ((Operand.Data.SIB.Base == FEXCore::X86State::REG_RSP ||
+         Operand.Data.SIB.Index == FEXCore::X86State::REG_RSP)
+        && AccessType == MemoryAccessType::DEFAULT) {
+      AccessType = MemoryAccessType::NONTSO;
+    }
+
     LoadableType = true;
   }
   else {
@@ -4762,6 +4761,12 @@ void OpDispatchBuilder::StoreResult_WithOpSize(FEXCore::IR::RegisterClassType Cl
       MemStoreDst = _Bfe(IR::SizeToOpSize(std::max<uint8_t>(4u, AddrSize)), AddrSize * 8, 0, MemStoreDst);
     }
 
+    if ((Operand.Data.SIB.Base == FEXCore::X86State::REG_RSP ||
+         Operand.Data.SIB.Index == FEXCore::X86State::REG_RSP)
+        && AccessType == MemoryAccessType::DEFAULT) {
+      AccessType = MemoryAccessType::NONTSO;
+    }
+
     MemStore = true;
   }