Various changes

Renamed some macros, added helper macros to replace raw arithmetic operations,
Added missing DCONTEXT_ACTUAL_TO_TLS_OFFSET.

core/arch/arch_exports.h

@@ -1836,13 +1836,17 @@ typedef struct _rseq_entry_state_t {
 #endif
 
 #if (DCONTEXT_TLS_MIDPTR_OFFSET != 0)
-#    define CONTEXT_PTR_TO_HEAD(x) \
-        ((dcontext_t *)(((ptr_uint_t)x) - DCONTEXT_TLS_MIDPTR_OFFSET))
-#    define CONTEXT_HEAD_TO_PTR(x) \
+#    define DCONTEXT_ACTUAL_TO_TLS_PTR(x) \
         ((dcontext_t *)(((ptr_uint_t)x) + DCONTEXT_TLS_MIDPTR_OFFSET))
+#    define DCONTEXT_TLS_TO_ACTUAL_PTR(x) \
+        ((dcontext_t *)(((ptr_uint_t)x) - DCONTEXT_TLS_MIDPTR_OFFSET))
+#    define DCONTEXT_ACTUAL_TO_TLS_OFFSET(x) (x - DCONTEXT_TLS_MIDPTR_OFFSET)
+#    define DCONTEXT_TLS_TO_ACTUAL_OFFSET(x) (x + DCONTEXT_TLS_MIDPTR_OFFSET)
 #else
-#    define CONTEXT_PTR_TO_HEAD(x) x
-#    define CONTEXT_HEAD_TO_PTR(x) x
+#    define DCONTEXT_ACTUAL_TO_TLS_PTR(x) x
+#    define DCONTEXT_TLS_TO_ACTUAL_PTR(x) x
+#    define DCONTEXT_ACTUAL_TO_TLS_OFFSET(x) x
+#    define DCONTEXT_TLS_TO_ACTUAL_OFFSET(x) x
 #endif
 
 #endif /* _ARCH_EXPORTS_H_ */

core/arch/emit_utils_shared.c

@@ -2182,15 +2182,15 @@ emit_fcache_enter_common(dcontext_t *dcontext, generated_code_t *code, byte *pc,
     APP(&ilist,
         INSTR_CREATE_ld(
             dcontext, opnd_create_reg(DR_REG_A0),
-            opnd_create_base_disp(REG_DCXT, DR_REG_NULL, 0,
-                                  (int)REG_OFFSET(DR_REG_A0) - DCONTEXT_TLS_MIDPTR_OFFSET,
-                                  OPSZ_8)));
+            opnd_create_base_disp(
+                REG_DCXT, DR_REG_NULL, 0,
+                DCONTEXT_ACTUAL_TO_TLS_OFFSET((int)REG_OFFSET(DR_REG_A0)), OPSZ_8)));
     APP(&ilist,
         INSTR_CREATE_ld(
             dcontext, opnd_create_reg(DR_REG_A1),
-            opnd_create_base_disp(REG_DCXT, DR_REG_NULL, 0,
-                                  (int)REG_OFFSET(DR_REG_A1) - DCONTEXT_TLS_MIDPTR_OFFSET,
-                                  OPSZ_8)));
+            opnd_create_base_disp(
+                REG_DCXT, DR_REG_NULL, 0,
+                DCONTEXT_ACTUAL_TO_TLS_OFFSET((int)REG_OFFSET(DR_REG_A1)), OPSZ_8)));
 
     APP(&ilist,
         INSTR_CREATE_sd(

core/arch/riscv64/emit_utils.c

@@ -704,7 +704,7 @@ append_restore_simd_reg(dcontext_t *dcontext, instrlist_t *ilist, bool absolute)
             INSTR_CREATE_addi(
                 dcontext, opnd_create_reg(DR_REG_A1), opnd_create_reg(REG_DCXT),
                 opnd_create_immed_int(
-                    VREG_OFFSET(DR_REG_VR0) - DCONTEXT_TLS_MIDPTR_OFFSET, OPSZ_12b)));
+                    DCONTEXT_ACTUAL_TO_TLS_OFFSET(VREG_OFFSET(DR_REG_VR0)), OPSZ_12b)));
         /* For the following vector instructions, set the element width to 8b, and use 8
          * registers as a group (lmul=8).
          */
@@ -842,7 +842,7 @@ append_save_simd_reg(dcontext_t *dcontext, instrlist_t *ilist, bool absolute)
             INSTR_CREATE_addi(
                 dcontext, opnd_create_reg(DR_REG_A1), opnd_create_reg(REG_DCXT),
                 opnd_create_immed_int(
-                    VREG_OFFSET(DR_REG_VR0) - DCONTEXT_TLS_MIDPTR_OFFSET, OPSZ_12b)));
+                    DCONTEXT_ACTUAL_TO_TLS_OFFSET(VREG_OFFSET(DR_REG_VR0)), OPSZ_12b)));
         /* For the following vector instructions, set the element width to 8b, and use 8
          * registers as a group (lmul=8).
          */

core/dispatch.c

@@ -571,7 +571,7 @@ enter_fcache(dcontext_t *dcontext, fcache_enter_func_t entry, cache_pc pc)
      */
     PTHREAD_JIT_READ();
 
-    (*entry)(CONTEXT_HEAD_TO_PTR(dcontext));
+    (*entry)(DCONTEXT_ACTUAL_TO_TLS_PTR(dcontext));
     IF_WINDOWS(ASSERT_NOT_REACHED()); /* returns for signals on unix */
 }
 

core/ir/opnd_shared.c

@@ -2899,15 +2899,15 @@ dcontext_opnd_common(dcontext_t *dcontext, bool absolute, reg_id_t basereg, int
             absolute ? REG_NULL : (basereg == REG_NULL ? REG_DCXT_PROT : basereg),
             REG_NULL, 0,
             ((int)(ptr_int_t)(absolute ? dcontext->upcontext.separate_upcontext : 0)) +
-                offs,
+                DCONTEXT_ACTUAL_TO_TLS_OFFSET(offs),
             size);
     } else {
         if (offs >= sizeof(unprotected_context_t))
             offs -= sizeof(unprotected_context_t);
         return opnd_create_base_disp(
             absolute ? REG_NULL : (basereg == REG_NULL ? REG_DCXT : basereg), REG_NULL, 0,
-            ((int)(ptr_int_t)(absolute ? dcontext : 0)) + offs -
-                DCONTEXT_TLS_MIDPTR_OFFSET,
+            ((int)(ptr_int_t)(absolute ? dcontext : 0)) +
+                DCONTEXT_ACTUAL_TO_TLS_OFFSET(offs),
             size);
     }
 }

core/unix/os.c

@@ -3144,7 +3144,7 @@ get_thread_private_dcontext(void)
                pid_cached != get_process_id());
     });
     READ_TLS_SLOT_IMM(TLS_DCONTEXT_OFFSET, dcontext);
-    return CONTEXT_PTR_TO_HEAD(dcontext);
+    return DCONTEXT_TLS_TO_ACTUAL_PTR(dcontext);
 #else
     /* Assumption: no lock needed on a read => no race conditions between
      * reading and writing same tid!  Since both get and set are only for
@@ -3156,7 +3156,7 @@ get_thread_private_dcontext(void)
     if (tls_table != NULL) {
         for (i = 0; i < MAX_THREADS; i++) {
             if (tls_table[i].tid == tid) {
-                return CONTEXT_PTR_TO_HEAD(tls_table[i].dcontext);
+                return DCONTEXT_TLS_TO_ACTUAL_PTR(tls_table[i].dcontext);
             }
         }
     }
@@ -3168,7 +3168,7 @@ get_thread_private_dcontext(void)
 void
 set_thread_private_dcontext(dcontext_t *dcontext)
 {
-    dcontext = CONTEXT_HEAD_TO_PTR(dcontext);
+    dcontext = DCONTEXT_ACTUAL_TO_TLS_PTR(dcontext);
 #ifdef HAVE_TLS
     ASSERT(is_thread_tls_allocated());
     WRITE_TLS_SLOT_IMM(TLS_DCONTEXT_OFFSET, dcontext);