This is RISCV soft processor designed that can be deployed to Cyclone-V FPGA. The hardware tool that is was used for testing is DE10-Nano development kit from Terasic.
This is a fourth year capstone project and this project is not 100% complete. One of the aims is to perform read & write operation to the physical SDRAM that is on DE10-NANO board. While this is implemented in the design, the behaviour of the memory access operations (on hardware) is not correct. I spent hours trying to fix this problem but I stopped due to the time constrains to work on this project the limited hardware testing tools.
Other that the memory access operations, the processor should be able to execute the base 32-bit RISCV instructions. This project is considered in version ALPHA so you may encounter bugs
- The Quartus project can be found in
quartus-project
folder, open theRISCV_CPU_FPGA.qpf
file - To initialise the ROM with RISCV instructions, follow these steps:
- Make sure you have
.mif
file in thequartus-project
directory. (to compline the instructions, follow the steps in the next section) - Open
CPU_pipelined.bdf
file - Right-click on
rom
modules, then properties - Add the full path of the
.mif
in theINSTRUCTIONS_INIT_FILE
parameter.
- Make sure you have
- Click on the "Start Compilation" button from the tool bar, or use the shortcut
Ctrl+L
. - Before deploying the design to the board, make sure you the BootLoader image from Terasic is written in the SD Card to initialise the SDRAM controller properly.
- Open the "Programmer" window by navigating to Tools -> Programmer.
- Make sure you have your DE10-Nano board connected to your computer
- Select the FPGA chip, then click on "Add File" or "Change File".
- Select the
.sof
file from the project directory. Most likely namedRISCV_CPU_FPGA.sof
- Click on Start button.
NOTE: Windows users should have a program that can run bash scripts e.g. git in order to run assemble-inst.sh
file
- Download RARS tool from github and place the
.jar
file in the root directory of this project - Write your RISCV instructions in
code.s
file. - Run
assemble-inst.sh
...