From 162b377e96bfabf072b05e9c63a823d064edceb5 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Wed, 15 Jan 2025 18:04:58 +0800 Subject: [PATCH 1/6] west.yml: update hal_nxp to the pull-request support for mimx9131 Update the hal_nxp revison to the depended PR support for mimx9131. Signed-off-by: Hou Zhiqiang --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index eb8ac3785d30..f78b2662e0e6 100644 --- a/west.yml +++ b/west.yml @@ -203,7 +203,7 @@ manifest: groups: - hal - name: hal_nxp - revision: c15dd51d7af27593e38b65b1443a350e9d2de64f + revision: pull/497/head path: modules/hal/nxp groups: - hal From dc6c8e4c14582bb0b5e5bb6337888ac4fa0c654b Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Sun, 12 Jan 2025 22:52:21 +0800 Subject: [PATCH 2/6] dts: arm64: nxp: add device tree for SoC imx91 Add DTSi file for i.MX91. Signed-off-by: Hou Zhiqiang --- dts/arm64/nxp/nxp_mimx91.dtsi | 95 +++++++++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+) create mode 100644 dts/arm64/nxp/nxp_mimx91.dtsi diff --git a/dts/arm64/nxp/nxp_mimx91.dtsi b/dts/arm64/nxp/nxp_mimx91.dtsi new file mode 100644 index 000000000000..872205719bf1 --- /dev/null +++ b/dts/arm64/nxp/nxp_mimx91.dtsi @@ -0,0 +1,95 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0>; + }; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + interrupt-parent = <&gic>; + }; + + psci: psci { + compatible = "arm,psci-1.1"; + method = "smc"; + }; + + gic: interrupt-controller@48000000 { + compatible = "arm,gic-v3", "arm,gic"; + reg = <0x48000000 0x10000>, /* GIC Dist */ + <0x48040000 0xc0000>; /* GICR (RD_base + SGI_base) */ + interrupt-controller; + #interrupt-cells = <4>; + status = "okay"; + }; + + iomuxc: iomuxc@443c0000 { + compatible = "nxp,imx-iomuxc"; + reg = <0x443c0000 DT_SIZE_K(64)>; + status = "okay"; + pinctrl: pinctrl { + status = "okay"; + compatible = "nxp,imx93-pinctrl"; + }; + }; + + ana_pll: ana_pll@44480000 { + compatible = "nxp,imx-ana"; + reg = <0x44480000 DT_SIZE_K(64)>; + }; + + ccm: ccm@44450000 { + compatible = "nxp,imx-ccm-rev2"; + reg = <0x44450000 DT_SIZE_K(64)>; + #clock-cells = <3>; + }; + + lpuart1: serial@44380000 { + compatible = "nxp,imx-lpuart", "nxp,lpuart"; + reg = <0x44380000 DT_SIZE_K(64)>; + interrupts = ; + interrupt-names = "irq_0"; + interrupt-parent = <&gic>; + clocks = <&ccm IMX_CCM_LPUART1_CLK 0x6c 24>; + status = "disabled"; + }; + + lpuart2: serial@44390000 { + compatible = "nxp,imx-lpuart", "nxp,lpuart"; + reg = <0x44390000 DT_SIZE_K(64)>; + interrupts = ; + interrupt-names = "irq_0"; + interrupt-parent = <&gic>; + clocks = <&ccm IMX_CCM_LPUART2_CLK 0x6c 24>; + status = "disabled"; + }; +}; From da2463efa686df266929444ecdb6317a13ac0815 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Sun, 12 Jan 2025 23:14:34 +0800 Subject: [PATCH 3/6] soc: nxp: add SoC imx91 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The i.MX 91 SoC’s integrated EdgeLock® Secure Enclave provides security features including lifecycle management, tamper detection, secure boot and a simplified path to certifications. The i.MX 91 family features an Arm® Cortex®-A55 running at up to 1.4GHz, support for modern LPDDR4 memory to enable platform longevity, dual Gigabit Ethernet and dual USB ports, along with a rich set of peripherals targeting medical, industrial and consumer IoT market segments. Signed-off-by: Hou Zhiqiang --- soc/nxp/imx/imx9/CMakeLists.txt | 6 +- soc/nxp/imx/imx9/imx91/CMakeLists.txt | 8 ++ soc/nxp/imx/imx9/imx91/Kconfig | 12 +++ soc/nxp/imx/imx9/imx91/Kconfig.defconfig | 8 ++ .../imx/imx9/imx91/Kconfig.defconfig.mimx91 | 21 +++++ soc/nxp/imx/imx9/imx91/Kconfig.soc | 21 +++++ soc/nxp/imx/imx9/imx91/mmu_regions.c | 38 +++++++++ soc/nxp/imx/imx9/imx91/pinctrl_soc.h | 79 +++++++++++++++++++ soc/nxp/imx/soc.yml | 1 + 9 files changed, 192 insertions(+), 2 deletions(-) create mode 100644 soc/nxp/imx/imx9/imx91/CMakeLists.txt create mode 100644 soc/nxp/imx/imx9/imx91/Kconfig create mode 100644 soc/nxp/imx/imx9/imx91/Kconfig.defconfig create mode 100644 soc/nxp/imx/imx9/imx91/Kconfig.defconfig.mimx91 create mode 100644 soc/nxp/imx/imx9/imx91/Kconfig.soc create mode 100644 soc/nxp/imx/imx9/imx91/mmu_regions.c create mode 100644 soc/nxp/imx/imx9/imx91/pinctrl_soc.h diff --git a/soc/nxp/imx/imx9/CMakeLists.txt b/soc/nxp/imx/imx9/CMakeLists.txt index 369519ad7b3b..7c0803be8074 100644 --- a/soc/nxp/imx/imx9/CMakeLists.txt +++ b/soc/nxp/imx/imx9/CMakeLists.txt @@ -1,7 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # SPDX-License-Identifier: Apache-2.0 -if(CONFIG_SOC_MIMX9352) +if(CONFIG_SOC_MIMX9131) + add_subdirectory(imx91) +elseif(CONFIG_SOC_MIMX9352) add_subdirectory(imx93) elseif(CONFIG_SOC_MIMX9596) add_subdirectory(imx95) diff --git a/soc/nxp/imx/imx9/imx91/CMakeLists.txt b/soc/nxp/imx/imx9/imx91/CMakeLists.txt new file mode 100644 index 000000000000..4d342af6f139 --- /dev/null +++ b/soc/nxp/imx/imx9/imx91/CMakeLists.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +zephyr_compile_options(-Wno-misleading-indentation) + +zephyr_include_directories(.) + +zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/imx/imx9/imx91/Kconfig b/soc/nxp/imx/imx9/imx91/Kconfig new file mode 100644 index 000000000000..a528effa490c --- /dev/null +++ b/soc/nxp/imx/imx9/imx91/Kconfig @@ -0,0 +1,12 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_MIMX9131 + select ARM64 + select CPU_CORTEX_A55 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS + select HAS_MCUX if CLOCK_CONTROL + select HAS_MCUX_CCM_REV2 if CLOCK_CONTROL + select HAS_MCUX_IOMUXC if PINCTRL + select HAS_MCUX_CACHE + select KERNEL_DIRECT_MAP if HAS_MCUX diff --git a/soc/nxp/imx/imx9/imx91/Kconfig.defconfig b/soc/nxp/imx/imx9/imx91/Kconfig.defconfig new file mode 100644 index 000000000000..1f176ff47482 --- /dev/null +++ b/soc/nxp/imx/imx9/imx91/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_IMX9 + +rsource "Kconfig.defconfig.*" + +endif # SOC_SERIES_IMX9 diff --git a/soc/nxp/imx/imx9/imx91/Kconfig.defconfig.mimx91 b/soc/nxp/imx/imx9/imx91/Kconfig.defconfig.mimx91 new file mode 100644 index 000000000000..748117545f0f --- /dev/null +++ b/soc/nxp/imx/imx9/imx91/Kconfig.defconfig.mimx91 @@ -0,0 +1,21 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MIMX9131 + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +config NUM_IRQS + default 300 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 24000000 + +endif diff --git a/soc/nxp/imx/imx9/imx91/Kconfig.soc b/soc/nxp/imx/imx9/imx91/Kconfig.soc new file mode 100644 index 000000000000..a3a063740cd9 --- /dev/null +++ b/soc/nxp/imx/imx9/imx91/Kconfig.soc @@ -0,0 +1,21 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_MIMX9131 + bool + select SOC_SERIES_IMX9 + help + NXP i.MX91 + +config SOC_PART_NUMBER_MIMX9131CVVXJ + bool + +config SOC_PART_NUMBER_MIMX9131DVVXJ + bool + +config SOC_PART_NUMBER + default "MIMX9131CVVXJ" if SOC_PART_NUMBER_MIMX9131CVVXJ + default "MIMX9131DVVXJ" if SOC_PART_NUMBER_MIMX9131DVVXJ + +config SOC + default "mimx9131" if SOC_MIMX9131 diff --git a/soc/nxp/imx/imx9/imx91/mmu_regions.c b/soc/nxp/imx/imx9/imx91/mmu_regions.c new file mode 100644 index 000000000000..62f04672b662 --- /dev/null +++ b/soc/nxp/imx/imx9/imx91/mmu_regions.c @@ -0,0 +1,38 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +static const struct arm_mmu_region mmu_regions[] = { + MMU_REGION_FLAT_ENTRY("GIC", DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0), + DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS), + + MMU_REGION_FLAT_ENTRY("GIC", DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1), + DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS), + + MMU_REGION_FLAT_ENTRY("CCM", DT_REG_ADDR(DT_NODELABEL(ccm)), DT_REG_SIZE(DT_NODELABEL(ccm)), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS), + + MMU_REGION_FLAT_ENTRY("ANA_PLL", DT_REG_ADDR(DT_NODELABEL(ana_pll)), + DT_REG_SIZE(DT_NODELABEL(ana_pll)), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS), + + MMU_REGION_FLAT_ENTRY("IOMUXC", DT_REG_ADDR(DT_NODELABEL(iomuxc)), + DT_REG_SIZE(DT_NODELABEL(iomuxc)), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS), + + MMU_REGION_DT_COMPAT_FOREACH_FLAT_ENTRY(nxp_lpuart, + (MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS)) +}; + +const struct arm_mmu_config mmu_config = { + .num_regions = ARRAY_SIZE(mmu_regions), + .mmu_regions = mmu_regions, +}; diff --git a/soc/nxp/imx/imx9/imx91/pinctrl_soc.h b/soc/nxp/imx/imx9/imx91/pinctrl_soc.h new file mode 100644 index 000000000000..da79bbfab43a --- /dev/null +++ b/soc/nxp/imx/imx9/imx91/pinctrl_soc.h @@ -0,0 +1,79 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_ARM64_NXP_IMX9_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_ARM64_NXP_IMX9_PINCTRL_SOC_H_ + +#include +#include +#include "fsl_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT IOMUXC1_SW_PAD_CTL_PAD_HYS_SHIFT +#define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC1_SW_PAD_CTL_PAD_OD_SHIFT +#define MCUX_IMX_BIAS_PULL_DOWN_SHIFT IOMUXC1_SW_PAD_CTL_PAD_PD_SHIFT +#define MCUX_IMX_BIAS_PULL_UP_SHIFT IOMUXC1_SW_PAD_CTL_PAD_PU_SHIFT +#define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC1_SW_PAD_CTL_PAD_FSEL1_SHIFT +#define MCUX_IMX_DRIVE_STRENGTH_SHIFT IOMUXC1_SW_PAD_CTL_PAD_DSE_SHIFT +#define MCUX_IMX_INPUT_ENABLE_SHIFT 23 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */ +#define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1) + +#define Z_PINCTRL_MCUX_IMX_PINCFG_INIT(node_id) \ + ((DT_PROP(node_id, input_schmitt_enable) << MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT) | \ + (DT_PROP(node_id, drive_open_drain) << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT) | \ + (DT_PROP(node_id, bias_pull_down) << MCUX_IMX_BIAS_PULL_DOWN_SHIFT) | \ + (DT_PROP(node_id, bias_pull_up) << MCUX_IMX_BIAS_PULL_UP_SHIFT) | \ + (DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) | \ + ((~(0xff << DT_ENUM_IDX(node_id, drive_strength))) << MCUX_IMX_DRIVE_STRENGTH_SHIFT) | \ + (DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT)) + +/* This struct must be present. It is used by the mcux gpio driver */ +struct pinctrl_soc_pinmux { + uint32_t mux_register; /*!< IOMUXC SW_PAD_MUX register */ + uint32_t config_register; /*!< IOMUXC SW_PAD_CTL register */ + uint32_t input_register; /*!< IOMUXC SELECT_INPUT DAISY register */ + uint8_t mux_mode: 4; /*!< Mux value for SW_PAD_MUX register */ + uint32_t input_daisy: 4; /*!< Mux value for SELECT_INPUT_DAISY register */ +}; + +struct pinctrl_soc_pin { + struct pinctrl_soc_pinmux pinmux; + uint32_t pin_ctrl_flags; /*!< value to write to IOMUXC_SW_PAD_CTL register */ +}; + +typedef struct pinctrl_soc_pin pinctrl_soc_pin_t; + +/* This definition must be present. It is used by the mcux gpio driver */ +#define MCUX_IMX_PINMUX(node_id) \ + { \ + .mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \ + .config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \ + .input_register = DT_PROP_BY_IDX(node_id, pinmux, 2), \ + .mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1), \ + .input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3), \ + } + +#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \ + MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx)) + +#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \ + { \ + .pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \ + .pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PINCFG_INIT(group_id), \ + }, + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \ + Z_PINCTRL_STATE_PIN_INIT)}; + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SOC_ARM64_NXP_IMX9_PINCTRL_SOC_H_ */ diff --git a/soc/nxp/imx/soc.yml b/soc/nxp/imx/soc.yml index 64371b41c235..e955bfee6a8a 100644 --- a/soc/nxp/imx/soc.yml +++ b/soc/nxp/imx/soc.yml @@ -35,6 +35,7 @@ family: - name: m4 - name: imx9 socs: + - name: mimx9131 - name: mimx9352 cpuclusters: - name: a55 From 51e7a4743f26328989c63c07f5e58fef0cdb042d Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Wed, 1 Jan 2025 02:33:00 +0800 Subject: [PATCH 4/6] drivers: clock: ccm_rev2: add imx91 support Add clock driver support for MIMX9131. Signed-off-by: Hou Zhiqiang --- drivers/clock_control/clock_control_mcux_ccm_rev2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clock_control/clock_control_mcux_ccm_rev2.c b/drivers/clock_control/clock_control_mcux_ccm_rev2.c index 504faa86bad4..dcca3f4eca96 100644 --- a/drivers/clock_control/clock_control_mcux_ccm_rev2.c +++ b/drivers/clock_control/clock_control_mcux_ccm_rev2.c @@ -1,5 +1,5 @@ /* - * Copyright 2021,2024 NXP + * Copyright 2021,2024-2025 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -287,7 +287,7 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev, default: return -EINVAL; } -#ifdef CONFIG_SOC_MIMX9352 +#if defined(CONFIG_SOC_MIMX9352) || defined(CONFIG_SOC_MIMX9131) *rate = CLOCK_GetIpFreq(clock_root); #else *rate = CLOCK_GetRootClockFreq(clock_root); From 529712d004cfb5357d0e0e9ba172015e750794bf Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Wed, 1 Jan 2025 02:33:50 +0800 Subject: [PATCH 5/6] drivers: pinctrl_imx: add imx91 support Add pinctrl driver support for MIMX9131. Signed-off-by: Hou Zhiqiang --- drivers/pinctrl/pinctrl_imx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl_imx.c b/drivers/pinctrl/pinctrl_imx.c index 8d60cea5817b..51a81f134ea7 100644 --- a/drivers/pinctrl/pinctrl_imx.c +++ b/drivers/pinctrl/pinctrl_imx.c @@ -1,5 +1,5 @@ /* - * Copyright 2022, 2024 NXP + * Copyright 2022, 2024-2025 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -33,7 +33,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, } #endif -#ifdef CONFIG_SOC_MIMX9352 +#if defined(CONFIG_SOC_MIMX9352) || defined(CONFIG_SOC_MIMX9131) sys_write32(IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE(mux_mode) | IOMUXC1_SW_MUX_CTL_PAD_SION(MCUX_IMX_INPUT_ENABLE(pin_ctrl_flags)), (mem_addr_t)mux_register); From ebffa1ae3cf016e3624e2e598fe30caac6371aea Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Sun, 12 Jan 2025 23:41:58 +0800 Subject: [PATCH 6/6] boards: nxp: add imx91_evk support The i.MX 91 Evaluation Kit (MCIMX91-EVK board) is a platform designed to display the most commonly used features of the i.MX 91 applications processor. The MCIMX91-EVK board is an entry-level development board with a small and low-cost package. Signed-off-by: Hou Zhiqiang --- boards/nxp/imx91_evk/Kconfig.imx91_evk | 6 + boards/nxp/imx91_evk/board.yml | 6 + boards/nxp/imx91_evk/doc/index.rst | 128 ++++++++++++++++++ boards/nxp/imx91_evk/imx91_evk-pinctrl.dtsi | 29 ++++ boards/nxp/imx91_evk/imx91_evk_mimx9131.dts | 34 +++++ boards/nxp/imx91_evk/imx91_evk_mimx9131.yaml | 17 +++ .../imx91_evk/imx91_evk_mimx9131_defconfig | 30 ++++ 7 files changed, 250 insertions(+) create mode 100644 boards/nxp/imx91_evk/Kconfig.imx91_evk create mode 100644 boards/nxp/imx91_evk/board.yml create mode 100644 boards/nxp/imx91_evk/doc/index.rst create mode 100644 boards/nxp/imx91_evk/imx91_evk-pinctrl.dtsi create mode 100644 boards/nxp/imx91_evk/imx91_evk_mimx9131.dts create mode 100644 boards/nxp/imx91_evk/imx91_evk_mimx9131.yaml create mode 100644 boards/nxp/imx91_evk/imx91_evk_mimx9131_defconfig diff --git a/boards/nxp/imx91_evk/Kconfig.imx91_evk b/boards/nxp/imx91_evk/Kconfig.imx91_evk new file mode 100644 index 000000000000..6bfc897688e8 --- /dev/null +++ b/boards/nxp/imx91_evk/Kconfig.imx91_evk @@ -0,0 +1,6 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IMX91_EVK + select SOC_MIMX9131 + select SOC_PART_NUMBER_MIMX9131CVVXJ diff --git a/boards/nxp/imx91_evk/board.yml b/boards/nxp/imx91_evk/board.yml new file mode 100644 index 000000000000..8912c7df530d --- /dev/null +++ b/boards/nxp/imx91_evk/board.yml @@ -0,0 +1,6 @@ +board: + name: imx91_evk + full_name: i.MX91 EVK + vendor: nxp + socs: + - name: mimx9131 diff --git a/boards/nxp/imx91_evk/doc/index.rst b/boards/nxp/imx91_evk/doc/index.rst new file mode 100644 index 000000000000..aeed42617949 --- /dev/null +++ b/boards/nxp/imx91_evk/doc/index.rst @@ -0,0 +1,128 @@ +.. zephyr:board:: imx91_evk + +Overview +******** + +The i.MX 91 Evaluation Kit (MCIMX91-EVK board) is a platform designed +to display the most commonly used features of the i.MX 91 applications +processor. The MCIMX91-EVK board is an entry-level development board +with a small and low-cost package. The board can be used by developers +to get familiar with the processor before investing a large amount of +resources in more specific designs. + +The i.MX 91 applications processor features an Arm Cortex-A55 core +that can operate at speeds of up to 1.4 GHz. + +- Board features: + + - RAM: 2GB LPDDR4 + - Storage: + + - SanDisk 16GB eMMC5.1 + - microSD Socket + - Wireless: + + - Murata Type-2EL (SDIO+UART+SPI) module. It is based on NXP IW612 SoC, + which supports dual-band (2.4 GHz /5 GHz) 1x1 Wi-Fi 6, Bluetooth 5.2, + and 802.15.4 + - USB: + + - Two USB 2.0 Type C connectors + - Ethernet: + + - ENET: 10/100/1000 Mbit/s RGMII Ethernet connected with external PHY + RTL8211 + - ENET_QoS: 10/100/1000 Mbit/s RGMII Ethernet supporting TSN connected + with external PHY RTL8211 + - PCIe: + + - One M.2/NGFF Key E mini card 75-pin connector + - Connectors: + + - 40-Pin Dual Row Header + - LEDs: + + - 1x Power status LED + - 2x UART LED + - Debug: + + - JTAG 20-pin connector + - MicroUSB for UART debug + + +Supported Features +================== + +The Zephyr ``imx91_evk/mimx9131`` board supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| GIC-v3 | on-chip | interrupt controller | ++-----------+------------+-------------------------------------+ +| ARM TIMER | on-chip | system clock | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 24 MHz. +Cortex-A55 Core runs up to 1.4 GHz. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +CPU's UART1 for A55 core. + +Programming and Debugging +******************************* + +U-Boot "go" command is used to load and kick Zephyr to Cortex-A55 Core. + +Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and +plug the SD card into the board. Power it up and stop the u-boot execution at +prompt. + +Use U-Boot to load and kick zephyr.bin to Cortex-A55 Core: + +.. code-block:: console + + fatload mmc 1:1 0x80000000 zephyr.bin; dcache flush; icache flush; go 0x80000000 + +Use this configuration to run basic Zephyr applications and kernel tests, +for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: imx91_evk/mimx9131 + :goals: build + +This will build an image with the synchronization sample app, boot it and +display the following console output: + +.. code-block:: console + + *** Booting Zephyr OS build v4.0.0-3277-g69f43115c9a8 *** + thread_a: Hello World from cpu 0 on imx91_evk! + thread_b: Hello World from cpu 0 on imx91_evk! + thread_a: Hello World from cpu 0 on imx91_evk! + thread_b: Hello World from cpu 0 on imx91_evk! + +References +========== + +More information can refer to NXP official website: +`NXP website`_. + +.. _NXP website: + https://www.nxp.com/products/i.MX91 diff --git a/boards/nxp/imx91_evk/imx91_evk-pinctrl.dtsi b/boards/nxp/imx91_evk/imx91_evk-pinctrl.dtsi new file mode 100644 index 000000000000..94d9f0f7f91c --- /dev/null +++ b/boards/nxp/imx91_evk/imx91_evk-pinctrl.dtsi @@ -0,0 +1,29 @@ +/* + * Copyright 2025 NXP + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#include + +&pinctrl { + uart1_default: uart1_default { + group0 { + pinmux = <&iomuxc1_uart1_rxd_lpuart_rx_lpuart1_rx>, + <&iomuxc1_uart1_txd_lpuart_tx_lpuart1_tx>; + bias-pull-up; + slew-rate = "slightly_fast"; + drive-strength = "x5"; + }; + }; + + uart2_default: uart2_default { + group0 { + pinmux = <&iomuxc1_uart2_rxd_lpuart_rx_lpuart2_rx>, + <&iomuxc1_uart2_txd_lpuart_tx_lpuart2_tx>; + bias-pull-up; + slew-rate = "slightly_fast"; + drive-strength = "x5"; + }; + }; +}; diff --git a/boards/nxp/imx91_evk/imx91_evk_mimx9131.dts b/boards/nxp/imx91_evk/imx91_evk_mimx9131.dts new file mode 100644 index 000000000000..6b4f464375b0 --- /dev/null +++ b/boards/nxp/imx91_evk/imx91_evk_mimx9131.dts @@ -0,0 +1,34 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx91_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX91 A55"; + compatible = "fsl,mimx91"; + + chosen { + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + /* sram node actually locates at DDR DRAM */ + zephyr,sram = &dram; + }; + + dram: memory@80000000 { + reg = <0x80000000 DT_SIZE_M(1)>; + }; + +}; + +&lpuart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/imx91_evk/imx91_evk_mimx9131.yaml b/boards/nxp/imx91_evk/imx91_evk_mimx9131.yaml new file mode 100644 index 000000000000..4302f9566b4d --- /dev/null +++ b/boards/nxp/imx91_evk/imx91_evk_mimx9131.yaml @@ -0,0 +1,17 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx91_evk/mimx9131 +name: NXP i.MX91 EVK +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +supported: + - uart +vendor: nxp diff --git a/boards/nxp/imx91_evk/imx91_evk_mimx9131_defconfig b/boards/nxp/imx91_evk/imx91_evk_mimx9131_defconfig new file mode 100644 index 000000000000..830456d006d2 --- /dev/null +++ b/boards/nxp/imx91_evk/imx91_evk_mimx9131_defconfig @@ -0,0 +1,30 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y + +# MMU Options +# Increase the value when encounter the assert on the MAX_XLAT_TABLES +CONFIG_MAX_XLAT_TABLES=24 + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_CLOCK_CONTROL=y