diff --git a/boards/renesas/rzg3s_smarc/Kconfig.rzg3s_smarc b/boards/renesas/rzg3s_smarc/Kconfig.rzg3s_smarc new file mode 100644 index 000000000000..3a0abcb410b3 --- /dev/null +++ b/boards/renesas/rzg3s_smarc/Kconfig.rzg3s_smarc @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RZG3S_SMARC + select SOC_R9A08G045S33GBG diff --git a/boards/renesas/rzg3s_smarc/board.cmake b/boards/renesas/rzg3s_smarc/board.cmake new file mode 100644 index 000000000000..1dbf0782ab0d --- /dev/null +++ b/boards/renesas/rzg3s_smarc/board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R9A08G045S33_M33_0" "--speed=15000") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/rzg3s_smarc/board.yml b/boards/renesas/rzg3s_smarc/board.yml new file mode 100644 index 000000000000..97f7d9ba24f3 --- /dev/null +++ b/boards/renesas/rzg3s_smarc/board.yml @@ -0,0 +1,6 @@ +board: + name: rzg3s_smarc + full_name: RZ/G3S SMARC Evaluation Board Kit + vendor: renesas + socs: + - name: r9a08g045s33gbg diff --git a/boards/renesas/rzg3s_smarc/doc/index.rst b/boards/renesas/rzg3s_smarc/doc/index.rst new file mode 100644 index 000000000000..e442a836ee44 --- /dev/null +++ b/boards/renesas/rzg3s_smarc/doc/index.rst @@ -0,0 +1,234 @@ +.. zephyr:board:: rzg3s_smarc + +Overview +******** + +The Renesas RZ/G3S SMARC Evaluation Board Kit (RZ/G3S-EVKIT) consists of a SMARC v2.1 module board and a carrier board. + +* Device: RZ/G3S R9A08G045S33GBG + + * Cortex-A55 Single, Cortex-M33 x 2 + * BGA 359-pin, 14mmSq body, 0.5mm pitch + +* SMARC v2.1 Module Board Functions + + * LPDDR4 SDRAM: 1GB x 1pc + * QSPI flash memory: 128Mb x 1pc + * eMMC memory: 64GB x 1pc + * PMIC power supply RAA215300A2GNP#HA3 implemented + * microSD card x2 + * I3C connector + * JTAG connector + * ADC x8 channels + * Current monitor (USB Micro B) + +* Carrier Board Functions + + * Gigabit Ethernet x2 + * USB2.0 x2ch (OTG x1ch, Host x1ch) + * CAN-FD x2 + * microSD card x1 + * Mono speaker, Stereo headphone, Mic., and Aux.. + * PMOD x2 + * USB-Type C for power input + * PCIe Gen2 4-lane slot (G3S supports only 1-lane) + * M.2 Key E + * M.2 Key B and SIM card + * Coin cell battery holder (3.0V support) + +Hardware +******** + +The Renesas RZ/G3S MPU documentation can be found at `RZ/G3S Group Website`_ + +.. figure:: rzg3s_block_diagram.webp + :width: 600px + :align: center + :alt: RZ/G3S group feature + + RZ/G3S block diagram (Credit: Renesas Electronics Corporation) + +Supported Features +================== + +The ``rzg3s_smarc/r9a08g045s33gbg/cm33`` board target supports the ARM Cortex-M33 System Core without FPU +and the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | arch/arm | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | arch/arm | ++-----------+------------+-------------------------------------+ +| PINCTRL | on-chip | pinctrl | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +RZ/G3S-EVKIT is designed to start different systems on different cores. +It uses Yocto as the build system to build Linux system and boot loaders +to run BL2 TF-A on Cortex-A55 System Core before starting Zephyr. The minimal steps are described below. + + 1. Follow ''2.2 Building Images'' of `SMARC EVK of RZ/G3S Linux Start-up Guide`_ to prepare the build environment. + + 2. Before build, add ``PLAT_M33_BOOT_SUPPORT=1`` to meta-renesas/meta-rzg3s/recipes-bsp/trusted-firmware-a/trusted-firmware-a.bbappend. + + .. code-block:: bash + :emphasize-lines: 6 + + require trusted-firmware-a.inc + COMPATIBLE_MACHINE_rzg3s = "(rzg3s-dev|smarc-rzg3s)" + PLATFORM_rzg3s-dev = "g3s" + EXTRA_FLAGS_rzg3s-dev = "BOARD=dev14_1_lpddr PLAT_SYSTEM_SUSPEND=vbat" + PLATFORM_smarc-rzg3s = "g3s" + EXTRA_FLAGS_smarc-rzg3s = "BOARD=smarc PLAT_SYSTEM_SUSPEND=vbat PLAT_M33_BOOT_SUPPORT=1" + + 3. Start the build: + + .. code-block:: bash + + MACHINE=smarc-rzg3s bitbake core-image-minimal + + The below necessary artifacts will be located in the build/tmp/deploy/images + + +---------------+-----------------------------+ + | Artifacts | File name | + +===============+=============================+ + | Boot loader | bl2_bp_spi-smarc-rzg3s.srec | + | | | + | | fip-smarc-rzg3s.srec | + +---------------+-----------------------------+ + | Flash Writer | FlashWriter-smarc-rzg3s.mot | + +---------------+-----------------------------+ + + 4. Follow ''4.2 Startup Procedure'' of `SMARC EVK of RZ/G3S Linux Start-up Guide`_ for power supply and board setting + at SCIF download (SW_MODE[1:4] = OFF, ON, OFF, ON) and Cortex-A55 cold boot (SW_CONFIG[1:6] = OFF, OFF, ON, OFF, OFF, OFF) + + 5. Follow ''4.3 Download Flash Writer to RAM'' of `SMARC EVK of RZ/G3S Linux Start-up Guide`_ to download Flash Writer to RAM + + 6. Follow ''4.4 Write the Bootloader'' of `SMARC EVK of RZ/G3S Linux Start-up Guide`_ to write the boot loader + to the target board by using Flash Writer. + +Applications for the ``rzg3s_smarc`` board can be built in the usual way as +documented in :ref:`build_an_application`. + +Console +======= + +The UART port for Cortex-M33 System Core can be accessed by connecting `Pmod USBUART `_ +to the upper side of ``PMOD1_3A``. + +Debugging +========= + +It is possible to load and execute a Zephyr application binary on +this board on the Cortex-M33 System Core from +the internal SRAM, using ``JLink`` debugger (:ref:`jlink-debug-host-tools`). + +.. note:: + + Currently it's required Renesas BL2 TF-A to be started on Cortex-A55 System Core + before starting Zephyr as it configures clocks and the Cortex-M33 System Core before starting it. + +Here is an example for building and debugging with the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rzg3s_smarc/r9a08g045s33gbg/cm33 + :goals: build debug + +Flashing +======== + +Zephyr application can be flashed to QSPI storage and then loaded by +Renesas BL2 TF-A running on the Cortex-A55 System Core and starting binary on the Cortex-M33 System Core. + +The Zephyr application binary has to be converted to Motorolla S-record `SREC`_ format +which is generated automatically in Zephyr application build directory with the extension ``s19``. + +.. _SREC: https://en.wikipedia.org/wiki/SREC_(file_format) + +.. _Flashing on QSPI: + +Flashing on QSPI using Flash Writer +--------------------------------------- + +Zephyr binary has to be converted to **srec** format. + +* Download and start **Flash Writer** as described in ''4.3 Download Flash Writer to RAM'' of `SMARC EVK of RZ/G3S Linux Start-up Guide`_ +* Use **XLS2** command to flash Zephyr binary +* Input when asked: + +.. code-block:: console + + ===== Please Input Program Top Address ============ + Please Input : H'23000 + ===== Please Input Qspi Save Address === + Please Input : H'200000 + +* Then send Zephyr **s19** file from terminal (use ''ascii'' mode) +* Reboot the board in the **QSPI Boot Mode** + +.. code-block:: console + + -- Load Program to SRAM --------------- + + Flash writer for RZ/G3S Series V0.60 Jan.26,2023 + Product Code : RZ/G3S + >XLS2 + ===== Qspi writing of RZ/G2 Board Command ============= + Load Program to Spiflash + Writes to any of SPI address. + Program size & Qspi Save Address + ===== Please Input Program Top Address ============ + Please Input : H'23000 + + ===== Please Input Qspi Save Address === + Please Input : H'200000 + please send ! ('.' & CR stop load) + I Flash memory... + Erase Completed + Write to SPI Flash memory. + ======= Qspi Save Information ================= + SpiFlashMemory Stat Address : H'00200000 + SpiFlashMemory End Address : H'002098E6 + =========================================================== + +Flashing on QSPI using west +--------------------------- + +Before using ``flash`` command, the board must be set to Cortex-M33 cold boot (SW_CONFIG[1:6] = OFF, OFF, ON, OFF, OFF, ON). +After flashing, it must be set back to Cortex-A55 cold boot to run. + +The minimal version of SEGGER JLink SW which can perform flashing of QSPI memory is v7.96. + +**Note:** It's verified that we can perform flashing successfully with SEGGER JLink SW v7.98g so please use this or later +version. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rzg3s_smarc/r9a08g045s33gbg/cm33 + :goals: build flash + :compact: + +References +********** + +.. target-notes:: + +.. _RZ/G3S Group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzg3s-general-purpose-microprocessors-single-core-arm-cortex-a55-11-ghz-cpu-and-dual-core-cortex-m33-250 + +.. _RZG3S-EVKIT Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzg3s-evkit-evaluation-board-kit-rzg3s-mpu + +.. _SMARC EVK of RZ/G3S Linux Start-up Guide: + https://www.renesas.com/us/en/document/gde/smarc-evk-rzg3s-linux-start-guide-rev104 diff --git a/boards/renesas/rzg3s_smarc/doc/rzg3s_block_diagram.webp b/boards/renesas/rzg3s_smarc/doc/rzg3s_block_diagram.webp new file mode 100644 index 000000000000..ae3022760bc4 Binary files /dev/null and b/boards/renesas/rzg3s_smarc/doc/rzg3s_block_diagram.webp differ diff --git a/boards/renesas/rzg3s_smarc/doc/rzg3s_smarc.webp b/boards/renesas/rzg3s_smarc/doc/rzg3s_smarc.webp new file mode 100644 index 000000000000..1d81bb7a6155 Binary files /dev/null and b/boards/renesas/rzg3s_smarc/doc/rzg3s_smarc.webp differ diff --git a/boards/renesas/rzg3s_smarc/rzg3s_smarc-pinctrl.dtsi b/boards/renesas/rzg3s_smarc/rzg3s_smarc-pinctrl.dtsi new file mode 100644 index 000000000000..aa8ae25d0579 --- /dev/null +++ b/boards/renesas/rzg3s_smarc/rzg3s_smarc-pinctrl.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2024 EPAM Systems + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +&pinctrl { + /omit-if-no-ref/ scif0_pins: scif0 { + scif0-pinmux { + pinmux = , /* TXD */ + ; /* RXD */ + }; + }; + + /omit-if-no-ref/ scif1_pins: scif1 { + scif1-pinmux { + pinmux = , /* TXD */ + ; /* RXD */ + }; + }; + + /omit-if-no-ref/ scif3_pins: scif3 { + scif3-pinmux { + pinmux = , /* TXD */ + ; /* RXD */ + }; + }; + + /omit-if-no-ref/ scif5_pins: scif5 { + scif5-pinmux { + pinmux = , /* RXD */ + ; /* TXD */ + }; + }; +}; diff --git a/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.dts b/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.dts new file mode 100644 index 000000000000..81210407ae4f --- /dev/null +++ b/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.dts @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2024 EPAM Systems + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rzg3s_smarc-pinctrl.dtsi" + +/ { + model = "Renesas RZ/G3S SMARC"; + compatible = "renesas,rzg3s-smarc"; + + chosen { + zephyr,sram = &sram_mcpu0; + zephyr,flash = &spi_flash; + zephyr,console = &scif1; + zephyr,shell-uart = &scif1; + }; + + aliases { + sw0 = &sw_1; + sw1 = &sw_2; + sw2 = &sw_3; + }; + + buttons { + compatible = "gpio-keys"; + + sw_1: button_1 { + gpios = <&gpio18 0 GPIO_ACTIVE_LOW>; + label = "SW1"; + zephyr,code = ; + }; + + sw_2: button_2 { + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + label = "SW2"; + zephyr,code = ; + }; + + sw_3: button_3 { + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + label = "SW3"; + zephyr,code = ; + }; + }; + + ddr: memory@60000000 { + compatible ="zephyr,memory-region", "mmio-sram"; + reg = <0x60000000 DT_SIZE_M(16)>; + zephyr,memory-region = "DDR"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + }; + + sram_mcpu0: memory@23000 { + compatible = "mmio-sram"; + reg = <0x23000 DT_SIZE_K(243)>; + }; + + /* + * This node is defined to enable west flash support. + * The base addr and size depends on ATF-F configuration, which is running on Cortex-A55 and + * loading Zephyr app from xSPI flash. + */ + spi_flash: memory@80200000 { + compatible = "mmio-sram"; + reg = <0x80200000 DT_SIZE_K(256)>; + }; + +}; + +&scif1 { + current-speed = <115200>; + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio0{ + status = "okay"; +}; + +&gpio18{ + status = "okay"; +}; diff --git a/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.yaml b/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.yaml new file mode 100644 index 000000000000..06285a945dec --- /dev/null +++ b/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.yaml @@ -0,0 +1,10 @@ +identifier: rzg3s_smarc/r9a08g045s33gbg/cm33 +name: Cortex-M33 for Renesas RZ/G3S SMARC +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - uart + - gpio diff --git a/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33_defconfig b/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33_defconfig new file mode 100644 index 000000000000..b06a719875e7 --- /dev/null +++ b/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33_defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 EPAM Systems +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XIP=n + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=ys +CONFIG_UART_CONSOLE=y diff --git a/drivers/gpio/CMakeLists.txt b/drivers/gpio/CMakeLists.txt index 03c5aa211bae..2ba21ce57f7c 100644 --- a/drivers/gpio/CMakeLists.txt +++ b/drivers/gpio/CMakeLists.txt @@ -75,6 +75,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_PSOC6 gpio_psoc6.c) zephyr_library_sources_ifdef(CONFIG_GPIO_RA_IOPORT gpio_renesas_ra_ioport.c) zephyr_library_sources_ifdef(CONFIG_GPIO_RCAR gpio_rcar.c) zephyr_library_sources_ifdef(CONFIG_GPIO_RENESAS_RA gpio_renesas_ra.c) +zephyr_library_sources_ifdef(CONFIG_GPIO_RENESAS_RZ gpio_renesas_rz.c) zephyr_library_sources_ifdef(CONFIG_GPIO_RP1 gpio_rp1.c) zephyr_library_sources_ifdef(CONFIG_GPIO_RPI_PICO gpio_rpi_pico.c) zephyr_library_sources_ifdef(CONFIG_GPIO_RT1718S gpio_rt1718s.c) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 96d69068cd55..f067a0725e4f 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -162,6 +162,7 @@ source "drivers/gpio/Kconfig.psoc6" source "drivers/gpio/Kconfig.rcar" source "drivers/gpio/Kconfig.renesas_ra" source "drivers/gpio/Kconfig.renesas_ra_ioport" +source "drivers/gpio/Kconfig.renesas_rz" source "drivers/gpio/Kconfig.rp1" source "drivers/gpio/Kconfig.rpi_pico" source "drivers/gpio/Kconfig.rt1718s" diff --git a/drivers/gpio/Kconfig.renesas_rz b/drivers/gpio/Kconfig.renesas_rz new file mode 100644 index 000000000000..ae2e08c85de6 --- /dev/null +++ b/drivers/gpio/Kconfig.renesas_rz @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config GPIO_RENESAS_RZ + bool "Renesas RZ series gpio driver" + default y + depends on DT_HAS_RENESAS_RZ_GPIO_ENABLED + select USE_RZ_FSP_IOPORT + help + Enable Renesas RZ series gpio driver. diff --git a/drivers/gpio/gpio_renesas_rz.c b/drivers/gpio/gpio_renesas_rz.c new file mode 100644 index 000000000000..7728b59cfeb9 --- /dev/null +++ b/drivers/gpio/gpio_renesas_rz.c @@ -0,0 +1,502 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT renesas_rz_gpio + +#include +#include +#include +#include +#include "r_ioport.h" +#include +#include +#include "gpio_renesas_rz.h" +#include +LOG_MODULE_REGISTER(rz_gpio, CONFIG_GPIO_LOG_LEVEL); + +#define LOG_DEV_ERR(dev, format, ...) LOG_ERR("%s:" #format, (dev)->name, ##__VA_ARGS__) +#define LOG_DEV_DBG(dev, format, ...) LOG_DBG("%s:" #format, (dev)->name, ##__VA_ARGS__) + +struct gpio_rz_config { + struct gpio_driver_config common; + uint8_t ngpios; + uint8_t port_num; + bsp_io_port_t fsp_port; + const ioport_cfg_t *fsp_cfg; + const ioport_api_t *fsp_api; + const struct device *int_dev; + uint8_t tint_num[GPIO_RZ_MAX_TINT_NUM]; +}; + +struct gpio_rz_data { + struct gpio_driver_data common; + sys_slist_t cb; + ioport_instance_ctrl_t *fsp_ctrl; + struct k_spinlock lock; +}; + +struct gpio_rz_tint_isr_data { + const struct device *gpio_dev; + gpio_pin_t pin; +}; + +struct gpio_rz_tint_data { + struct gpio_rz_tint_isr_data tint_data[GPIO_RZ_MAX_TINT_NUM]; + uint32_t irq_set_edge; +}; + +struct gpio_rz_tint_config { + void (*gpio_int_init)(void); +}; + +static int gpio_rz_pin_config_get_raw(bsp_io_port_pin_t port_pin, uint32_t *flags); + +#ifdef CONFIG_GPIO_GET_CONFIG +static int gpio_rz_pin_get_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t *flags) +{ + const struct gpio_rz_config *config = dev->config; + bsp_io_port_pin_t port_pin = config->fsp_port | pin; + + gpio_rz_pin_config_get_raw(port_pin, flags); + return 0; +} +#endif + +/* Get previous pin's configuration, used by pin_configure/pin_interrupt_configure api */ +static int gpio_rz_pin_config_get_raw(bsp_io_port_pin_t port_pin, uint32_t *flags) +{ + bsp_io_port_t port = (port_pin >> 8U) & 0xFF; + gpio_pin_t pin = port_pin & 0xFF; + volatile uint8_t *p_p = GPIO_RZ_IOPORT_P_REG_BASE_GET; + volatile uint16_t *p_pm = GPIO_RZ_IOPORT_PM_REG_BASE_GET; + + uint8_t adr_offset; + uint8_t p_value; + uint16_t pm_value; + + adr_offset = (uint8_t)GPIO_RZ_REG_OFFSET(port, pin); + + p_p = &p_p[adr_offset]; + p_pm = &p_pm[adr_offset]; + + p_value = GPIO_RZ_P_VALUE_GET(*p_p, pin); + pm_value = GPIO_RZ_PM_VALUE_GET(*p_pm, pin); + + if (p_value) { + *flags |= GPIO_OUTPUT_INIT_HIGH; + } else { + *flags |= GPIO_OUTPUT_INIT_LOW; + } + + *flags |= ((pm_value << 16)); + return 0; +} + +static int gpio_rz_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) +{ + const struct gpio_rz_config *config = dev->config; + struct gpio_rz_data *data = dev->data; + bsp_io_port_pin_t port_pin = config->fsp_port | pin; + uint32_t ioport_config_data = 0; + gpio_flags_t pre_flags; + fsp_err_t err; + + gpio_rz_pin_config_get_raw(port_pin, &pre_flags); + + if (!flags) { + /* Disconnect mode */ + ioport_config_data = 0; + } else if (!(flags & GPIO_OPEN_DRAIN)) { + /* PM register */ + ioport_config_data &= GPIO_RZ_PIN_CONFIGURE_INPUT_OUTPUT_RESET; + if (flags & GPIO_INPUT) { + if (flags & GPIO_OUTPUT) { + ioport_config_data |= IOPORT_CFG_PORT_DIRECTION_OUTPUT_INPUT; + } else { + ioport_config_data |= IOPORT_CFG_PORT_DIRECTION_INPUT; + } + } else if (flags & GPIO_OUTPUT) { + ioport_config_data &= GPIO_RZ_PIN_CONFIGURE_INPUT_OUTPUT_RESET; + ioport_config_data |= IOPORT_CFG_PORT_DIRECTION_OUTPUT; + } + /* P register */ + if (!(flags & (GPIO_OUTPUT_INIT_HIGH | GPIO_OUTPUT_INIT_LOW))) { + flags |= pre_flags & (GPIO_OUTPUT_INIT_HIGH | GPIO_OUTPUT_INIT_LOW); + } + + if (flags & GPIO_OUTPUT_INIT_HIGH) { + ioport_config_data |= IOPORT_CFG_PORT_OUTPUT_HIGH; + } else if (flags & GPIO_OUTPUT_INIT_LOW) { + ioport_config_data &= ~(IOPORT_CFG_PORT_OUTPUT_HIGH); + } + /* PUPD register */ + if (flags & GPIO_PULL_UP) { + ioport_config_data |= IOPORT_CFG_PULLUP_ENABLE; + } else if (flags & GPIO_PULL_DOWN) { + ioport_config_data |= IOPORT_CFG_PULLUP_ENABLE; + } + + /* ISEL register */ + if (flags & GPIO_INT_ENABLE) { + ioport_config_data |= GPIO_RZ_PIN_CONFIGURE_INT_ENABLE; + } else if (flags & GPIO_INT_DISABLE) { + ioport_config_data &= GPIO_RZ_PIN_CONFIGURE_INT_DISABLE; + } + + /* Drive Ability register */ + ioport_config_data |= GPIO_RZ_PIN_CONFIGURE_GET_DRIVE_ABILITY(flags); + + /* Filter register, see in renesas-rz-gpio-ioport.h */ + ioport_config_data |= GPIO_RZ_PIN_CONFIGURE_GET_FILTER(flags); + } else { + return -ENOTSUP; + } + + err = config->fsp_api->pinCfg(data->fsp_ctrl, port_pin, ioport_config_data); + if (err != FSP_SUCCESS) { + return -EIO; + } + return 0; +} + +static int gpio_rz_port_get_raw(const struct device *dev, gpio_port_value_t *value) +{ + const struct gpio_rz_config *config = dev->config; + struct gpio_rz_data *data = dev->data; + fsp_err_t err; + ioport_size_t port_value; + + err = config->fsp_api->portRead(data->fsp_ctrl, config->fsp_port, &port_value); + if (err != FSP_SUCCESS) { + return -EIO; + } + *value = (gpio_port_value_t)port_value; + return 0; +} + +static int gpio_rz_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, + gpio_port_value_t value) +{ + const struct gpio_rz_config *config = dev->config; + struct gpio_rz_data *data = dev->data; + ioport_size_t port_mask = (ioport_size_t)mask; + ioport_size_t port_value = (ioport_size_t)value; + fsp_err_t err; + + err = config->fsp_api->portWrite(data->fsp_ctrl, config->fsp_port, port_value, port_mask); + if (err != FSP_SUCCESS) { + return -EIO; + } + return 0; +} + +static int gpio_rz_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins) +{ + const struct gpio_rz_config *config = dev->config; + struct gpio_rz_data *data = dev->data; + ioport_size_t mask = (ioport_size_t)pins; + ioport_size_t value = (ioport_size_t)pins; + fsp_err_t err; + + err = config->fsp_api->portWrite(data->fsp_ctrl, config->fsp_port, value, mask); + if (err != FSP_SUCCESS) { + return -EIO; + } + return 0; +} + +static int gpio_rz_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins) +{ + const struct gpio_rz_config *config = dev->config; + struct gpio_rz_data *data = dev->data; + ioport_size_t mask = (ioport_size_t)pins; + ioport_size_t value = 0x00; + fsp_err_t err; + + err = config->fsp_api->portWrite(data->fsp_ctrl, config->fsp_port, value, mask); + if (err != FSP_SUCCESS) { + return -EIO; + } + return 0; +} + +static int gpio_rz_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins) +{ + const struct gpio_rz_config *config = dev->config; + struct gpio_rz_data *data = dev->data; + bsp_io_port_pin_t port_pin; + gpio_flags_t pre_flags; + ioport_size_t value = 0; + fsp_err_t err; + + for (uint8_t idx = 0; idx < config->ngpios; idx++) { + if (pins & (1U << idx)) { + port_pin = config->fsp_port | idx; + gpio_rz_pin_config_get_raw(port_pin, &pre_flags); + if (pre_flags & GPIO_OUTPUT_INIT_HIGH) { + value &= (1U << idx); + } else if (pre_flags & GPIO_OUTPUT_INIT_LOW) { + value |= (1U << idx); + } + } + } + err = config->fsp_api->portWrite(data->fsp_ctrl, config->fsp_port, value, + (ioport_size_t)pins); + if (err != FSP_SUCCESS) { + return -EIO; + } + return 0; +} + +#define GPIO_RZ_HAS_INTERRUPT DT_HAS_COMPAT_STATUS_OKAY(renesas_rz_gpio_int) + +#if GPIO_RZ_HAS_INTERRUPT +static int gpio_rz_int_disable(const struct device *dev, uint8_t tint_num) +{ + struct gpio_rz_tint_data *data = dev->data; + volatile uint32_t *tssr = &R_INTC_IM33->TSSR0; + volatile uint32_t *titsr = &R_INTC_IM33->TITSR0; + volatile uint32_t *tscr = &R_INTC_IM33->TSCR; + + /* Get register offset base on interrupt number. */ + tssr = &tssr[tint_num / 4]; + titsr = &titsr[tint_num / 16]; + + irq_disable(GPIO_RZ_TINT_IRQ_GET(tint_num)); + /* Disable interrupt and clear interrupt source. */ + *tssr &= ~(0xFF << GPIO_RZ_TSSR_OFFSET(tint_num)); + /* Reset interrupt dectect type to default. */ + *titsr &= ~(0x3 << GPIO_RZ_TITSR_OFFSET(tint_num)); + + /* Clear interrupt detection status. */ + if (data->irq_set_edge & BIT(tint_num)) { + *tscr &= ~BIT(tint_num); + data->irq_set_edge &= ~BIT(tint_num); + } + data->tint_data[tint_num].gpio_dev = NULL; + data->tint_data[tint_num].pin = UINT8_MAX; + + return 0; +} + +static int gpio_rz_int_enable(const struct device *int_dev, const struct device *gpio_dev, + uint8_t tint_num, uint8_t irq_type, gpio_pin_t pin) +{ + struct gpio_rz_tint_data *int_data = int_dev->data; + const struct gpio_rz_config *gpio_config = gpio_dev->config; + volatile uint32_t *tssr = &R_INTC_IM33->TSSR0; + volatile uint32_t *titsr = &R_INTC_IM33->TITSR0; + + tssr = &tssr[tint_num / 4]; + titsr = &titsr[tint_num / 16]; + /* Select interrupt detect type. */ + *titsr |= (irq_type << GPIO_RZ_TITSR_OFFSET(tint_num)); + /* Select interrupt source base on port and pin number.*/ + *tssr |= (GPIO_RZ_TSSR_VAL(gpio_config->port_num, pin)) << GPIO_RZ_TSSR_OFFSET(tint_num); + + if (irq_type == GPIO_RZ_TINT_EDGE_RISING || irq_type == GPIO_RZ_TINT_EDGE_FALLING) { + int_data->irq_set_edge |= BIT(tint_num); + /* Clear interrupt status. */ + R_INTC_IM33->TSCR &= ~BIT(tint_num); + } + int_data->tint_data[tint_num].gpio_dev = gpio_dev; + int_data->tint_data[tint_num].pin = pin; + irq_enable(GPIO_RZ_TINT_IRQ_GET(tint_num)); + + return 0; +} + +static int gpio_rz_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin, + enum gpio_int_mode mode, enum gpio_int_trig trig) +{ + const struct gpio_rz_config *config = dev->config; + struct gpio_rz_data *data = dev->data; + bsp_io_port_pin_t port_pin = config->fsp_port | pin; + uint8_t tint_num = config->tint_num[pin]; + uint8_t irq_type = 0; + gpio_flags_t pre_flags = 0; + k_spinlock_key_t key; + + if (tint_num >= GPIO_RZ_MAX_TINT_NUM) { + LOG_DEV_ERR(dev, "Invalid TINT interrupt:%d >= %d", tint_num, GPIO_RZ_MAX_TINT_NUM); + } + + if (pin > config->ngpios) { + return -EINVAL; + } + + if (trig == GPIO_INT_TRIG_BOTH) { + return -ENOTSUP; + } + + key = k_spin_lock(&data->lock); + + if (mode == GPIO_INT_MODE_DISABLED) { + gpio_rz_pin_config_get_raw(port_pin, &pre_flags); + pre_flags |= GPIO_INT_DISABLE; + gpio_rz_pin_configure(dev, pin, pre_flags); + gpio_rz_int_disable(config->int_dev, tint_num); + goto exit_unlock; + } + + if (mode == GPIO_INT_MODE_EDGE) { + irq_type = GPIO_RZ_TINT_EDGE_RISING; + if (trig == GPIO_INT_TRIG_LOW) { + irq_type = GPIO_RZ_TINT_EDGE_FALLING; + } + } else { + irq_type = GPIO_RZ_TINT_LEVEL_HIGH; + if (trig == GPIO_INT_TRIG_LOW) { + irq_type = GPIO_RZ_TINT_LEVEL_LOW; + } + } + + /* Set register ISEL */ + gpio_rz_pin_config_get_raw(port_pin, &pre_flags); + pre_flags |= GPIO_INT_ENABLE; + gpio_rz_pin_configure(dev, pin, pre_flags); + gpio_rz_int_enable(config->int_dev, dev, tint_num, irq_type, pin); + +exit_unlock: + k_spin_unlock(&data->lock, key); + return 0; +} + +static int gpio_rz_manage_callback(const struct device *dev, struct gpio_callback *callback, + bool set) +{ + struct gpio_rz_data *data = dev->data; + + return gpio_manage_callback(&data->cb, callback, set); +} + +static void gpio_rz_isr(const struct device *dev, uint8_t pin) +{ + struct gpio_rz_data *data = dev->data; + + gpio_fire_callbacks(&data->cb, dev, BIT(pin)); +} + +static void gpio_rz_tint_isr(uint16_t irq, const struct device *dev) +{ + struct gpio_rz_tint_data *data = dev->data; + volatile uint32_t *tscr = &R_INTC_IM33->TSCR; + uint8_t tint_num; + + tint_num = irq - GPIO_RZ_TINT_IRQ_OFFSET; + + if (!(*tscr & BIT(tint_num))) { + LOG_DEV_DBG(dev, "tint:%u spurious irq, status 0", tint_num); + return; + } + + if (data->irq_set_edge & BIT(tint_num)) { + *tscr &= ~BIT(tint_num); + } + + gpio_rz_isr(data->tint_data[tint_num].gpio_dev, data->tint_data[tint_num].pin); +} + +static int gpio_rz_int_init(const struct device *dev) +{ + const struct gpio_rz_tint_config *config = dev->config; + + config->gpio_int_init(); + return 0; +} +#endif + +static const struct gpio_driver_api gpio_rz_driver_api = { + .pin_configure = gpio_rz_pin_configure, +#ifdef CONFIG_GPIO_GET_CONFIG + .pin_get_config = gpio_rz_pin_get_config, +#endif + .port_get_raw = gpio_rz_port_get_raw, + .port_set_masked_raw = gpio_rz_port_set_masked_raw, + .port_set_bits_raw = gpio_rz_port_set_bits_raw, + .port_clear_bits_raw = gpio_rz_port_clear_bits_raw, + .port_toggle_bits = gpio_rz_port_toggle_bits, +#if GPIO_RZ_HAS_INTERRUPT + .pin_interrupt_configure = gpio_rz_pin_interrupt_configure, + .manage_callback = gpio_rz_manage_callback, +#endif +}; + +/*Initialize GPIO interrupt device*/ +#define GPIO_RZ_TINT_ISR_DECLARE(irq_num, node_id) \ + static void rz_gpio_isr_##irq_num(void *param) \ + { \ + gpio_rz_tint_isr(DT_IRQ_BY_IDX(node_id, irq_num, irq), param); \ + } + +#define GPIO_RZ_TINT_ISR_INIT(node_id, irq_num) LISTIFY(irq_num, \ + GPIO_RZ_TINT_ISR_DECLARE, (), node_id) + +#define GPIO_RZ_TINT_CONNECT(irq_num, node_id) \ + IRQ_CONNECT(DT_IRQ_BY_IDX(node_id, irq_num, irq), \ + DT_IRQ_BY_IDX(node_id, irq_num, priority), rz_gpio_isr_##irq_num, \ + DEVICE_DT_GET(node_id), 0); + +#define GPIO_RZ_TINT_CONNECT_FUNC(node_id) \ + static void rz_gpio_tint_connect_func##node_id(void) \ + { \ + LISTIFY(DT_NUM_IRQS(node_id), \ + GPIO_RZ_TINT_CONNECT, (;), \ + node_id) \ + } +/* Initialize GPIO device*/ +#define GPIO_RZ_INT_INIT(node_id) \ + GPIO_RZ_TINT_ISR_INIT(node_id, DT_NUM_IRQS(node_id)) \ + GPIO_RZ_TINT_CONNECT_FUNC(node_id) \ + static const struct gpio_rz_tint_config rz_gpio_tint_cfg_##node_id = { \ + .gpio_int_init = rz_gpio_tint_connect_func##node_id, \ + }; \ + static struct gpio_rz_tint_data rz_gpio_tint_data_##node_id = {}; \ + DEVICE_DT_DEFINE(node_id, gpio_rz_int_init, NULL, &rz_gpio_tint_data_##node_id, \ + &rz_gpio_tint_cfg_##node_id, POST_KERNEL, \ + UTIL_DEC(CONFIG_GPIO_INIT_PRIORITY), NULL); + +DT_FOREACH_STATUS_OKAY(renesas_rz_gpio_int, GPIO_RZ_INT_INIT) + +#define VALUE_2X(i, _) UTIL_X2(i) +#define PIN_IRQ_GET(idx, inst) \ + COND_CODE_1(DT_INST_PROP_HAS_IDX(inst, irqs, idx), \ + ([DT_INST_PROP_BY_IDX(inst, irqs, idx)] = \ + DT_INST_PROP_BY_IDX(inst, irqs, UTIL_INC(idx)),), \ + ()) + +#define PIN_IRQS_GET(inst) \ + FOR_EACH_FIXED_ARG(PIN_IRQ_GET, (), inst, \ + LISTIFY(DT_INST_PROP_LEN_OR(inst, irqs, 0), VALUE_2X, (,))) + +#define RZG_GPIO_PORT_INIT(inst) \ + static ioport_cfg_t g_ioport_##inst##_cfg = { \ + .number_of_pins = 0, \ + .p_pin_cfg_data = NULL, \ + .p_extend = NULL, \ + }; \ + static const struct gpio_rz_config gpio_rz_##inst##_config = { \ + .common = \ + { \ + .port_pin_mask = \ + (gpio_port_pins_t)GPIO_PORT_PIN_MASK_FROM_DT_INST(inst), \ + }, \ + .fsp_port = (uint32_t)DT_INST_REG_ADDR(inst), \ + .port_num = (uint8_t)DT_NODE_CHILD_IDX(DT_DRV_INST(inst)), \ + .ngpios = (uint8_t)DT_INST_PROP(inst, ngpios), \ + .fsp_cfg = &g_ioport_##inst##_cfg, \ + .fsp_api = &g_ioport_on_ioport, \ + .int_dev = DEVICE_DT_GET_OR_NULL(DT_INST(0, renesas_rz_gpio_int)), \ + .tint_num = {PIN_IRQS_GET(inst)}, \ + }; \ + static ioport_instance_ctrl_t g_ioport_##inst##_ctrl; \ + static struct gpio_rz_data gpio_rz_##inst##_data = { \ + .fsp_ctrl = &g_ioport_##inst##_ctrl, \ + }; \ + DEVICE_DT_INST_DEFINE(inst, NULL, NULL, &gpio_rz_##inst##_data, &gpio_rz_##inst##_config, \ + POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY, &gpio_rz_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(RZG_GPIO_PORT_INIT) diff --git a/drivers/gpio/gpio_renesas_rz.h b/drivers/gpio/gpio_renesas_rz.h new file mode 100644 index 000000000000..6980450f40c9 --- /dev/null +++ b/drivers/gpio/gpio_renesas_rz.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_GPIO_RENESAS_RZ_H_ +#define ZEPHYR_DRIVERS_GPIO_RENESAS_RZ_H_ + +#include +#include "r_ioport.h" + +#define GPIO_RZ_IOPORT_P_REG_BASE_GET (&R_GPIO->P_20) +#define GPIO_RZ_IOPORT_PM_REG_BASE_GET (&R_GPIO->PM_20) + +#define GPIO_RZ_REG_OFFSET(port, pin) (port + (pin / 4)) + +#define GPIO_RZ_P_VALUE_GET(value, pin) ((value >> pin) & 1U) +#define GPIO_RZ_PM_VALUE_GET(value, pin) ((value >> (pin * 2)) & 3U) + +#define GPIO_RZ_MAX_PORT_NUM 19 +#define GPIO_RZ_MAX_TINT_NUM 32 + +#define GPIO_RZ_TINT_IRQ_OFFSET 429 +#define GPIO_RZ_TINT_IRQ_GET(tint_num) (tint_num + GPIO_RZ_TINT_IRQ_OFFSET) + +#define GPIO_RZ_TINT_EDGE_RISING 0x0 +#define GPIO_RZ_TINT_EDGE_FALLING 0x1 +#define GPIO_RZ_TINT_LEVEL_HIGH 0x2 +#define GPIO_RZ_TINT_LEVEL_LOW 0x3 + +#define GPIO_RZ_TSSR_VAL(port, pin) (0x80 | (gpio_rz_int[port] + pin)) +#define GPIO_RZ_TSSR_OFFSET(irq) ((irq % 4) * 8) +#define GPIO_RZ_TITSR_OFFSET(irq) ((irq % 16) * 2) + +#define GPIO_RZ_PIN_CONFIGURE_GET_FILTER(flag) (((flags >> RZG3S_GPIO_FILTER_SHIFT) & 0x1F) << 19U) +#define GPIO_RZ_PIN_CONFIGURE_GET_DRIVE_ABILITY(flag) \ + (((flag >> RZG3S_GPIO_IOLH_SHIFT) & 0x3) << 10U) + +#define GPIO_RZ_PIN_CONFIGURE_INT_ENABLE IOPORT_CFG_TINT_ENABLE +#define GPIO_RZ_PIN_CONFIGURE_INT_DISABLE (~(IOPORT_CFG_TINT_ENABLE)) +#define GPIO_RZ_PIN_CONFIGURE_INPUT_OUTPUT_RESET (~(0x3 << 2)) + +static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 4, 9, 13, 17, 23, 28, 33, 38, 43, + 47, 52, 56, 58, 63, 66, 70, 72, 76}; +#endif /* ZEPHYR_DRIVERS_GPIO_RENESAS_RZ_H_ */ diff --git a/drivers/pinctrl/renesas/CMakeLists.txt b/drivers/pinctrl/renesas/CMakeLists.txt index 80e4c95ec14e..4d4205291789 100644 --- a/drivers/pinctrl/renesas/CMakeLists.txt +++ b/drivers/pinctrl/renesas/CMakeLists.txt @@ -5,5 +5,6 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RA_PFS ra/pinctrl_ra.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_RZT2M rz/pinctrl_rzt2m.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_SMARTBOND smartbond/pinctrl_smartbond.c) +zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RZ rz/pinctrl_renesas_rz.c) add_subdirectory_ifdef(CONFIG_PINCTRL_RCAR_PFC rcar) diff --git a/drivers/pinctrl/renesas/rz/Kconfig b/drivers/pinctrl/renesas/rz/Kconfig index 236afdcf55ec..745496b8f170 100644 --- a/drivers/pinctrl/renesas/rz/Kconfig +++ b/drivers/pinctrl/renesas/rz/Kconfig @@ -1,4 +1,5 @@ # Copyright (c) 2023 Antmicro +# Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 config PINCTRL_RZT2M @@ -7,3 +8,11 @@ config PINCTRL_RZT2M depends on DT_HAS_RENESAS_RZT2M_PINCTRL_ENABLED help Renesas RZ/T2M pinctrl driver + +config PINCTRL_RENESAS_RZ + bool "Renesas RZ pin controller driver" + default y + depends on DT_HAS_RENESAS_RZG_PINCTRL_ENABLED + select USE_RZ_FSP_IOPORT + help + Enable Renesas RZ pinctrl driver. diff --git a/drivers/pinctrl/renesas/rz/pinctrl_renesas_rz.c b/drivers/pinctrl/renesas/rz/pinctrl_renesas_rz.c new file mode 100644 index 000000000000..8ed2e8c4015e --- /dev/null +++ b/drivers/pinctrl/renesas/rz/pinctrl_renesas_rz.c @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "r_ioport.h" + +static void pinctrl_configure_pin(const pinctrl_soc_pin_t *pin) +{ + uint32_t cfg = *(uint32_t *)&pin->config; + + R_IOPORT_PinCfg(NULL, pin->port_pin, cfg); +} + +int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) +{ + ARG_UNUSED(reg); + + for (uint8_t i = 0U; i < pin_cnt; i++) { + pinctrl_configure_pin(pins++); + } + + return 0; +} diff --git a/drivers/serial/CMakeLists.txt b/drivers/serial/CMakeLists.txt index 15afe117e477..c3b1f8acdd91 100644 --- a/drivers/serial/CMakeLists.txt +++ b/drivers/serial/CMakeLists.txt @@ -58,6 +58,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_QUICKLOGIC_USBSERIALPORT_S3B uart_ql_us zephyr_library_sources_ifdef(CONFIG_UART_RA8_SCI_B uart_renesas_ra8_sci_b.c) zephyr_library_sources_ifdef(CONFIG_UART_RCAR uart_rcar.c) zephyr_library_sources_ifdef(CONFIG_UART_RENESAS_RA uart_renesas_ra.c) +zephyr_library_sources_ifdef(CONFIG_UART_RENESAS_RZ_SCIF uart_renesas_rz_scif.c) zephyr_library_sources_ifdef(CONFIG_UART_RPI_PICO_PIO uart_rpi_pico_pio.c) zephyr_library_sources_ifdef(CONFIG_UART_RTT_DRIVER uart_rtt.c) zephyr_library_sources_ifdef(CONFIG_UART_RV32M1_LPUART uart_rv32m1_lpuart.c) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 9b76ac170c70..013f0343bd77 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -199,6 +199,7 @@ rsource "Kconfig.ql_usbserialport_s3b" rsource "Kconfig.rcar" rsource "Kconfig.renesas_ra" rsource "Kconfig.renesas_ra8" +rsource "Kconfig.renesas_rz" rsource "Kconfig.rpi_pico" rsource "Kconfig.rtt" rsource "Kconfig.rv32m1_lpuart" diff --git a/drivers/serial/Kconfig.renesas_rz b/drivers/serial/Kconfig.renesas_rz new file mode 100644 index 000000000000..712529a7b20d --- /dev/null +++ b/drivers/serial/Kconfig.renesas_rz @@ -0,0 +1,23 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config UART_RENESAS_RZ_SCIF + bool "Renesas RZ SCIF UART" + default y + depends on DT_HAS_RENESAS_RZ_SCIF_UART_ENABLED + select SERIAL_HAS_DRIVER + select USE_RZ_FSP_SCIF_UART + select PINCTRL + help + Enable Renesas RZ SCIF UART Driver. + +if UART_RENESAS_RZ_SCIF + +config UART_RENESAS_RZG_INIT_DELAY_MS + int "UART initialization delay in milliseconds" + default 8000 + help + This option is to make a delay to wait for the A55 to complete its setting first + before UART initialization of M33. + +endif diff --git a/drivers/serial/uart_renesas_rz_scif.c b/drivers/serial/uart_renesas_rz_scif.c new file mode 100644 index 000000000000..ad08433740fb --- /dev/null +++ b/drivers/serial/uart_renesas_rz_scif.c @@ -0,0 +1,301 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT renesas_rz_scif_uart + +#include +#include +#include +#include "r_scif_uart.h" + +LOG_MODULE_REGISTER(rz_scif_uart); + +struct uart_rz_scif_config { + const struct pinctrl_dev_config *pin_config; + const uart_api_t *fsp_api; +}; + +struct uart_rz_scif_data { + struct uart_config uart_config; + uart_cfg_t *fsp_cfg; + scif_uart_instance_ctrl_t *fsp_ctrl; +}; + +static int uart_rz_scif_poll_in(const struct device *dev, unsigned char *c) +{ + struct uart_rz_scif_data *data = dev->data; + R_SCIFA0_Type *reg = data->fsp_ctrl->p_reg; + + if (reg->FDR_b.R == 0U) { + /* There are no characters available to read. */ + return -1; + } + *c = reg->FRDR; + + return 0; +} + +static void uart_rz_scif_poll_out(const struct device *dev, unsigned char c) +{ + struct uart_rz_scif_data *data = dev->data; + R_SCIFA0_Type *reg = data->fsp_ctrl->p_reg; + + while (!reg->FSR_b.TDFE) { + } + + reg->FTDR = c; + + while (!reg->FSR_b.TEND) { + } +} + +static int uart_rz_scif_err_check(const struct device *dev) +{ + struct uart_rz_scif_data *data = dev->data; + R_SCIFA0_Type *reg = data->fsp_ctrl->p_reg; + + const uint32_t fsr = reg->FSR; + const uint32_t lsr = reg->LSR; + int errors = 0; + + if ((lsr & R_SCIFA0_LSR_ORER_Msk) != 0) { + errors |= UART_ERROR_OVERRUN; + } + if ((fsr & R_SCIFA0_FSR_PER_Msk) != 0) { + errors |= UART_ERROR_PARITY; + } + if ((fsr & R_SCIFA0_FSR_FER_Pos) != 0) { + errors |= UART_ERROR_FRAMING; + } + + return errors; +} + +static int uart_rz_scif_apply_config(const struct device *dev) +{ + struct uart_rz_scif_data *data = dev->data; + + struct uart_config *uart_config = &data->uart_config; + uart_cfg_t *fsp_cfg = data->fsp_cfg; + + scif_baud_setting_t baud_setting; + scif_uart_extended_cfg_t config_extend; + const scif_uart_extended_cfg_t *fsp_config_extend = fsp_cfg->p_extend; + + fsp_err_t fsp_err; + + fsp_err = R_SCIF_UART_BaudCalculate(data->fsp_ctrl, uart_config->baudrate, false, 5000, + &baud_setting); + if (fsp_err) { + return -EIO; + } + + memcpy(fsp_config_extend->p_baud_setting, &baud_setting, sizeof(scif_baud_setting_t)); + + switch (uart_config->data_bits) { + case UART_CFG_DATA_BITS_7: + fsp_cfg->data_bits = UART_DATA_BITS_7; + break; + case UART_CFG_DATA_BITS_8: + fsp_cfg->data_bits = UART_DATA_BITS_8; + break; + default: + return -ENOTSUP; + } + + switch (uart_config->parity) { + case UART_CFG_PARITY_NONE: + fsp_cfg->parity = UART_PARITY_OFF; + break; + case UART_CFG_PARITY_ODD: + fsp_cfg->parity = UART_PARITY_ODD; + break; + case UART_CFG_PARITY_EVEN: + fsp_cfg->parity = UART_PARITY_EVEN; + break; + default: + return -ENOTSUP; + } + + switch (uart_config->stop_bits) { + case UART_CFG_STOP_BITS_1: + fsp_cfg->stop_bits = UART_STOP_BITS_1; + break; + case UART_CFG_STOP_BITS_2: + fsp_cfg->stop_bits = UART_STOP_BITS_2; + break; + default: + return -ENOTSUP; + } + + memcpy(&config_extend, fsp_config_extend->p_baud_setting, sizeof(scif_baud_setting_t)); + + switch (uart_config->flow_ctrl) { + case UART_CFG_FLOW_CTRL_NONE: + config_extend.flow_control = SCIF_UART_FLOW_CONTROL_NONE; + config_extend.uart_mode = SCIF_UART_MODE_RS232; + config_extend.rs485_setting.enable = SCI_UART_RS485_DISABLE; + break; + case UART_CFG_FLOW_CTRL_RTS_CTS: + config_extend.flow_control = SCIF_UART_FLOW_CONTROL_AUTO; + config_extend.uart_mode = SCIF_UART_MODE_RS232; + config_extend.rs485_setting.enable = SCI_UART_RS485_DISABLE; + break; + default: + return -ENOTSUP; + } + + memcpy(fsp_config_extend->p_baud_setting, &config_extend, sizeof(scif_baud_setting_t)); + + return 0; +} + +#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE + +static int uart_rz_scif_configure(const struct device *dev, const struct uart_config *cfg) +{ + int err; + fsp_err_t fsp_err; + const struct uart_rz_scif_config *config = dev->config; + struct uart_rz_scif_data *data = dev->data; + + memcpy(&data->uart_config, cfg, sizeof(struct uart_config)); + + err = uart_rz_scif_apply_config(dev); + + if (err) { + return err; + } + + fsp_err = config->fsp_api->close(data->fsp_ctrl); + if (fsp_err) { + return -EIO; + } + + fsp_err = config->fsp_api->open(data->fsp_ctrl, data->fsp_cfg); + if (fsp_err) { + return -EIO; + } + + R_SCIFA0_Type *reg = data->fsp_ctrl->p_reg; + /* Temporarily disable the DRI interrupt caused by receive data ready */ + /* TODO: support interrupt-driven api */ + reg->SCR_b.RIE = 0; + + return err; +} + +static int uart_rz_scif_config_get(const struct device *dev, struct uart_config *cfg) +{ + struct uart_rz_scif_data *data = dev->data; + + memcpy(cfg, &data->uart_config, sizeof(struct uart_config)); + return 0; +} + +#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */ + +static const struct uart_driver_api uart_rz_scif_driver_api = { + .poll_in = uart_rz_scif_poll_in, + .poll_out = uart_rz_scif_poll_out, + .err_check = uart_rz_scif_err_check, +#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE + .configure = uart_rz_scif_configure, + .config_get = uart_rz_scif_config_get, +#endif +}; + +static int uart_rz_scif_init(const struct device *dev) +{ + const struct uart_rz_scif_config *config = dev->config; + struct uart_rz_scif_data *data = dev->data; + int ret; + + /* Configure dt provided device signals when available */ + ret = pinctrl_apply_state(config->pin_config, PINCTRL_STATE_DEFAULT); + if (ret < 0) { + return ret; + } + + /* uart_rz_scif_apply_config must be called first before open api */ + ret = uart_rz_scif_apply_config(dev); + if (ret < 0) { + return ret; + } + + config->fsp_api->open(data->fsp_ctrl, data->fsp_cfg); + + R_SCIFA0_Type *reg = data->fsp_ctrl->p_reg; + /* Temporarily disable the DRI interrupt caused by receive data ready */ + /* TODO: support interrupt-driven api */ + reg->SCR_b.RIE = 0; + + return 0; +} + +#define UART_RZG_INIT(n) \ + static scif_uart_instance_ctrl_t g_uart##n##_ctrl; \ + static scif_baud_setting_t g_uart##n##_baud_setting; \ + static scif_uart_extended_cfg_t g_uart##n##_cfg_extend = { \ + .bri_ipl = DT_INST_IRQ_BY_NAME(n, bri, priority), \ + .bri_irq = DT_INST_IRQ_BY_NAME(n, bri, irq), \ + .clock = SCIF_UART_CLOCK_INT, \ + .noise_cancel = SCIF_UART_NOISE_CANCELLATION_ENABLE, \ + .p_baud_setting = &g_uart##n##_baud_setting, \ + .rx_fifo_trigger = SCIF_UART_RECEIVE_TRIGGER_MAX, \ + .rts_fifo_trigger = SCIF_UART_RTS_TRIGGER_14, \ + .uart_mode = SCIF_UART_MODE_RS232, \ + .flow_control = SCIF_UART_FLOW_CONTROL_NONE, \ + .rs485_setting = \ + { \ + .enable = (sci_uart_rs485_enable_t)NULL, \ + .polarity = SCI_UART_RS485_DE_POLARITY_HIGH, \ + .de_control_pin = \ + (bsp_io_port_pin_t)SCIF_UART_INVALID_16BIT_PARAM, \ + }, \ + }; \ + static uart_cfg_t g_uart##n##_cfg = { \ + .channel = DT_INST_PROP(n, channel), \ + .p_callback = NULL, \ + .p_context = NULL, \ + .p_extend = &g_uart##n##_cfg_extend, \ + .p_transfer_tx = NULL, \ + .p_transfer_rx = NULL, \ + .rxi_ipl = DT_INST_IRQ_BY_NAME(n, rxi, priority), \ + .txi_ipl = DT_INST_IRQ_BY_NAME(n, txi, priority), \ + .tei_ipl = DT_INST_IRQ_BY_NAME(n, tei, priority), \ + .eri_ipl = DT_INST_IRQ_BY_NAME(n, eri, priority), \ + .rxi_irq = DT_INST_IRQ_BY_NAME(n, rxi, irq), \ + .txi_irq = DT_INST_IRQ_BY_NAME(n, txi, irq), \ + .tei_irq = DT_INST_IRQ_BY_NAME(n, tei, irq), \ + .eri_irq = DT_INST_IRQ_BY_NAME(n, eri, irq), \ + }; \ + PINCTRL_DT_INST_DEFINE(n); \ + static const struct uart_rz_scif_config uart_rz_scif_config_##n = { \ + .pin_config = PINCTRL_DT_INST_DEV_CONFIG_GET(n), .fsp_api = &g_uart_on_scif}; \ + static struct uart_rz_scif_data uart_rz_scif_data_##n = { \ + .uart_config = \ + { \ + .baudrate = DT_INST_PROP_OR(n, current_speed, 115200), \ + .parity = DT_INST_ENUM_IDX_OR(n, parity, UART_CFG_PARITY_NONE), \ + .stop_bits = \ + DT_INST_ENUM_IDX_OR(n, stop_bits, UART_CFG_STOP_BITS_1), \ + .data_bits = \ + DT_INST_ENUM_IDX_OR(n, data_bits, UART_CFG_DATA_BITS_8), \ + .flow_ctrl = DT_INST_PROP_OR(n, hw_flow_control, \ + UART_CFG_FLOW_CTRL_NONE), \ + }, \ + .fsp_cfg = &g_uart##n##_cfg, \ + .fsp_ctrl = &g_uart##n##_ctrl, \ + }; \ + static int uart_rz_scif_init_##n(const struct device *dev) \ + { \ + return uart_rz_scif_init(dev); \ + } \ + DEVICE_DT_INST_DEFINE(n, &uart_rz_scif_init_##n, NULL, &uart_rz_scif_data_##n, \ + &uart_rz_scif_config_##n, PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \ + &uart_rz_scif_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(UART_RZG_INIT) diff --git a/dts/arm/renesas/rz/rzg/r9a08g045.dtsi b/dts/arm/renesas/rz/rzg/r9a08g045.dtsi new file mode 100644 index 000000000000..2bbb5573b15e --- /dev/null +++ b/dts/arm/renesas/rz/rzg/r9a08g045.dtsi @@ -0,0 +1,281 @@ +/* + * Copyright (c) 2024 EPAM Systems + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + compatible = "renesas,r9a08g045"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m33"; + reg = <0>; + clock-frequency = <250000000>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + soc { + pinctrl: pin-controller@41030000 { + compatible = "renesas,rzg-pinctrl"; + reg = <0x41030000 DT_SIZE_K(64)>; + reg-names = "pinctrl"; + + gpio: gpio-common { + compatible = "renesas,rz-gpio-int"; + interrupts = + <429 10>, <430 10>, <431 10>, <432 10>, + <433 10>, <434 10>, <435 10>, <436 10>, + <437 10>, <438 10>, <439 10>, <440 10>, + <441 10>, <442 10>, <443 10>, <444 10>, + <445 10>, <446 10>, <447 10>, <448 10>, + <449 10>, <450 10>, <451 10>, <452 10>, + <453 10>, <454 10>, <455 10>, <456 10>, + <457 10>, <458 10>, <459 10>, <460 10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + gpio0: gpio@0 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <4>; + reg = <0x0>; + status = "disabled"; + }; + + gpio1: gpio@1000 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <5>; + reg = <0x1000>; + status = "disabled"; + }; + + gpio2: gpio@1100 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <4>; + reg = <0x1100>; + status = "disabled"; + }; + + gpio3: gpio@1200 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <4>; + reg = <0x1200>; + status = "disabled"; + }; + + gpio4: gpio@1300 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <6>; + reg = <0x1300>; + status = "disabled"; + }; + + gpio5: gpio@100 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <5>; + reg = <0x100>; + status = "disabled"; + }; + + gpio6: gpio@200 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <5>; + reg = <0x200>; + status = "disabled"; + }; + + gpio7: gpio@1400 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <5>; + reg = <0x1400>; + status = "disabled"; + }; + + gpio8: gpio@1500 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <5>; + reg = <0x1500>; + status = "disabled"; + }; + + gpio9: gpio@1600 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <4>; + reg = <0x1600>; + status = "disabled"; + }; + + gpio10: gpio@1700 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <5>; + reg = <0x1700>; + status = "disabled"; + }; + + gpio11: gpio@300 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <4>; + reg = <0x300>; + status = "disabled"; + }; + + gpio12: gpio@400 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <2>; + reg = <0x400>; + status = "disabled"; + }; + + gpio13: gpio@500 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <5>; + reg = <0x500>; + status = "disabled"; + }; + + gpio14: gpio@600 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <3>; + reg = <0x600>; + status = "disabled"; + }; + + gpio15: gpio@700 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <4>; + reg = <0x700>; + status = "disabled"; + }; + + gpio16: gpio@800 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <2>; + reg = <0x800>; + status = "disabled"; + }; + + gpio17: gpio@900 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells= <2>; + ngpios = <4>; + reg = <0x900>; + status = "disabled"; + }; + + gpio18: gpio@A00 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells=<2>; + ngpios = <6>; + reg = <0xA00>; + status = "disabled"; + }; + }; + }; + + scif0: serial@4004b800 { + compatible = "renesas,rz-scif-uart"; + channel = <0>; + reg = <0x4004b800 0x18>; + interrupts = <320 1>, <321 1>, <322 1>, <323 1>, <324 1>; + interrupt-names = "eri", "bri", "rxi", "txi", "tei"; + status = "disabled"; + }; + scif1: serial@4004bc00 { + compatible = "renesas,rz-scif-uart"; + channel = <1>; + reg = <0x4004bc00 0x18>; + interrupts = <325 1>, <326 1>, <327 1>, <328 1>, <329 1>; + interrupt-names = "eri", "bri", "rxi", "txi", "tei"; + status = "disabled"; + }; + scif2: serial@4004c000 { + compatible = "renesas,rz-scif-uart"; + channel = <2>; + reg = <0x4004c000 0x18>; + interrupts = <330 1>, <331 1>, <332 1>, <333 1>, <334 1>; + interrupt-names = "eri", "bri", "rxi", "txi", "tei"; + status = "disabled"; + }; + scif3: serial@4004c400 { + compatible = "renesas,rz-scif-uart"; + channel = <3>; + reg = <0x4004c400 0x18>; + interrupts = <335 1>, <336 1>, <337 1>, <338 1>, <339 1>; + interrupt-names = "eri", "bri", "rxi", "txi", "tei"; + status = "disabled"; + }; + scif4: serial@4004c800 { + compatible = "renesas,rz-scif-uart"; + channel = <4>; + reg = <0x4004c800 0x18>; + interrupts = <340 1>, <341 1>, <342 1>, <343 1>, <344 1>; + interrupt-names = "eri", "bri", "rxi", "txi", "tei"; + status = "disabled"; + }; + scif5: serial@4004e000 { + compatible = "renesas,rz-scif-uart"; + channel = <5>; + reg = <0x4004e000 0x18>; + interrupts = <345 1>, <346 1>, <347 1>, <348 1>, <349 1>; + interrupt-names = "eri", "bri", "rxi", "txi", "tei"; + status = "disabled"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <7>; +}; diff --git a/dts/bindings/gpio/renesas,rz-gpio-int.yaml b/dts/bindings/gpio/renesas,rz-gpio-int.yaml new file mode 100644 index 000000000000..bffe75c2d7b5 --- /dev/null +++ b/dts/bindings/gpio/renesas,rz-gpio-int.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas RZ GPIO Interrupt + +compatible: "renesas,rz-gpio-int" + +include: base.yaml + +properties: + interrupts: + required: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 diff --git a/dts/bindings/gpio/renesas,rz-gpio.yaml b/dts/bindings/gpio/renesas,rz-gpio.yaml new file mode 100644 index 000000000000..9b4a37e6c174 --- /dev/null +++ b/dts/bindings/gpio/renesas,rz-gpio.yaml @@ -0,0 +1,43 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: | + Reneses RZ GPIO controller node. + Sample of usage: + gpio-consumer{ + out-gpio = <&gpio8 2 (GPIO_PULL_UP); + }; + &gpio8{ + irq = <2 10>, <9 1>; + status = "okay"; + }; + Example above will configure pin 2 port 8: + - Using interrupt TINT10 + - Set Pullup + + +compatible: "renesas,rz-gpio" + +include: +- name: base.yaml + property-allowlist: + - status + - reg + - label +- name: gpio-controller.yaml + +properties: + reg: + required: true + description: GPIO port number + + irqs: + type: array + description: pin-irq pairs + + "#gpio-cells": + const: 2 + +gpio-cells: +- pin +- flags diff --git a/dts/bindings/pinctrl/renesas,rzg-pinctrl.yaml b/dts/bindings/pinctrl/renesas,rzg-pinctrl.yaml new file mode 100644 index 000000000000..2b17a67857cf --- /dev/null +++ b/dts/bindings/pinctrl/renesas,rzg-pinctrl.yaml @@ -0,0 +1,95 @@ +# Copyright (c) 2024 Epam Systems +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: | + Below generic example shows of supported pinctrl definitions: + + #include + example_pins: device_pin { + device-pinmux { + pinmux = , + ; + bias_pull_up; + renesas,filter = RZG_FILTER_SET(RZG_FILNUM_8_STAGE,RZG_FILCLKSEL_DIV_18000); + drive-strength = <1>; + }; + + device-spins { + pins = , ; + input-enable; + renesas,filter = RZG_FILTER_SET(RZG_FILNUM_8_STAGE,RZG_FILCLKSEL_DIV_18000); + drive-strength = <2>; + }; + }; + + +compatible: renesas,rzg-pinctrl + +include: base.yaml +properties: + reg: + required: true + + reg-names: + required: true + +child-binding: + description: | + This RZG pins mux/cfg nodes description. + + child-binding: + description: | + The RZG pinmux/pincfg configuration nodes description. + + include: + - name: pincfg-node.yaml + property-allowlist: + - bias-disable + - bias-high-impedance + - bias-pull-down + - bias-pull-up + - bias-pull-pin-default + - drive-strength + - input-enable + - input-disable + - output-enable + - power-source + - low-power-enable + - low-power-disable + + properties: + pinmux: + type: array + description: | + Pinmux configuration node. + Values are constructed from GPIO port number, pin number, and + alternate function configuration number using the RZG_PINMUX() + helper macro in pinctrl_rzg.h + + pins: + type: array + description: | + Special Purpose pins configuration node. + Values are define in pinctrl_rzg.h. + Ex: BSP_IO_XSPI_IO0,BSP_IO_I3C_SCL,... + + drive-strength: + type: int + default: 0 + description: | + Maximum sink or source current in mA for pin which shell be selected + depending on device and pin group. + + renesas,filter: + type: int + default: 0 + description: | + Digital Noise Filter configuration for a pin which shell be defined + using RZG_FILTER_SET() helper macro in pinctrl_rzg.h to specify + FILNUM_m and FILCLKSEL_m. With 24Mhz external clock: + - min debounce time will be 166.666ns for FILNUM_m=0 and FILCLKSEL_m=0 + - max debounce time will be 24ms for FILNUM_m=3 and FILCLKSEL_m=3. + This property intentionally redefined to avoid unnecessary conversation from usec to + FILNUM_m and FILCLKSEL_m values depending on external clock value as this configuration + is static. diff --git a/dts/bindings/serial/renesas,rz-scif-uart.yaml b/dts/bindings/serial/renesas,rz-scif-uart.yaml new file mode 100644 index 000000000000..b362a09e4741 --- /dev/null +++ b/dts/bindings/serial/renesas,rz-scif-uart.yaml @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas RZ SCIF UART controller + +compatible: "renesas,rz-scif-uart" + +include: [uart-controller.yaml, pinctrl-device.yaml] + +properties: + channel: + type: int + required: true diff --git a/include/zephyr/dt-bindings/gpio/renesas-rz-gpio.h b/include/zephyr/dt-bindings/gpio/renesas-rz-gpio.h new file mode 100644 index 000000000000..30729af98bd3 --- /dev/null +++ b/include/zephyr/dt-bindings/gpio/renesas-rz-gpio.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZ_GPIO_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZ_GPIO_H_ + +/*********************************RZG3S*****************************************/ + +/** + * @brief RZ G3S specific GPIO Flags + * The pin driving ability flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as + * follows: + * - Bit 9..8: Pin driving ability value + * - Bit 11..10: Digital Noise Filter Clock Selection value + * - Bit 13..12: Digital Noise Filter Number value + * - Bit 14: Digital Noise Filter ON/OFF + * example: + * gpio-consumer { + * out-gpios = <&port8 2 (GPIO_PULL_UP | RZG3S_GPIO_FILTER_SET(1, 3, 3))>; + * }; + * gpio-consumer { + * out-gpios = <&port8 2 (GPIO_PULL_UP | RZG3S_GPIO_IOLH_SET(2))>; + * }; + */ + +/* GPIO drive IOLH */ +#define RZG3S_GPIO_IOLH_SHIFT 7U +#define RZG3S_GPIO_IOLH_SET(iolh_val) (iolh_val << RZG3S_GPIO_IOLH_SHIFT) + +/* GPIO filter */ +#define RZG3S_GPIO_FILTER_SHIFT 9U +#define RZG3S_GPIO_FILNUM_SHIFT 1U +#define RZG3S_GPIO_FILCLKSEL_SHIFT 3U +#define RZG3S_GPIO_FILTER_SET(fillonoff, filnum, filclksel) \ + (((fillonoff) | ((filnum) << RZG3S_GPIO_FILNUM_SHIFT) | \ + ((filclksel) << RZG3S_GPIO_FILCLKSEL_SHIFT)) \ + << RZG3S_GPIO_FILTER_SHIFT) + +/*******************************************************************************/ + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZ_GPIO_H_ */ diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg-common.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg-common.h new file mode 100644 index 000000000000..da9266ac780e --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg-common.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG_COMMON_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG_COMMON_H_ + +/* Superset list of all possible IO ports. */ +#define PORT_00 0x0000 /* IO port 0 */ +#define PORT_01 0x1000 /* IO port 1 */ +#define PORT_02 0x1100 /* IO port 2 */ +#define PORT_03 0x1200 /* IO port 3 */ +#define PORT_04 0x1300 /* IO port 4 */ +#define PORT_05 0x0100 /* IO port 5 */ +#define PORT_06 0x0200 /* IO port 6 */ +#define PORT_07 0x1400 /* IO port 7 */ +#define PORT_08 0x1500 /* IO port 8 */ +#define PORT_09 0x1600 /* IO port 9 */ +#define PORT_10 0x1700 /* IO port 10 */ +#define PORT_11 0x0300 /* IO port 11 */ +#define PORT_12 0x0400 /* IO port 12 */ +#define PORT_13 0x0500 /* IO port 13 */ +#define PORT_14 0x0600 /* IO port 14 */ +#define PORT_15 0x0700 /* IO port 15 */ +#define PORT_16 0x0800 /* IO port 16 */ +#define PORT_17 0x0900 /* IO port 17 */ +#define PORT_18 0x0A00 /* IO port 18 */ + +/* + * Create the value contain port/pin/function information + * + * port: port number BSP_IO_PORT_00..BSP_IO_PORT_18 + * pin: pin number + * func: pin function + */ +#define RZG_PINMUX(port, pin, func) (port | pin | (func << 4)) + +/* Special purpose port */ +#define BSP_IO_NMI 0xFFFF0000 /* NMI */ + +#define BSP_IO_TMS_SWDIO 0xFFFF0100 /* TMS_SWDIO */ +#define BSP_IO_TDO 0xFFFF0101 /* TDO */ + +#define BSP_IO_AUDIO_CLK1 0xFFFF0200 /* AUDIO_CLK1 */ +#define BSP_IO_AUDIO_CLK2 0xFFFF0201 /* AUDIO_CLK2 */ + +#define BSP_IO_XSPI_SPCLK 0xFFFF0400 /* XSPI_SPCLK */ +#define BSP_IO_XSPI_RESET_N 0xFFFF0401 /* XSPI_RESET_N */ +#define BSP_IO_XSPI_WP_N 0xFFFF0402 /* XSPI_WP_N */ +#define BSP_IO_XSPI_DS 0xFFFF0403 /* XSPI_DS */ +#define BSP_IO_XSPI_CS0_N 0xFFFF0404 /* XSPI_CS0_N */ +#define BSP_IO_XSPI_CS1_N 0xFFFF0405 /* XSPI_CS1_N */ + +#define BSP_IO_XSPI_IO0 0xFFFF0500 /* XSPI_IO0 */ +#define BSP_IO_XSPI_IO1 0xFFFF0501 /* XSPI_IO1 */ +#define BSP_IO_XSPI_IO2 0xFFFF0502 /* XSPI_IO2 */ +#define BSP_IO_XSPI_IO3 0xFFFF0503 /* XSPI_IO3 */ +#define BSP_IO_XSPI_IO4 0xFFFF0504 /* XSPI_IO4 */ +#define BSP_IO_XSPI_IO5 0xFFFF0505 /* XSPI_IO5 */ +#define BSP_IO_XSPI_IO6 0xFFFF0506 /* XSPI_IO6 */ +#define BSP_IO_XSPI_IO7 0xFFFF0507 /* XSPI_IO7 */ + +#define BSP_IO_WDTOVF_PERROUT 0xFFFF0600 /* WDTOVF_PERROUT */ + +#define BSP_IO_I3C_SDA 0xFFFF0900 /* I3C_SDA */ +#define BSP_IO_I3C_SCL 0xFFFF0901 /* I3C_SCL */ + +#define BSP_IO_SD0_CLK 0xFFFF1000 /* CD0_CLK */ +#define BSP_IO_SD0_CMD 0xFFFF1001 /* CD0_CMD */ +#define BSP_IO_SD0_RST_N 0xFFFF1002 /* CD0_RST_N */ + +#define BSP_IO_SD0_DATA0 0xFFFF1100 /* SD0_DATA0 */ +#define BSP_IO_SD0_DATA1 0xFFFF1101 /* SD0_DATA1 */ +#define BSP_IO_SD0_DATA2 0xFFFF1102 /* SD0_DATA2 */ +#define BSP_IO_SD0_DATA3 0xFFFF1103 /* SD0_DATA3 */ +#define BSP_IO_SD0_DATA4 0xFFFF1104 /* SD0_DATA4 */ +#define BSP_IO_SD0_DATA5 0xFFFF1105 /* SD0_DATA5 */ +#define BSP_IO_SD0_DATA6 0xFFFF1106 /* SD0_DATA6 */ +#define BSP_IO_SD0_DATA7 0xFFFF1107 /* SD0_DATA7 */ + +#define BSP_IO_SD1_CLK 0xFFFF1200 /* SD1_CLK */ +#define BSP_IO_SD1_CMD 0xFFFF1201 /* SD1_CMD */ + +#define BSP_IO_SD1_DATA0 0xFFFF1300 /* SD1_DATA0 */ +#define BSP_IO_SD1_DATA1 0xFFFF1301 /* SD1_DATA1 */ +#define BSP_IO_SD1_DATA2 0xFFFF1302 /* SD1_DATA2 */ +#define BSP_IO_SD1_DATA3 0xFFFF1303 /* SD1_DATA3 */ + +/*FILNUM*/ +#define RZG_FILNUM_4_STAGE 0 +#define RZG_FILNUM_8_STAGE 1 +#define RZG_FILNUM_12_STAGE 2 +#define RZG_FILNUM_16_STAGE 3 + +/*FILCLKSEL*/ +#define RZG_FILCLKSEL_NOT_DIV 0 +#define RZG_FILCLKSEL_DIV_9000 1 +#define RZG_FILCLKSEL_DIV_18000 2 +#define RZG_FILCLKSEL_DIV_36000 3 + +#define RZG_FILTER_SET(filnum, filclksel) (((filnum) & 0x3) << 0x2) | (filclksel & 0x3) + +#endif /*ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG_COMMON_H_*/ diff --git a/modules/Kconfig.renesas_fsp b/modules/Kconfig.renesas_fsp index 4b9eb15ddd4e..362a41f86f11 100644 --- a/modules/Kconfig.renesas_fsp +++ b/modules/Kconfig.renesas_fsp @@ -8,6 +8,11 @@ config HAS_RENESAS_RA_FSP help Enable Renesas RA FSP support +config HAS_RENESAS_RZ_FSP + bool + help + Enable Renesas RZ FSP support + if HAS_RENESAS_RA_FSP config USE_RA_FSP_SCI_B_UART @@ -92,3 +97,17 @@ config USE_RA_FSP_ETHER Enable RA FSP Ethernet driver endif # HAS_RENESAS_RA_FSP + +if HAS_RENESAS_RZ_FSP + +config USE_RZ_FSP_IOPORT + bool + help + Enable RZ FSP IOPORT driver + +config USE_RZ_FSP_SCIF_UART + bool + help + Enable RZ FSP SCIF UART driver + +endif diff --git a/samples/basic/button/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay b/samples/basic/button/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay new file mode 100644 index 000000000000..3c8c3537e39e --- /dev/null +++ b/samples/basic/button/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&gpio{ + status = "okay"; +}; + +&gpio18{ + irqs = <0 16>; +}; diff --git a/soc/renesas/rz/CMakeLists.txt b/soc/renesas/rz/CMakeLists.txt new file mode 100644 index 000000000000..77d3f459bf15 --- /dev/null +++ b/soc/renesas/rz/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories_ifdef(CONFIG_HAS_RENESAS_RZ_FSP common) + +add_subdirectory(${SOC_SERIES}) diff --git a/soc/renesas/rz/Kconfig b/soc/renesas/rz/Kconfig new file mode 100644 index 000000000000..0987cc809c3c --- /dev/null +++ b/soc/renesas/rz/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_RENESAS_RZ + +rsource "*/Kconfig" + +endif # SOC_FAMILY_RENESAS_RZ diff --git a/soc/renesas/rz/Kconfig.defconfig b/soc/renesas/rz/Kconfig.defconfig new file mode 100644 index 000000000000..460b3387e760 --- /dev/null +++ b/soc/renesas/rz/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_RENESAS_RZ + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_RENESAS_RZ diff --git a/soc/renesas/rz/Kconfig.soc b/soc/renesas/rz/Kconfig.soc new file mode 100644 index 000000000000..c6457e225213 --- /dev/null +++ b/soc/renesas/rz/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_RENESAS_RZ + bool + +config SOC_FAMILY + default "renesas_rz" if SOC_FAMILY_RENESAS_RZ + +rsource "*/Kconfig.soc" diff --git a/soc/renesas/rz/common/pinctrl_rzg.h b/soc/renesas/rz/common/pinctrl_rzg.h new file mode 100644 index 000000000000..e2ef13fbe33f --- /dev/null +++ b/soc/renesas/rz/common/pinctrl_rzg.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZG_H_ +#define ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZG_H_ + +#include +#include +#include +#include "r_ioport.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*Porting*/ +typedef struct pinctrl_cfg_data_t { + uint32_t reserved: 4; + uint32_t pupd_reg: 6; + uint32_t iolh_reg: 6; + uint32_t pmc_reg: 2; + uint32_t ien_reg: 1; + uint32_t filonoff_reg: 1; + uint32_t filnum_reg: 2; + uint32_t filclksel_reg: 2; + uint32_t pfc_reg: 3; +} pinctrl_cfg_data_t; + +typedef struct pinctrl_soc_pin_t { + bsp_io_port_pin_t port_pin; + pinctrl_cfg_data_t config; +} pinctrl_soc_pin_t; + +/* Iterate over each pinctrl-n phandle child */ +#define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx) \ + DT_FOREACH_CHILD(DT_PHANDLE_BY_IDX(node_id, state_prop, idx), \ + Z_PINCTRL_STATE_PIN_CHILD_INIT) + +/* Iterate over each pinctrl-n phandle child */ +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + {DT_FOREACH_PROP_ELEM_SEP(node_id, prop, Z_PINCTRL_STATE_PIN_INIT, ())}; + +#define Z_PINCTRL_STATE_PIN_CHILD_INIT(node_id) \ + COND_CODE_1(DT_NODE_HAS_PROP(node_id, pinmux), \ + (DT_FOREACH_PROP_ELEM(node_id, pinmux, Z_PINCTRL_PINMUX_INIT)), \ + ()) \ + COND_CODE_1(DT_NODE_HAS_PROP(node_id, pins), \ + (DT_FOREACH_PROP_ELEM(node_id, pins, Z_PINCTRL_SPECIAL_PINS_INIT)), \ + ()) + +#define RZG_GET_PORT_PIN(pinmux) (pinmux & ~(0xF << 4)) +#define RZG_GET_FUNC(pinmux) ((pinmux & 0xF0) >> 4) + +#define RZG_GET_PU_PD(node_id) \ + DT_PROP(node_id, bias_pull_up) == 1 ? 1U : (DT_PROP(node_id, bias_pull_down) == 1 ? 2U : 0U) + +#define RZG_GET_FILNUM(node_id) ((DT_PROP(node_id, renesas_filter) >> 2) & 0x3) + +#define RZG_GET_FILCLKSEL(node_id) (DT_PROP(node_id, renesas_filter) & 0x3) + +#define RZG_FILTER_ON_OFF(node_id) COND_CODE_0(DT_PROP(node_id, renesas_filter), (0), (1)) + +/* Process pinmux cfg */ +#define Z_PINCTRL_PINMUX_INIT(node_id, state_prop, idx) \ + { \ + .port_pin = RZG_GET_PORT_PIN(DT_PROP_BY_IDX(node_id, state_prop, idx)), \ + .config = \ + { \ + .reserved = 0, \ + .pupd_reg = RZG_GET_PU_PD(node_id), \ + .iolh_reg = DT_PROP(node_id, drive_strength), \ + .pmc_reg = 1, \ + .ien_reg = DT_PROP(node_id, input_enable), \ + .filonoff_reg = RZG_FILTER_ON_OFF(node_id), \ + .filnum_reg = RZG_GET_FILNUM(node_id), \ + .filclksel_reg = RZG_GET_FILCLKSEL(node_id), \ + .pfc_reg = \ + (RZG_GET_FUNC(DT_PROP_BY_IDX(node_id, state_prop, idx)) - \ + 1), \ + }, \ + }, + +#define Z_PINCTRL_SPECIAL_PINS_INIT(node_id, state_prop, idx) \ + { \ + .port_pin = DT_PROP_BY_IDX(node_id, state_prop, idx), \ + .config = \ + { \ + .reserved = 0, \ + .pupd_reg = RZG_GET_PU_PD(node_id), \ + .iolh_reg = DT_PROP(node_id, drive_strength), \ + .pmc_reg = 0, \ + .ien_reg = DT_PROP(node_id, input_enable), \ + .filonoff_reg = RZG_FILTER_ON_OFF(node_id), \ + .filnum_reg = RZG_GET_FILNUM(node_id), \ + .filclksel_reg = RZG_GET_FILCLKSEL(node_id), \ + .pfc_reg = 0, \ + }, \ + }, + +#ifdef __cplusplus +} +#endif +#endif /*ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZG_H_*/ diff --git a/soc/renesas/rz/rzg3s/CMakeLists.txt b/soc/renesas/rz/rzg3s/CMakeLists.txt new file mode 100644 index 000000000000..2db47f0bb794 --- /dev/null +++ b/soc/renesas/rz/rzg3s/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/rz/rzg3s/Kconfig b/soc/renesas/rz/rzg3s/Kconfig new file mode 100644 index 000000000000..15eaa95f1780 --- /dev/null +++ b/soc/renesas/rz/rzg3s/Kconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2024 EPAM Systems +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RZG3S + select ARM + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select HAS_RENESAS_RZ_FSP + select CPU_CORTEX_M_HAS_DWT + select SOC_EARLY_INIT_HOOK diff --git a/soc/renesas/rz/rzg3s/Kconfig.defconfig b/soc/renesas/rz/rzg3s/Kconfig.defconfig new file mode 100644 index 000000000000..77439d92b82a --- /dev/null +++ b/soc/renesas/rz/rzg3s/Kconfig.defconfig @@ -0,0 +1,29 @@ +# Copyright (c) 2024 EPAM Systems +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RZG3S + +config NUM_IRQS + default 480 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +config SYS_CLOCK_EXISTS + default y + +# This is required to support debug with xSPI boot when Zephyr already booted by TF-A +config INIT_ARCH_HW_AT_BOOT + default y + +config BUILD_OUTPUT_S19 + default y + +endif # SOC_SERIES_RZG3S diff --git a/soc/renesas/rz/rzg3s/Kconfig.soc b/soc/renesas/rz/rzg3s/Kconfig.soc new file mode 100644 index 000000000000..dc65a2303ed2 --- /dev/null +++ b/soc/renesas/rz/rzg3s/Kconfig.soc @@ -0,0 +1,24 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RZG3S + bool + select SOC_FAMILY_RENESAS_RZ + help + Renesas RZ/G3S series + +config SOC_SERIES + default "rzg3s" if SOC_SERIES_RZG3S + +config SOC_R9A08G045S33GBG + bool + select SOC_SERIES_RZG3S + help + R9A08G045S33GBG + +config SOC_R9A08G045S33GBG_CM33 + bool + select SOC_R9A08G045S33GBG + +config SOC + default "r9a08g045s33gbg" if SOC_R9A08G045S33GBG diff --git a/soc/renesas/rz/rzg3s/pinctrl_soc.h b/soc/renesas/rz/rzg3s/pinctrl_soc.h new file mode 100644 index 000000000000..8ce37a9d7a89 --- /dev/null +++ b/soc/renesas/rz/rzg3s/pinctrl_soc.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_RENESAS_RZ_RZG3S_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RZ_RZG3S_PINCTRL_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RZ_RZG3S_PINCTRL_SOC_H_ */ diff --git a/soc/renesas/rz/rzg3s/soc.c b/soc/renesas/rz/rzg3s/soc.c new file mode 100644 index 000000000000..a263b91b2838 --- /dev/null +++ b/soc/renesas/rz/rzg3s/soc.c @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for Renesas RZ/G3S Group + */ + +#include +#include + +/* System core clock is set to 250 MHz by IPL of A55 */ +uint32_t SystemCoreClock = 250000000; + +void soc_early_init_hook(void) +{ + bsp_clock_init(); + + /* This delay is required to wait for the A55 to complete its setting first before */ + /* UART initialization of M33 */ + R_BSP_SoftwareDelay(CONFIG_UART_RENESAS_RZG_INIT_DELAY_MS, BSP_DELAY_UNITS_MILLISECONDS); +} diff --git a/soc/renesas/rz/rzg3s/soc.h b/soc/renesas/rz/rzg3s/soc.h new file mode 100644 index 000000000000..1d2a2d05cfd1 --- /dev/null +++ b/soc/renesas/rz/rzg3s/soc.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_RENESAS_RZG3S_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RZG3S_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RZG3S_SOC_H_ */ diff --git a/soc/renesas/rz/soc.yml b/soc/renesas/rz/soc.yml new file mode 100644 index 000000000000..3cc8edd8baf7 --- /dev/null +++ b/soc/renesas/rz/soc.yml @@ -0,0 +1,8 @@ +family: + - name: renesas_rz + series: + - name: rzg3s + socs: + - name: r9a08g045s33gbg + cpuclusters: + - name: cm33 diff --git a/tests/drivers/gpio/gpio_api_1pin/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay b/tests/drivers/gpio/gpio_api_1pin/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay new file mode 100644 index 000000000000..7ab7cc704921 --- /dev/null +++ b/tests/drivers/gpio/gpio_api_1pin/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + led0 = &led_0; + }; + + gpio-led { + compatible = "gpio-leds"; + led_0: led_0 { + gpios = <&gpio13 1 0>; + }; + }; +}; + +&gpio{ + status = "okay"; +}; + +&gpio13 { + irqs = <1 1>; + status = "okay"; +}; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.conf b/tests/drivers/gpio/gpio_basic_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.conf new file mode 100644 index 000000000000..b9d02cf11d5d --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.conf @@ -0,0 +1 @@ +CONFIG_SKIP_PULL_TEST=y diff --git a/tests/drivers/gpio/gpio_basic_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay b/tests/drivers/gpio/gpio_basic_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay new file mode 100644 index 000000000000..58b19b4dc123 --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + resources { + compatible = "test-gpio-basic-api"; + out-gpios = <&gpio8 2 GPIO_ACTIVE_HIGH>; + in-gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio{ + status = "okay"; +}; + +&gpio8{ + irqs = <3 20>; + status = "okay"; +}; diff --git a/tests/lib/cpp/cxx/testcase.yaml b/tests/lib/cpp/cxx/testcase.yaml index e9fc90855c4c..8535faf9c30f 100644 --- a/tests/lib/cpp/cxx/testcase.yaml +++ b/tests/lib/cpp/cxx/testcase.yaml @@ -35,7 +35,8 @@ tests: cpp.main.cpp98: arch_exclude: posix # Exclude nRF54L series, nRF54H20 and nRF9280 as Nordic HAL is not compatible with C++98. - # Exclude CONFIG_HAS_RENESAS_RA_FSP as Renesas RA HAL is not compatible with C++98. + # Exclude CONFIG_HAS_RENESAS_RA_FSP and CONFIG_HAS_RENESAS_RZ_FSP as Renesas HALs are not + # compatible with C++98. platform_exclude: - nrf54l15dk/nrf54l05/cpuapp - nrf54l15dk/nrf54l10/cpuapp @@ -45,7 +46,7 @@ tests: - nrf54h20dk/nrf54h20/cpurad - nrf9280pdk/nrf9280/cpuapp - nrf9280pdk/nrf9280/cpurad - filter: not CONFIG_HAS_RENESAS_RA_FSP + filter: not CONFIG_HAS_RENESAS_RA_FSP and not CONFIG_HAS_RENESAS_RZ_FSP build_only: true extra_configs: - CONFIG_STD_CPP98=y diff --git a/west.yml b/west.yml index 9e815cbc6ad3..c149fc7db3ae 100644 --- a/west.yml +++ b/west.yml @@ -215,7 +215,7 @@ manifest: - hal - name: hal_renesas path: modules/hal/renesas - revision: f77a8501c2adeec8eb98f51ee5c5c5aa095575a1 + revision: ca0be9e9c56bdedf2f18426639c5aca79a4e06ae groups: - hal - name: hal_rpi_pico