From 2de01ce4db996a32698330a4a94a1ef939641ddc Mon Sep 17 00:00:00 2001
From: Hao Luo <hluo@ambiq.com>
Date: Thu, 9 Jan 2025 11:47:18 +0800
Subject: [PATCH] dts: ambiq: use macros to represent reg address/size

Changed to use macros defined in HAL to represent reg
address/size in dtsi.

Signed-off-by: Hao Luo <hluo@ambiq.com>
---
 boards/ambiq/apollo4p_evb/apollo4p_evb.dts    |   4 +-
 .../apollo4p_evb/apollo4p_evb_connector.dtsi  |   2 +-
 dts/arm/ambiq/ambiq_apollo3_blue.dtsi         | 207 ++++++++--------
 dts/arm/ambiq/ambiq_apollo3p_blue.dtsi        | 233 +++++++++---------
 dts/arm/ambiq/ambiq_apollo4p.dtsi             | 213 ++++++++--------
 dts/arm/ambiq/ambiq_apollo4p_blue.dtsi        | 206 ++++++++--------
 west.yml                                      |   2 +-
 7 files changed, 435 insertions(+), 432 deletions(-)

diff --git a/boards/ambiq/apollo4p_evb/apollo4p_evb.dts b/boards/ambiq/apollo4p_evb/apollo4p_evb.dts
index 71ccc5399fdc09..428acc9b8485e4 100644
--- a/boards/ambiq/apollo4p_evb/apollo4p_evb.dts
+++ b/boards/ambiq/apollo4p_evb/apollo4p_evb.dts
@@ -95,7 +95,7 @@
 	status = "okay";
 };
 
-&iom0_i2c {
+&i2c0 {
 	compatible = "ambiq,i2c";
 	pinctrl-0 = <&i2c0_default>;
 	pinctrl-names = "default";
@@ -105,7 +105,7 @@
 	status = "okay";
 };
 
-&iom1_spi {
+&spi1 {
 	compatible = "ambiq,spi";
 	pinctrl-0 = <&spi1_default>;
 	pinctrl-names = "default";
diff --git a/boards/ambiq/apollo4p_evb/apollo4p_evb_connector.dtsi b/boards/ambiq/apollo4p_evb/apollo4p_evb_connector.dtsi
index e083db991e24db..32d5814986bc81 100644
--- a/boards/ambiq/apollo4p_evb/apollo4p_evb_connector.dtsi
+++ b/boards/ambiq/apollo4p_evb/apollo4p_evb_connector.dtsi
@@ -118,4 +118,4 @@
 	};
 };
 
-spi1: &iom1_spi {};
+spi1: &spi1 {};
diff --git a/dts/arm/ambiq/ambiq_apollo3_blue.dtsi b/dts/arm/ambiq/ambiq_apollo3_blue.dtsi
index 53ef76bbd2059c..27c8ce27dc8be2 100644
--- a/dts/arm/ambiq/ambiq_apollo3_blue.dtsi
+++ b/dts/arm/ambiq/ambiq_apollo3_blue.dtsi
@@ -3,6 +3,7 @@
 #include <arm/armv7-m.dtsi>
 #include <mem.h>
 #include <freq.h>
+#include <apollo3/am_apollo3.h>
 #include <zephyr/dt-bindings/adc/adc.h>
 #include <zephyr/dt-bindings/i2c/i2c.h>
 #include <zephyr/dt-bindings/gpio/gpio.h>
@@ -61,124 +62,124 @@
 	};
 
 	/* TCM */
-	tcm: tcm@10000000 {
+	tcm: tcm@APOLLO3_TCM {
 		compatible = "zephyr,memory-region";
-		reg = <0x10000000 0x10000>;
+		reg = <APOLLO3_TCM_BASE APOLLO3_TCM_SIZE>;
 		zephyr,memory-region = "ITCM";
 	};
 
 	/* SRAM */
-	sram0: memory@10010000 {
+	sram0: memory@APOLLO3_SRAM {
 		compatible = "mmio-sram";
-		reg = <0x10010000 0x50000>;
+		reg = <APOLLO3_SRAM_BASE APOLLO3_SRAM_SIZE>;
 	};
 
 	soc {
 		compatible = "ambiq,apollo3-blue", "ambiq,apollo3x", "simple-bus";
 
-		flash: flash-controller@0 {
+		flash: flash-controller@APOLLO3_FLASH {
 			compatible = "ambiq,flash-controller";
-			reg = <0x00000000 0x100000>;
+			reg = <APOLLO3_FLASH_BASE APOLLO3_FLASH_SIZE>;
 
 			#address-cells = <1>;
 			#size-cells = <1>;
 
 			/* Flash region */
-			flash0: flash@0 {
+			flash0: flash@APOLLO3_FLASH {
 				compatible = "soc-nv-flash";
-				reg = <0x00000000 0x100000>;
+				reg = <APOLLO3_FLASH_BASE APOLLO3_FLASH_SIZE>;
 			};
 		};
 
-		pwrcfg: pwrcfg@40021000 {
+		pwrcfg: pwrcfg@APOLLO3_PWRCTRL {
 			compatible = "ambiq,pwrctrl";
-			reg = <0x40021000 0x400>;
+			reg = <APOLLO3_PWRCTRL_BASE APOLLO3_PWRCTRL_SIZE>;
 			#pwrcfg-cells = <2>;
 		};
 
-		stimer0: stimer@40008140 {
+		stimer0: stimer@APOLLO3_STIMER {
 			compatible = "ambiq,stimer";
-			reg = <0x40008140 0x80>;
-			interrupts = <23 0>;
+			reg = <APOLLO3_STIMER_BASE APOLLO3_STIMER_SIZE>;
+			interrupts = <APOLLO3_STIMER_CMPR0_IRQ 0>;
 			status = "okay";
 		};
 
-		counter0: counter@40008000 {
+		counter0: counter@APOLLO3_CTIMER0 {
 			compatible = "ambiq,counter";
-			reg = <0x40008000 0x20>;
-			interrupts = <14 0>;
+			reg = <APOLLO3_CTIMER0_BASE APOLLO3_CTIMER0_SIZE>;
+			interrupts = <APOLLO3_CTIMER_IRQ 0>;
 			clock-frequency = <DT_FREQ_M(3)>;
 			clk-source = <2>;
 			status = "disabled";
 		};
 
-		counter1: counter@40008020 {
+		counter1: counter@APOLLO3_CTIMER1 {
 			compatible = "ambiq,counter";
-			reg = <0x40008020 0x20>;
-			interrupts = <14 0>;
+			reg = <APOLLO3_CTIMER1_BASE APOLLO3_CTIMER1_SIZE>;
+			interrupts = <APOLLO3_CTIMER_IRQ 0>;
 			clock-frequency = <DT_FREQ_M(3)>;
 			clk-source = <2>;
 			status = "disabled";
 		};
 
-		counter2: counter@40008040 {
+		counter2: counter@APOLLO3_CTIMER2 {
 			compatible = "ambiq,counter";
-			reg = <0x40008040 0x20>;
-			interrupts = <14 0>;
+			reg = <APOLLO3_CTIMER2_BASE APOLLO3_CTIMER2_SIZE>;
+			interrupts = <APOLLO3_CTIMER_IRQ 0>;
 			clock-frequency = <DT_FREQ_M(3)>;
 			clk-source = <2>;
 			status = "disabled";
 		};
 
-		counter3: counter@40008060 {
+		counter3: counter@APOLLO3_CTIMER3 {
 			compatible = "ambiq,counter";
-			reg = <0x40008060 0x20>;
-			interrupts = <14 0>;
+			reg = <APOLLO3_CTIMER3_BASE APOLLO3_CTIMER3_SIZE>;
+			interrupts = <APOLLO3_CTIMER_IRQ 0>;
 			clock-frequency = <DT_FREQ_M(3)>;
 			clk-source = <2>;
 			status = "disabled";
 		};
 
-		counter4: counter@40008080 {
+		counter4: counter@APOLLO3_CTIMER4 {
 			compatible = "ambiq,counter";
-			reg = <0x40008080 0x20>;
-			interrupts = <14 0>;
+			reg = <APOLLO3_CTIMER4_BASE APOLLO3_CTIMER4_SIZE>;
+			interrupts = <APOLLO3_CTIMER_IRQ 0>;
 			clock-frequency = <DT_FREQ_M(3)>;
 			clk-source = <2>;
 			status = "disabled";
 		};
 
-		counter5: counter@400080a0 {
+		counter5: counter@APOLLO3_CTIMER5 {
 			compatible = "ambiq,counter";
-			reg = <0x400080A0 0x20>;
-			interrupts = <14 0>;
+			reg = <APOLLO3_CTIMER5_BASE APOLLO3_CTIMER5_SIZE>;
+			interrupts = <APOLLO3_CTIMER_IRQ 0>;
 			clock-frequency = <DT_FREQ_M(3)>;
 			clk-source = <2>;
 			status = "disabled";
 		};
 
-		counter6: counter@400080c0 {
+		counter6: counter@APOLLO3_CTIMER6 {
 			compatible = "ambiq,counter";
-			reg = <0x400080C0 0x20>;
-			interrupts = <14 0>;
+			reg = <APOLLO3_CTIMER6_BASE APOLLO3_CTIMER6_SIZE>;
+			interrupts = <APOLLO3_CTIMER_IRQ 0>;
 			clock-frequency = <DT_FREQ_M(3)>;
 			clk-source = <2>;
 			status = "disabled";
 		};
 
-		counter7: counter@400080e0 {
+		counter7: counter@APOLLO3_CTIMER7 {
 			compatible = "ambiq,counter";
-			reg = <0x400080E0 0x20>;
-			interrupts = <14 0>;
+			reg = <APOLLO3_CTIMER7_BASE APOLLO3_CTIMER7_SIZE>;
+			interrupts = <APOLLO3_CTIMER_IRQ 0>;
 			clock-frequency = <DT_FREQ_M(3)>;
 			clk-source = <2>;
 			status = "disabled";
 		};
 
-		uart0: uart@4001c000 {
+		uart0: uart@APOLLO3_UART0 {
 			compatible = "ambiq,uart", "arm,pl011";
-			reg = <0x4001c000 0x1000>;
-			interrupts = <15 0>;
+			reg = <APOLLO3_UART0_BASE APOLLO3_UART0_SIZE>;
+			interrupts = <APOLLO3_UART0_IRQ 0>;
 			interrupt-names = "UART0";
 			status = "disabled";
 			clocks = <&uartclk>;
@@ -186,10 +187,10 @@
 			zephyr,pm-device-runtime-auto;
 		};
 
-		uart1: uart@4001d000 {
+		uart1: uart@APOLLO3_UART1 {
 			compatible = "ambiq,uart", "arm,pl011";
-			reg = <0x4001d000 0x1000>;
-			interrupts = <16 0>;
+			reg = <APOLLO3_UART1_BASE APOLLO3_UART1_SIZE>;
+			interrupts = <APOLLO3_UART1_IRQ 0>;
 			interrupt-names = "UART1";
 			status = "disabled";
 			clocks = <&uartclk>;
@@ -197,140 +198,140 @@
 			zephyr,pm-device-runtime-auto;
 		};
 
-		spid0: spi@50000100 {
+		spid0: spi@APOLLO3_IOS {
 			compatible = "ambiq,spid";
-			reg = <0x50000100 0x1000>;
+			reg = <APOLLO3_IOS_BASE APOLLO3_IOS_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <4 0>;
+			interrupts = <APOLLO3_IOSLAVE_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		spi0: spi@50004000 {
-			reg = <0x50004000 0x1000>;
+		spi0: spi@APOLLO3_IOM0 {
+			reg = <APOLLO3_IOM0_BASE APOLLO3_IOM0_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <6 0>;
+			interrupts = <APOLLO3_IOMSTR0_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		spi1: spi@50005000 {
-			reg = <0x50005000 0x1000>;
+		spi1: spi@APOLLO3_IOM1 {
+			reg = <APOLLO3_IOM1_BASE APOLLO3_IOM1_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <7 0>;
+			interrupts = <APOLLO3_IOMSTR1_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		spi2: spi@50006000 {
-			reg = <0x50006000 0x1000>;
+		spi2: spi@APOLLO3_IOM2 {
+			reg = <APOLLO3_IOM2_BASE APOLLO3_IOM2_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <8 0>;
+			interrupts = <APOLLO3_IOMSTR2_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		spi3: spi@50007000 {
-			reg = <0x50007000 0x1000>;
+		spi3: spi@APOLLO3_IOM3 {
+			reg = <APOLLO3_IOM3_BASE APOLLO3_IOM3_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <9 0>;
+			interrupts = <APOLLO3_IOMSTR3_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		spi4: spi@50008000 {
-			reg = <0x50008000 0x1000>;
+		spi4: spi@APOLLO3_IOM4 {
+			reg = <APOLLO3_IOM4_BASE APOLLO3_IOM4_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <10 0>;
+			interrupts = <APOLLO3_IOMSTR4_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		spi5: spi@50009000 {
-			reg = <0x50009000 0x1000>;
+		spi5: spi@APOLLO3_IOM5 {
+			reg = <APOLLO3_IOM5_BASE APOLLO3_IOM5_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <11 0>;
+			interrupts = <APOLLO3_IOMSTR5_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		i2c0: i2c@50004000 {
-			reg = <0x50004000 0x1000>;
+		i2c0: i2c@APOLLO3_IOM0 {
+			reg = <APOLLO3_IOM0_BASE APOLLO3_IOM0_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <6 0>;
+			interrupts = <APOLLO3_IOMSTR0_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		i2c1: i2c@50005000 {
-			reg = <0x50005000 0x1000>;
+		i2c1: i2c@APOLLO3_IOM1 {
+			reg = <APOLLO3_IOM1_BASE APOLLO3_IOM1_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <7 0>;
+			interrupts = <APOLLO3_IOMSTR1_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		i2c2: i2c@50006000 {
-			reg = <0x50006000 0x1000>;
+		i2c2: i2c@APOLLO3_IOM2 {
+			reg = <APOLLO3_IOM2_BASE APOLLO3_IOM2_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <8 0>;
+			interrupts = <APOLLO3_IOMSTR2_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		i2c3: i2c@50007000 {
-			reg = <0x50007000 0x1000>;
+		i2c3: i2c@APOLLO3_IOM3 {
+			reg = <APOLLO3_IOM3_BASE APOLLO3_IOM3_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <9 0>;
+			interrupts = <APOLLO3_IOMSTR3_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		i2c4: i2c@50008000 {
-			reg = <0x50008000 0x1000>;
+		i2c4: i2c@APOLLO3_IOM4 {
+			reg = <APOLLO3_IOM4_BASE APOLLO3_IOM4_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <10 0>;
+			interrupts = <APOLLO3_IOMSTR4_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		i2c5: i2c@50009000 {
-			reg = <0x50009000 0x1000>;
+		i2c5: i2c@APOLLO3_IOM5 {
+			reg = <APOLLO3_IOM5_BASE APOLLO3_IOM5_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <11 0>;
+			interrupts = <APOLLO3_IOMSTR5_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		adc0: adc@50010000 {
-			reg = <0x50010000 0x400>;
-			interrupts = <18 0>;
+		adc0: adc@APOLLO3_ADC {
+			reg = <APOLLO3_ADC_BASE APOLLO3_ADC_SIZE>;
+			interrupts = <APOLLO3_ADC_IRQ 0>;
 			interrupt-names = "ADC";
 			channel-count = <10>;
 			internal-vref-mv = <1500>;
@@ -339,28 +340,28 @@
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x200>;
 		};
 
-		mspi0: spi@40020000 {
+		mspi0: spi@APOLLO3_MSPI {
 			compatible = "ambiq,mspi";
-			reg = <0x40020000 0x400>;
-			interrupts = <20 0>;
+			reg = <APOLLO3_MSPI_BASE APOLLO3_MSPI_SIZE>;
+			interrupts = <APOLLO3_MSPI0_IRQ 0>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x800>;
 		};
 
-		rtc0: rtc@40004240 {
+		rtc0: rtc@APOLLO3_RTC {
 			compatible = "ambiq,rtc";
-			reg = <0x40004240 0xD0>;
-			interrupts = <2 0>;
+			reg = <APOLLO3_RTC_BASE APOLLO3_RTC_SIZE>;
+			interrupts = <APOLLO3_RTC_IRQ 0>;
 			alarms-count = <1>;
 			status = "disabled";
 		};
 
-		bleif: spi@5000c000 {
+		bleif: spi@APOLLO3_BLEIF {
 			compatible = "ambiq,spi-bleif";
-			reg = <0x5000c000 0x414>;
-			interrupts = <12 1>;
+			reg = <APOLLO3_BLEIF_BASE APOLLO3_BLEIF_SIZE>;
+			interrupts = <APOLLO3_BLE_IRQ 1>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
@@ -373,13 +374,13 @@
 			};
 		};
 
-		pinctrl: pin-controller@40010000 {
+		pinctrl: pin-controller@APOLLO3_GPIO {
 			compatible = "ambiq,apollo3-pinctrl";
-			reg = <0x40010000 0x800>;
+			reg = <APOLLO3_GPIO_BASE APOLLO3_GPIO_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 
-			gpio: gpio@40010000 {
+			gpio: gpio@APOLLO3_GPIO {
 				compatible = "ambiq,gpio";
 				gpio-map-mask = <0xffffffe0 0xffffffc0>;
 				gpio-map-pass-thru = <0x1f 0x3f>;
@@ -387,7 +388,7 @@
 					0x00 0x0 &gpio0_31 0x0 0x0
 					0x20 0x0 &gpio32_63 0x0 0x0
 				>;
-				reg = <0x40010000>;
+				reg = <APOLLO3_GPIO_BASE>;
 				#gpio-cells = <2>;
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -398,7 +399,7 @@
 					gpio-controller;
 					#gpio-cells = <2>;
 					reg = <0>;
-					interrupts = <13 0>;
+					interrupts = <APOLLO3_GPIO_IRQ 0>;
 					status = "disabled";
 				};
 
@@ -407,17 +408,17 @@
 					gpio-controller;
 					#gpio-cells = <2>;
 					reg = <0x20>;
-					interrupts = <13 0>;
+					interrupts = <APOLLO3_GPIO_IRQ 0>;
 					status = "disabled";
 					ngpios = <18>;
 				};
 			};
 		};
 
-		wdt0: watchdog@40024000 {
+		wdt0: watchdog@APOLLO3_WDT {
 			compatible = "ambiq,watchdog";
-			reg = <0x40024000 0x400>;
-			interrupts = <1 0>;
+			reg = <APOLLO3_WDT_BASE APOLLO3_WDT_SIZE>;
+			interrupts = <APOLLO3_WDT_IRQ 0>;
 			clock-frequency = <16>;
 			status = "disabled";
 		};
diff --git a/dts/arm/ambiq/ambiq_apollo3p_blue.dtsi b/dts/arm/ambiq/ambiq_apollo3p_blue.dtsi
index 9679e8787418b6..a28e4e45abbcba 100644
--- a/dts/arm/ambiq/ambiq_apollo3p_blue.dtsi
+++ b/dts/arm/ambiq/ambiq_apollo3p_blue.dtsi
@@ -3,6 +3,7 @@
 #include <arm/armv7-m.dtsi>
 #include <mem.h>
 #include <freq.h>
+#include <apollo3p/am_apollo3p.h>
 #include <zephyr/dt-bindings/adc/adc.h>
 #include <zephyr/dt-bindings/i2c/i2c.h>
 #include <zephyr/dt-bindings/gpio/gpio.h>
@@ -61,142 +62,142 @@
 	};
 
 	/* TCM */
-	tcm: tcm@10000000 {
+	tcm: tcm@APOLLO3P_TCM {
 		compatible = "zephyr,memory-region";
-		reg = <0x10000000 0x10000>;
+		reg = <APOLLO3P_TCM_BASE APOLLO3P_TCM_SIZE>;
 		zephyr,memory-region = "ITCM";
 	};
 
 	/* SRAM */
-	sram0: memory@10010000 {
+	sram0: memory@APOLLO3P_SRAM {
 		compatible = "mmio-sram";
-		reg = <0x10010000 0xB0000>;
+		reg = <APOLLO3P_SRAM_BASE APOLLO3P_SRAM_SIZE>;
 	};
 
-	xip0: memory@52000000 {
+	xip0: memory@APOLLO3P_MSPI0_XIPMM_APERTURE {
 		compatible = "zephyr,memory-region";
-		reg = <0x52000000 0x2000000>;
+		reg = <APOLLO3P_MSPI0_XIPMM_APERTURE_BASE APOLLO3P_MSPI0_XIPMM_APERTURE_SIZE>;
 		zephyr,memory-region = "XIP0";
 	};
 
-	xip1: memory@54000000 {
+	xip1: memory@APOLLO3P_MSPI1_XIPMM_APERTURE {
 		compatible = "zephyr,memory-region";
-		reg = <0x54000000 0x2000000>;
+		reg = <APOLLO3P_MSPI1_XIPMM_APERTURE_BASE APOLLO3P_MSPI1_XIPMM_APERTURE_SIZE>;
 		zephyr,memory-region = "XIP1";
 	};
 
-	xip2: memory@56000000 {
+	xip2: memory@APOLLO3P_MSPI2_XIPMM_APERTURE {
 		compatible = "zephyr,memory-region";
-		reg = <0x56000000 0x2000000>;
+		reg = <APOLLO3P_MSPI2_XIPMM_APERTURE_BASE APOLLO3P_MSPI2_XIPMM_APERTURE_SIZE>;
 		zephyr,memory-region = "XIP2";
 	};
 
 	soc {
 		compatible = "ambiq,apollo3p-blue", "ambiq,apollo3x", "simple-bus";
 
-		flash: flash-controller@c000 {
+		flash: flash-controller@APOLLO3P_FLASH {
 			compatible = "ambiq,flash-controller";
-			reg = <0x0000c000 0x1f4000>;
+			reg = <APOLLO3P_FLASH_BASE APOLLO3P_FLASH_SIZE>;
 
 			#address-cells = <1>;
 			#size-cells = <1>;
 
 			/* Flash region */
-			flash0: flash@c000 {
+			flash0: flash@APOLLO3P_FLASH {
 				compatible = "soc-nv-flash";
-				reg = <0x0000c000 0x1f4000>;
+				reg = <APOLLO3P_FLASH_BASE APOLLO3P_FLASH_SIZE>;
 			};
 		};
 
-		pwrcfg: pwrcfg@40021000 {
+		pwrcfg: pwrcfg@APOLLO3P_PWRCTRL {
 			compatible = "ambiq,pwrctrl";
-			reg = <0x40021000 0x400>;
+			reg = <APOLLO3P_PWRCTRL_BASE APOLLO3P_PWRCTRL_SIZE>;
 			#pwrcfg-cells = <2>;
 		};
 
-		stimer0: stimer@40008140 {
+		stimer0: stimer@APOLLO3P_STIMER {
 			compatible = "ambiq,stimer";
-			reg = <0x40008140 0x80>;
-			interrupts = <23 0>;
+			reg = <APOLLO3P_STIMER_BASE APOLLO3P_STIMER_SIZE>;
+			interrupts = <APOLLO3P_STIMER_CMPR0_IRQ 0>;
 			status = "okay";
 		};
 
-		counter0: counter@40008000 {
+		counter0: counter@APOLLO3P_CTIMER0 {
 			compatible = "ambiq,counter";
-			reg = <0x40008000 0x20>;
-			interrupts = <14 0>;
+			reg = <APOLLO3P_CTIMER0_BASE APOLLO3P_CTIMER0_SIZE>;
+			interrupts = <APOLLO3P_CTIMER_IRQ 0>;
 			clock-frequency = <DT_FREQ_M(3)>;
 			clk-source = <2>;
 			status = "disabled";
 		};
 
-		counter1: counter@40008020 {
+		counter1: counter@APOLLO3P_CTIMER1 {
 			compatible = "ambiq,counter";
-			reg = <0x40008020 0x20>;
-			interrupts = <14 0>;
+			reg = <APOLLO3P_CTIMER1_BASE APOLLO3P_CTIMER1_SIZE>;
+			interrupts = <APOLLO3P_CTIMER_IRQ 0>;
 			clock-frequency = <DT_FREQ_M(3)>;
 			clk-source = <2>;
 			status = "disabled";
 		};
 
-		counter2: counter@40008040 {
+		counter2: counter@APOLLO3P_CTIMER2 {
 			compatible = "ambiq,counter";
-			reg = <0x40008040 0x20>;
-			interrupts = <14 0>;
+			reg = <APOLLO3P_CTIMER2_BASE APOLLO3P_CTIMER2_SIZE>;
+			interrupts = <APOLLO3P_CTIMER_IRQ 0>;
 			clock-frequency = <DT_FREQ_M(3)>;
 			clk-source = <2>;
 			status = "disabled";
 		};
 
-		counter3: counter@40008060 {
+		counter3: counter@APOLLO3P_CTIMER3 {
 			compatible = "ambiq,counter";
-			reg = <0x40008060 0x20>;
-			interrupts = <14 0>;
+			reg = <APOLLO3P_CTIMER3_BASE APOLLO3P_CTIMER3_SIZE>;
+			interrupts = <APOLLO3P_CTIMER_IRQ 0>;
 			clock-frequency = <DT_FREQ_M(3)>;
 			clk-source = <2>;
 			status = "disabled";
 		};
 
-		counter4: counter@40008080 {
+		counter4: counter@APOLLO3P_CTIMER4 {
 			compatible = "ambiq,counter";
-			reg = <0x40008080 0x20>;
-			interrupts = <14 0>;
+			reg = <APOLLO3P_CTIMER4_BASE APOLLO3P_CTIMER4_SIZE>;
+			interrupts = <APOLLO3P_CTIMER_IRQ 0>;
 			clock-frequency = <DT_FREQ_M(3)>;
 			clk-source = <2>;
 			status = "disabled";
 		};
 
-		counter5: counter@400080a0 {
+		counter5: counter@APOLLO3P_CTIMER5 {
 			compatible = "ambiq,counter";
-			reg = <0x400080A0 0x20>;
-			interrupts = <14 0>;
+			reg = <APOLLO3P_CTIMER5_BASE APOLLO3P_CTIMER5_SIZE>;
+			interrupts = <APOLLO3P_CTIMER_IRQ 0>;
 			clock-frequency = <DT_FREQ_M(3)>;
 			clk-source = <2>;
 			status = "disabled";
 		};
 
-		counter6: counter@400080c0 {
+		counter6: counter@APOLLO3P_CTIMER6 {
 			compatible = "ambiq,counter";
-			reg = <0x400080C0 0x20>;
-			interrupts = <14 0>;
+			reg = <APOLLO3P_CTIMER6_BASE APOLLO3P_CTIMER6_SIZE>;
+			interrupts = <APOLLO3P_CTIMER_IRQ 0>;
 			clock-frequency = <DT_FREQ_M(3)>;
 			clk-source = <2>;
 			status = "disabled";
 		};
 
-		counter7: counter@400080e0 {
+		counter7: counter@APOLLO3P_CTIMER7 {
 			compatible = "ambiq,counter";
-			reg = <0x400080E0 0x20>;
-			interrupts = <14 0>;
+			reg = <APOLLO3P_CTIMER7_BASE APOLLO3P_CTIMER7_SIZE>;
+			interrupts = <APOLLO3P_CTIMER_IRQ 0>;
 			clock-frequency = <DT_FREQ_M(3)>;
 			clk-source = <2>;
 			status = "disabled";
 		};
 
-		uart0: uart@4001c000 {
+		uart0: uart@APOLLO3P_UART0 {
 			compatible = "ambiq,uart", "arm,pl011";
-			reg = <0x4001c000 0x1000>;
-			interrupts = <15 0>;
+			reg = <APOLLO3P_UART0_BASE APOLLO3P_UART0_SIZE>;
+			interrupts = <APOLLO3P_UART0_IRQ 0>;
 			interrupt-names = "UART0";
 			status = "disabled";
 			clocks = <&uartclk>;
@@ -204,10 +205,10 @@
 			zephyr,pm-device-runtime-auto;
 		};
 
-		uart1: uart@4001d000 {
+		uart1: uart@APOLLO3P_UART1 {
 			compatible = "ambiq,uart", "arm,pl011";
-			reg = <0x4001d000 0x1000>;
-			interrupts = <16 0>;
+			reg = <APOLLO3P_UART1_BASE APOLLO3P_UART1_SIZE>;
+			interrupts = <APOLLO3P_UART1_IRQ 0>;
 			interrupt-names = "UART1";
 			status = "disabled";
 			clocks = <&uartclk>;
@@ -215,140 +216,140 @@
 			zephyr,pm-device-runtime-auto;
 		};
 
-		spid0: spi@50000100 {
+		spid0: spi@APOLLO3P_IOS {
 			compatible = "ambiq,spid";
-			reg = <0x50000100 0x1000>;
+			reg = <APOLLO3P_IOS_BASE APOLLO3P_IOS_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <4 0>;
+			interrupts = <APOLLO3P_IOSLAVE_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		spi0: spi@50004000 {
-			reg = <0x50004000 0x1000>;
+		spi0: spi@APOLLO3P_IOM0 {
+			reg = <APOLLO3P_IOM0_BASE APOLLO3P_IOM0_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <6 0>;
+			interrupts = <APOLLO3P_IOMSTR0_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		spi1: spi@50005000 {
-			reg = <0x50005000 0x1000>;
+		spi1: spi@APOLLO3P_IOM1 {
+			reg = <APOLLO3P_IOM1_BASE APOLLO3P_IOM1_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <7 0>;
+			interrupts = <APOLLO3P_IOMSTR1_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		spi2: spi@50006000 {
-			reg = <0x50006000 0x1000>;
+		spi2: spi@APOLLO3P_IOM2 {
+			reg = <APOLLO3P_IOM2_BASE APOLLO3P_IOM2_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <8 0>;
+			interrupts = <APOLLO3P_IOMSTR2_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		spi3: spi@50007000 {
-			reg = <0x50007000 0x1000>;
+		spi3: spi@APOLLO3P_IOM3 {
+			reg = <APOLLO3P_IOM3_BASE APOLLO3P_IOM3_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <9 0>;
+			interrupts = <APOLLO3P_IOMSTR3_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		spi4: spi@50008000 {
-			reg = <0x50008000 0x1000>;
+		spi4: spi@APOLLO3P_IOM4 {
+			reg = <APOLLO3P_IOM4_BASE APOLLO3P_IOM4_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <10 0>;
+			interrupts = <APOLLO3P_IOMSTR4_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		spi5: spi@50009000 {
-			reg = <0x50009000 0x1000>;
+		spi5: spi@APOLLO3P_IOM5 {
+			reg = <APOLLO3P_IOM5_BASE APOLLO3P_IOM5_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <11 0>;
+			interrupts = <APOLLO3P_IOMSTR5_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		i2c0: i2c@50004000 {
-			reg = <0x50004000 0x1000>;
+		i2c0: i2c@APOLLO3P_IOM0 {
+			reg = <APOLLO3P_IOM0_BASE APOLLO3P_IOM0_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <6 0>;
+			interrupts = <APOLLO3P_IOMSTR0_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		i2c1: i2c@50005000 {
-			reg = <0x50005000 0x1000>;
+		i2c1: i2c@APOLLO3P_IOM1 {
+			reg = <APOLLO3P_IOM1_BASE APOLLO3P_IOM1_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <7 0>;
+			interrupts = <APOLLO3P_IOMSTR1_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		i2c2: i2c@50006000 {
-			reg = <0x50006000 0x1000>;
+		i2c2: i2c@APOLLO3P_IOM2 {
+			reg = <APOLLO3P_IOM2_BASE APOLLO3P_IOM2_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <8 0>;
+			interrupts = <APOLLO3P_IOMSTR2_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		i2c3: i2c@50007000 {
-			reg = <0x50007000 0x1000>;
+		i2c3: i2c@APOLLO3P_IOM3 {
+			reg = <APOLLO3P_IOM3_BASE APOLLO3P_IOM3_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <9 0>;
+			interrupts = <APOLLO3P_IOMSTR3_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		i2c4: i2c@50008000 {
-			reg = <0x50008000 0x1000>;
+		i2c4: i2c@APOLLO3P_IOM4 {
+			reg = <APOLLO3P_IOM4_BASE APOLLO3P_IOM4_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <10 0>;
+			interrupts = <APOLLO3P_IOMSTR4_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		i2c5: i2c@50009000 {
-			reg = <0x50009000 0x1000>;
+		i2c5: i2c@APOLLO3P_IOM5 {
+			reg = <APOLLO3P_IOM5_BASE APOLLO3P_IOM5_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <11 0>;
+			interrupts = <APOLLO3P_IOMSTR5_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		adc0: adc@50010000 {
-			reg = <0x50010000 0x400>;
-			interrupts = <18 0>;
+		adc0: adc@APOLLO3P_ADC {
+			reg = <APOLLO3P_ADC_BASE APOLLO3P_ADC_SIZE>;
+			interrupts = <APOLLO3P_ADC_IRQ 0>;
 			interrupt-names = "ADC";
 			channel-count = <10>;
 			internal-vref-mv = <1500>;
@@ -357,51 +358,51 @@
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x200>;
 		};
 
-		mspi0: mspi@50014000 {
+		mspi0: mspi@APOLLO3P_MSPI0 {
 			compatible = "ambiq,mspi-controller";
-			reg = <0x50014000 0x400>,<0x52000000 0x2000000>;
+			reg = <APOLLO3P_MSPI0_BASE APOLLO3P_MSPI0_SIZE>,<APOLLO3P_MSPI0_XIPMM_APERTURE_BASE APOLLO3P_MSPI0_XIPMM_APERTURE_SIZE>;
 			clock-frequency = <48000000>;
-			interrupts = <20 0>;
+			interrupts = <APOLLO3P_MSPI0_IRQ 0>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x800>;
 		};
 
-		mspi1: mspi@50015000 {
+		mspi1: mspi@APOLLO3P_MSPI1 {
 			compatible = "ambiq,mspi-controller";
-			reg = <0x50015000 0x400>,<0x54000000 0x2000000>;
+			reg = <APOLLO3P_MSPI1_BASE APOLLO3P_MSPI1_SIZE>,<APOLLO3P_MSPI1_XIPMM_APERTURE_BASE APOLLO3P_MSPI1_XIPMM_APERTURE_SIZE>;
 			clock-frequency = <48000000>;
-			interrupts = <32 0>;
+			interrupts = <APOLLO3P_MSPI1_IRQ 0>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x1000>;
 		};
 
-		mspi2: mspi@50016000 {
+		mspi2: mspi@APOLLO3P_MSPI2 {
 			compatible = "ambiq,mspi-controller";
 			clock-frequency = <48000000>;
-			reg = <0x50016000 0x400>,<0x56000000 0x2000000>;
-			interrupts = <33 0>;
+			reg = <APOLLO3P_MSPI2_BASE APOLLO3P_MSPI2_SIZE>,<APOLLO3P_MSPI2_XIPMM_APERTURE_BASE APOLLO3P_MSPI2_XIPMM_APERTURE_SIZE>;
+			interrupts = <APOLLO3P_MSPI2_IRQ 0>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x8 0x2000>;
 		};
 
-		rtc0: rtc@40004240 {
+		rtc0: rtc@APOLLO3P_RTC {
 			compatible = "ambiq,rtc";
-			reg = <0x40004240 0xD0>;
-			interrupts = <2 0>;
+			reg = <APOLLO3P_RTC_BASE APOLLO3P_RTC_SIZE>;
+			interrupts = <APOLLO3P_RTC_IRQ 0>;
 			alarms-count = <1>;
 			status = "disabled";
 		};
 
-		bleif: spi@5000c000 {
+		bleif: spi@APOLLO3P_BLEIF {
 			compatible = "ambiq,spi-bleif";
-			reg = <0x5000c000 0x414>;
-			interrupts = <12 1>;
+			reg = <APOLLO3P_BLEIF_BASE APOLLO3P_BLEIF_SIZE>;
+			interrupts = <APOLLO3P_BLE_IRQ 1>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
@@ -414,13 +415,13 @@
 			};
 		};
 
-		pinctrl: pin-controller@40010000 {
+		pinctrl: pin-controller@APOLLO3P_GPIO {
 			compatible = "ambiq,apollo3-pinctrl";
-			reg = <0x40010000 0x800>;
+			reg = <APOLLO3P_GPIO_BASE APOLLO3P_GPIO_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 
-			gpio: gpio@40010000 {
+			gpio: gpio@APOLLO3P_GPIO {
 				compatible = "ambiq,gpio";
 				gpio-map-mask = <0xffffffe0 0xffffffc0>;
 				gpio-map-pass-thru = <0x1f 0x3f>;
@@ -429,7 +430,7 @@
 					0x20 0x0 &gpio32_63 0x0 0x0
 					0x40 0x0 &gpio64_95 0x0 0x0
 				>;
-				reg = <0x40010000>;
+				reg = <APOLLO3P_GPIO_BASE>;
 				#gpio-cells = <2>;
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -440,7 +441,7 @@
 					gpio-controller;
 					#gpio-cells = <2>;
 					reg = <0>;
-					interrupts = <13 0>;
+					interrupts = <APOLLO3P_GPIO_IRQ 0>;
 					status = "disabled";
 				};
 
@@ -449,7 +450,7 @@
 					gpio-controller;
 					#gpio-cells = <2>;
 					reg = <0x20>;
-					interrupts = <13 0>;
+					interrupts = <APOLLO3P_GPIO_IRQ 0>;
 					status = "disabled";
 				};
 
@@ -458,17 +459,17 @@
 					gpio-controller;
 					#gpio-cells = <2>;
 					reg = <0x40>;
-					interrupts = <13 0>;
+					interrupts = <APOLLO3P_GPIO_IRQ 0>;
 					status = "disabled";
 					ngpios = <10>;
 				};
 			};
 		};
 
-		wdt0: watchdog@40024000 {
+		wdt0: watchdog@APOLLO3P_WDT {
 			compatible = "ambiq,watchdog";
-			reg = <0x40024000 0x400>;
-			interrupts = <1 0>;
+			reg = <APOLLO3P_WDT_BASE APOLLO3P_WDT_SIZE>;
+			interrupts = <APOLLO3P_WDT_IRQ 0>;
 			clock-frequency = <16>;
 			status = "disabled";
 		};
diff --git a/dts/arm/ambiq/ambiq_apollo4p.dtsi b/dts/arm/ambiq/ambiq_apollo4p.dtsi
index c5641cfd352dca..d56a6568d8fb7f 100644
--- a/dts/arm/ambiq/ambiq_apollo4p.dtsi
+++ b/dts/arm/ambiq/ambiq_apollo4p.dtsi
@@ -3,6 +3,7 @@
 #include <arm/armv7-m.dtsi>
 #include <mem.h>
 #include <freq.h>
+#include <apollo4p/am_apollo4p.h>
 #include <zephyr/dt-bindings/adc/adc.h>
 #include <zephyr/dt-bindings/i2c/i2c.h>
 #include <zephyr/dt-bindings/gpio/gpio.h>
@@ -63,243 +64,243 @@
 	};
 
 	/* TCM */
-	tcm: tcm@10000000 {
+	tcm: tcm@APOLLO4P_TCM {
 		compatible = "zephyr,memory-region";
-		reg = <0x10000000 0x10000>;
+		reg = <APOLLO4P_TCM_BASE APOLLO4P_TCM_SIZE>;
 		zephyr,memory-region = "ITCM";
 	};
 
 	/* SRAM */
-	sram0: memory@10010000 {
+	sram0: memory@APOLLO4P_SRAM0 {
 		compatible = "mmio-sram";
-		reg = <0x10010000 0x2B0000>;
+		reg = <APOLLO4P_SRAM0_BASE APOLLO4P_SRAM0_SIZE>;
 	};
 
 	soc {
 		compatible = "ambiq,apollo4p", "ambiq,apollo4x", "simple-bus";
 
-		flash: flash-controller@18000 {
+		flash: flash-controller@APOLLO4P_FLASH {
 			compatible = "ambiq,flash-controller";
-			reg = <0x00018000 0x1e8000>;
+			reg = <APOLLO4P_FLASH_BASE APOLLO4P_FLASH_SIZE>;
 
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			/* Flash region */
-			flash0: flash@18000 {
+			/* MRAM region */
+			flash0: flash@APOLLO4P_FLASH {
 				compatible = "soc-nv-flash";
-				reg = <0x00018000 0x1e8000>;
+				reg = <APOLLO4P_FLASH_BASE APOLLO4P_FLASH_SIZE>;
 			};
 		};
 
-		pwrcfg: pwrcfg@40021000 {
+		pwrcfg: pwrcfg@APOLLO4P_PWRCTRL {
 			compatible = "ambiq,pwrctrl";
-			reg = <0x40021000 0x400>;
+			reg = <APOLLO4P_PWRCTRL_BASE APOLLO4P_PWRCTRL_SIZE>;
 			#pwrcfg-cells = <2>;
 		};
 
-		stimer0: stimer@40008800 {
+		stimer0: stimer@APOLLO4P_STIMER {
 			compatible = "ambiq,stimer";
-			reg = <0x40008800 0x80>;
-			interrupts = <32 0>;
+			reg = <APOLLO4P_STIMER_BASE APOLLO4P_STIMER_SIZE>;
+			interrupts = <APOLLO4P_STIMER_CMPR0_IRQ 0>;
 			status = "okay";
 		};
 
-		counter0: counter@40008200 {
+		counter0: counter@APOLLO4P_TIMER0 {
 			compatible = "ambiq,counter";
-			reg = <0x40008200 0x20>;
-			interrupts = <67 0>;
+			reg = <APOLLO4P_TIMER0_BASE APOLLO4P_TIMER0_SIZE>;
+			interrupts = <APOLLO4P_TIMER0_IRQ 0>;
 			clock-frequency = <DT_FREQ_M(6)>;
 			clk-source = <1>;
 			status = "disabled";
 		};
 
-		uart0: uart@4001c000 {
+		uart0: uart@APOLLO4P_UART0 {
 			compatible = "ambiq,uart", "arm,pl011";
-			reg = <0x4001c000 0x1000>;
-			interrupts = <15 0>;
+			reg = <APOLLO4P_UART0_BASE APOLLO4P_UART0_SIZE>;
+			interrupts = <APOLLO4P_UART0_IRQ 0>;
 			interrupt-names = "UART0";
 			status = "disabled";
 			clocks = <&uartclk>;
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x200>;
 		};
-		uart1: uart@4001d000 {
+		uart1: uart@APOLLO4P_UART1 {
 			compatible = "ambiq,uart", "arm,pl011";
-			reg = <0x4001d000 0x1000>;
-			interrupts = <16 0>;
+			reg = <APOLLO4P_UART1_BASE APOLLO4P_UART1_SIZE>;
+			interrupts = <APOLLO4P_UART1_IRQ 0>;
 			interrupt-names = "UART1";
 			status = "disabled";
 			clocks = <&uartclk>;
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x400>;
 		};
 
-		uart2: uart@4001e000 {
+		uart2: uart@APOLLO4P_UART2 {
 			compatible = "ambiq,uart", "arm,pl011";
-			reg = <0x4001e000 0x1000>;
-			interrupts = <17 0>;
+			reg = <APOLLO4P_UART2_BASE APOLLO4P_UART2_SIZE>;
+			interrupts = <APOLLO4P_UART2_IRQ 0>;
 			interrupt-names = "UART2";
 			status = "disabled";
 			clocks = <&uartclk>;
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x800>;
 		};
 
-		uart3: uart@4001f000 {
+		uart3: uart@APOLLO4P_UART3 {
 			compatible = "ambiq,uart", "arm,pl011";
-			reg = <0x4001f000 0x1000>;
-			interrupts = <18 0>;
+			reg = <APOLLO4P_UART3_BASE APOLLO4P_UART3_SIZE>;
+			interrupts = <APOLLO4P_UART3_IRQ 0>;
 			interrupt-names = "UART3";
 			status = "disabled";
 			clocks = <&uartclk>;
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x1000>;
 		};
 
-		iom0_spi: spi@40050000 {
-			reg = <0x40050000 0x1000>;
+		spi0: spi@APOLLO4P_IOM0 {
+			reg = <APOLLO4P_IOM0_BASE APOLLO4P_IOM0_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <6 0>;
+			interrupts = <APOLLO4P_IOMSTR0_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x2>;
 		};
 
-		iom0_i2c: i2c@40050000 {
-			reg = <0x40050000 0x1000>;
+		i2c0: i2c@APOLLO4P_IOM0 {
+			reg = <APOLLO4P_IOM0_BASE APOLLO4P_IOM0_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <6 0>;
+			interrupts = <APOLLO4P_IOMSTR0_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x2>;
 		};
 
-		iom1_spi: spi@40051000 {
-			reg = <0x40051000 0x1000>;
+		spi1: spi@APOLLO4P_IOM1 {
+			reg = <APOLLO4P_IOM1_BASE APOLLO4P_IOM1_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <7 0>;
+			interrupts = <APOLLO4P_IOMSTR1_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x4>;
 		};
 
-		iom1_i2c: i2c@40051000 {
-			reg = <0x40051000 0x1000>;
+		i2c1: i2c@APOLLO4P_IOM1 {
+			reg = <APOLLO4P_IOM1_BASE APOLLO4P_IOM1_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <7 0>;
+			interrupts = <APOLLO4P_IOMSTR1_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x4>;
 		};
 
-		iom2_spi: spi@40052000 {
-			reg = <0x40052000 0x1000>;
+		spi2: spi@APOLLO4P_IOM2 {
+			reg = <APOLLO4P_IOM2_BASE APOLLO4P_IOM2_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <8 0>;
+			interrupts = <APOLLO4P_IOMSTR2_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x8>;
 		};
 
-		iom2_i2c: i2c@40052000 {
-			reg = <0x40052000 0x1000>;
+		i2c2: i2c@APOLLO4P_IOM2 {
+			reg = <APOLLO4P_IOM2_BASE APOLLO4P_IOM2_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <8 0>;
+			interrupts = <APOLLO4P_IOMSTR2_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x8>;
 		};
 
-		iom3_spi: spi@40053000 {
-			reg = <0x40053000 0x1000>;
+		spi3: spi@APOLLO4P_IOM3 {
+			reg = <APOLLO4P_IOM3_BASE APOLLO4P_IOM3_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <9 0>;
+			interrupts = <APOLLO4P_IOMSTR3_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x10>;
 		};
 
-		iom3_i2c: i2c@40053000 {
-			reg = <0x40053000 0x1000>;
+		i2c3: i2c@APOLLO4P_IOM3 {
+			reg = <APOLLO4P_IOM3_BASE APOLLO4P_IOM3_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <9 0>;
+			interrupts = <APOLLO4P_IOMSTR3_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x10>;
 		};
 
-		iom4_spi: spi@40054000 {
-			reg = <0x40054000 0x1000>;
+		spi4: spi@APOLLO4P_IOM4 {
+			reg = <APOLLO4P_IOM4_BASE APOLLO4P_IOM4_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <10 0>;
+			interrupts = <APOLLO4P_IOMSTR4_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x20>;
 		};
 
-		iom4_i2c: i2c@40054000 {
-			reg = <0x40054000 0x1000>;
+		i2c4: i2c@APOLLO4P_IOM4 {
+			reg = <APOLLO4P_IOM4_BASE APOLLO4P_IOM4_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <10 0>;
+			interrupts = <APOLLO4P_IOMSTR4_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x20>;
 		};
 
-		iom5_spi: spi@40055000 {
-			reg = <0x40055000 0x1000>;
+		spi5: spi@APOLLO4P_IOM5 {
+			reg = <APOLLO4P_IOM5_BASE APOLLO4P_IOM5_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <11 0>;
+			interrupts = <APOLLO4P_IOMSTR5_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x40>;
 		};
 
-		iom5_i2c: i2c@40055000 {
-			reg = <0x40055000 0x1000>;
+		i2c5: i2c@APOLLO4P_IOM5 {
+			reg = <APOLLO4P_IOM5_BASE APOLLO4P_IOM5_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <11 0>;
+			interrupts = <APOLLO4P_IOMSTR5_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x40>;
 		};
 
-		iom6_spi: spi@40056000 {
-			reg = <0x40056000 0x1000>;
+		spi6: spi@APOLLO4P_IOM6 {
+			reg = <APOLLO4P_IOM6_BASE APOLLO4P_IOM6_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <12 0>;
+			interrupts = <APOLLO4P_IOMSTR6_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x80>;
 		};
 
-		iom6_i2c: i2c@40056000 {
-			reg = <0x40056000 0x1000>;
+		i2c6: i2c@APOLLO4P_IOM6 {
+			reg = <APOLLO4P_IOM6_BASE APOLLO4P_IOM6_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <12 0>;
+			interrupts = <APOLLO4P_IOMSTR6_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x80>;
 		};
 
-		iom7_spi: spi@40057000 {
-			reg = <0x40057000 0x1000>;
+		spi7: spi@APOLLO4P_IOM7 {
+			reg = <APOLLO4P_IOM7_BASE APOLLO4P_IOM7_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <13 0>;
+			interrupts = <APOLLO4P_IOMSTR7_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x100>;
 		};
 
-		iom7_i2c: i2c@40057000 {
-			reg = <0x40057000 0x1000>;
+		i2c7: i2c@APOLLO4P_IOM7 {
+			reg = <APOLLO4P_IOM7_BASE APOLLO4P_IOM7_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <13 0>;
+			interrupts = <APOLLO4P_IOMSTR7_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x100>;
 		};
 
-		adc0: adc@40038000 {
-			reg = <0x40038000 0x400>;
-			interrupts = <19 0>;
+		adc0: adc@APOLLO4P_ADC {
+			reg = <APOLLO4P_ADC_BASE APOLLO4P_ADC_SIZE>;
+			interrupts = <APOLLO4P_ADC_IRQ 0>;
 			interrupt-names = "ADC";
 			channel-count = <10>;
 			internal-vref-mv = <1190>;
@@ -308,61 +309,61 @@
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x2000>;
 		};
 
-		mspi0: spi@40060000 {
+		mspi0: spi@APOLLO4P_MSPI0 {
 			compatible = "ambiq,mspi";
-			reg = <0x40060000 0x400>;
-			interrupts = <20 0>;
+			reg = <APOLLO4P_MSPI0_BASE APOLLO4P_MSPI0_SIZE>;
+			interrupts = <APOLLO4P_MSPI0_IRQ 0>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x4000>;
 		};
 
-		mspi1: spi@40061000 {
+		mspi1: spi@APOLLO4P_MSPI1 {
 			compatible = "ambiq,mspi";
-			reg = <0x40061000 0x400>;
-			interrupts = <21 0>;
+			reg = <APOLLO4P_MSPI1_BASE APOLLO4P_MSPI1_SIZE>;
+			interrupts = <APOLLO4P_MSPI1_IRQ 0>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x8000>;
 		};
 
-		mspi2: spi@40062000 {
+		mspi2: spi@APOLLO4P_MSPI2 {
 			compatible = "ambiq,mspi";
-			reg = <0x40062000 0x400>;
-			interrupts = <22 0>;
+			reg = <APOLLO4P_MSPI2_BASE APOLLO4P_MSPI2_SIZE>;
+			interrupts = <APOLLO4P_MSPI2_IRQ 0>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x10000>;
 		};
 
-		rtc0: rtc@40004800 {
+		rtc0: rtc@APOLLO4P_RTC {
 			compatible = "ambiq,rtc";
-			reg = <0x40004800 0x210>;
-			interrupts = <2 0>;
+			reg = <APOLLO4P_RTC_BASE APOLLO4P_RTC_SIZE>;
+			interrupts = <APOLLO4P_RTC_IRQ 0>;
 			alarms-count = <1>;
 			status = "disabled";
 		};
 
-		usb: usb@400b0000 {
+		usb: usb@APOLLO4P_USB {
 			compatible = "ambiq,usb";
-			reg = <0x400B0000 0x4100>;
-			interrupts = <27 0>;
+			reg = <APOLLO4P_USB_BASE APOLLO4P_USB_SIZE>;
+			interrupts = <APOLLO4P_USB_IRQ 0>;
 			num-bidir-endpoints = <6>;
 			maximum-speed = "full-speed";
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x400000>;
 		};
 
-		pinctrl: pin-controller@40010000 {
+		pinctrl: pin-controller@APOLLO4P_GPIO {
 			compatible = "ambiq,apollo4-pinctrl";
-			reg = <0x40010000 0x800>;
+			reg = <APOLLO4P_GPIO_BASE APOLLO4P_GPIO_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 
-			gpio: gpio@40010000 {
+			gpio: gpio@APOLLO4P_GPIO {
 				compatible = "ambiq,gpio";
 				gpio-map-mask = <0xffffffe0 0xffffffc0>;
 				gpio-map-pass-thru = <0x1f 0x3f>;
@@ -372,7 +373,7 @@
 					0x40 0x0 &gpio64_95 0x0 0x0
 					0x60 0x0 &gpio96_127 0x0 0x0
 				>;
-				reg = <0x40010000>;
+				reg = <APOLLO4P_GPIO_BASE>;
 				#gpio-cells = <2>;
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -383,7 +384,7 @@
 					gpio-controller;
 					#gpio-cells = <2>;
 					reg = <0>;
-					interrupts = <56 0>;
+					interrupts = <APOLLO4P_GPIO0_001F_IRQ 0>;
 					status = "disabled";
 				};
 
@@ -392,7 +393,7 @@
 					gpio-controller;
 					#gpio-cells = <2>;
 					reg = <0x80>;
-					interrupts = <57 0>;
+					interrupts = <APOLLO4P_GPIO0_203F_IRQ 0>;
 					status = "disabled";
 				};
 
@@ -401,7 +402,7 @@
 					gpio-controller;
 					#gpio-cells = <2>;
 					reg = <0x100>;
-					interrupts = <58 0>;
+					interrupts = <APOLLO4P_GPIO0_405F_IRQ 0>;
 					status = "disabled";
 				};
 
@@ -410,16 +411,16 @@
 					gpio-controller;
 					#gpio-cells = <2>;
 					reg = <0x180>;
-					interrupts = <59 0>;
+					interrupts = <APOLLO4P_GPIO0_607F_IRQ 0>;
 					status = "disabled";
 				};
 			};
 		};
 
-		wdt0: watchdog@40024000 {
+		wdt0: watchdog@APOLLO4P_WDT {
 			compatible = "ambiq,watchdog";
-			reg = <0x40024000 0x400>;
-			interrupts = <1 0>;
+			reg = <APOLLO4P_WDT_BASE APOLLO4P_WDT_SIZE>;
+			interrupts = <APOLLO4P_WDT_IRQ 0>;
 			clock-frequency = <16>;
 			status = "disabled";
 		};
diff --git a/dts/arm/ambiq/ambiq_apollo4p_blue.dtsi b/dts/arm/ambiq/ambiq_apollo4p_blue.dtsi
index 421e0dcb587d9b..339c56bb5cfa91 100644
--- a/dts/arm/ambiq/ambiq_apollo4p_blue.dtsi
+++ b/dts/arm/ambiq/ambiq_apollo4p_blue.dtsi
@@ -3,6 +3,7 @@
 #include <arm/armv7-m.dtsi>
 #include <mem.h>
 #include <freq.h>
+#include <apollo4p/am_apollo4p.h>
 #include <zephyr/dt-bindings/i2c/i2c.h>
 #include <zephyr/dt-bindings/gpio/gpio.h>
 
@@ -44,139 +45,139 @@
 	};
 
 	/* TCM */
-	tcm: tcm@10000000 {
+	tcm: tcm@APOLLO4P_TCM {
 		compatible = "zephyr,memory-region";
-		reg = <0x10000000 0x10000>;
+		reg = <APOLLO4P_TCM_BASE APOLLO4P_TCM_SIZE>;
 		zephyr,memory-region = "ITCM";
 	};
 
 	/* SRAM */
-	sram0: memory@10010000 {
+	sram0: memory@APOLLO4P_SRAM0 {
 		compatible = "mmio-sram";
-		reg = <0x10010000 0x2B0000>;
+		reg = <APOLLO4P_SRAM0_BASE APOLLO4P_SRAM0_SIZE>;
 	};
 
 	soc {
 		compatible = "ambiq,apollo4p-blue", "ambiq,apollo4x", "simple-bus";
 
-		flash: flash-controller@18000 {
+		flash: flash-controller@APOLLO4P_FLASH {
 			compatible = "ambiq,flash-controller";
-			reg = <0x00018000 0x1e8000>;
+			reg = <APOLLO4P_FLASH_BASE APOLLO4P_FLASH_SIZE>;
 
 			#address-cells = <1>;
 			#size-cells = <1>;
 
 			/* MRAM region */
-			flash0: flash@18000 {
+			flash0: flash@APOLLO4P_FLASH {
 				compatible = "soc-nv-flash";
-				reg = <0x00018000 0x1e8000>;
+				reg = <APOLLO4P_FLASH_BASE APOLLO4P_FLASH_SIZE>;
 			};
 		};
 
-		pwrcfg: pwrcfg@40021000 {
+		pwrcfg: pwrcfg@APOLLO4P_PWRCTRL {
 			compatible = "ambiq,pwrctrl";
-			reg = <0x40021000 0x400>;
+			reg = <APOLLO4P_PWRCTRL_BASE APOLLO4P_PWRCTRL_SIZE>;
 			#pwrcfg-cells = <2>;
 		};
 
-		stimer0: stimer@40008800 {
+		stimer0: stimer@APOLLO4P_STIMER {
 			compatible = "ambiq,stimer";
-			reg = <0x40008800 0x80>;
-			interrupts = <32 0>;
+			reg = <APOLLO4P_STIMER_BASE APOLLO4P_STIMER_SIZE>;
+			interrupts = <APOLLO4P_STIMER_CMPR0_IRQ 0>;
 			status = "okay";
 		};
 
-		counter0: counter@40008200 {
+		counter0: counter@APOLLO4P_TIMER0 {
 			compatible = "ambiq,counter";
-			reg = <0x40008200 0x20>;
-			interrupts = <67 0>;
+			reg = <APOLLO4P_TIMER0_BASE APOLLO4P_TIMER0_SIZE>;
+			interrupts = <APOLLO4P_TIMER0_IRQ 0>;
 			clock-frequency = <DT_FREQ_M(6)>;
 			clk-source = <1>;
 			status = "disabled";
 		};
 
-		uart0: uart@4001c000 {
+		uart0: uart@APOLLO4P_UART0 {
 			compatible = "ambiq,uart", "arm,pl011";
-			reg = <0x4001c000 0x1000>;
-			interrupts = <15 0>;
+			reg = <APOLLO4P_UART0_BASE APOLLO4P_UART0_SIZE>;
+			interrupts = <APOLLO4P_UART0_IRQ 0>;
 			interrupt-names = "UART0";
 			status = "disabled";
 			clocks = <&uartclk>;
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x200>;
 		};
-		uart1: uart@4001d000 {
+		uart1: uart@APOLLO4P_UART1 {
 			compatible = "ambiq,uart", "arm,pl011";
-			reg = <0x4001d000 0x1000>;
-			interrupts = <16 0>;
+			reg = <APOLLO4P_UART1_BASE APOLLO4P_UART1_SIZE>;
+			interrupts = <APOLLO4P_UART1_IRQ 0>;
 			interrupt-names = "UART1";
 			status = "disabled";
 			clocks = <&uartclk>;
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x400>;
 		};
 
-		uart2: uart@4001e000 {
+		uart2: uart@APOLLO4P_UART2 {
 			compatible = "ambiq,uart", "arm,pl011";
-			reg = <0x4001e000 0x1000>;
-			interrupts = <17 0>;
+			reg = <APOLLO4P_UART2_BASE APOLLO4P_UART2_SIZE>;
+			interrupts = <APOLLO4P_UART2_IRQ 0>;
 			interrupt-names = "UART2";
 			status = "disabled";
 			clocks = <&uartclk>;
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x800>;
 		};
 
-		uart3: uart@4001f000 {
+		uart3: uart@APOLLO4P_UART3 {
 			compatible = "ambiq,uart", "arm,pl011";
-			reg = <0x4001f000 0x1000>;
-			interrupts = <18 0>;
+			reg = <APOLLO4P_UART3_BASE APOLLO4P_UART3_SIZE>;
+			interrupts = <APOLLO4P_UART3_IRQ 0>;
 			interrupt-names = "UART3";
 			status = "disabled";
 			clocks = <&uartclk>;
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x1000>;
 		};
 
-		spi0: spi@40050000 {
-			reg = <0x40050000 0x1000>;
+		spi0: spi@APOLLO4P_IOM0 {
+			reg = <APOLLO4P_IOM0_BASE APOLLO4P_IOM0_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <6 0>;
+			interrupts = <APOLLO4P_IOMSTR0_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x2>;
 		};
 
-		spi1: spi@40051000 {
-			reg = <0x40051000 0x1000>;
+		spi1: spi@APOLLO4P_IOM1 {
+			reg = <APOLLO4P_IOM1_BASE APOLLO4P_IOM1_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <7 0>;
+			interrupts = <APOLLO4P_IOMSTR1_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x4>;
 		};
 
-		spi2: spi@40052000 {
-			reg = <0x40052000 0x1000>;
+		spi2: spi@APOLLO4P_IOM2 {
+			reg = <APOLLO4P_IOM2_BASE APOLLO4P_IOM2_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <8 0>;
+			interrupts = <APOLLO4P_IOMSTR2_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x8>;
 		};
 
-		spi3: spi@40053000 {
-			reg = <0x40053000 0x1000>;
+		spi3: spi@APOLLO4P_IOM3 {
+			reg = <APOLLO4P_IOM3_BASE APOLLO4P_IOM3_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <9 0>;
+			interrupts = <APOLLO4P_IOMSTR3_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x10>;
 		};
 
-		spi4: spi@40054000 {
+		spi4: spi@APOLLO4P_IOM4 {
 			/* IOM4 works as SPI and is wired internally for BLE HCI. */
 			compatible = "ambiq,spi";
-			reg = <0x40054000 0x1000>;
+			reg = <APOLLO4P_IOM4_BASE APOLLO4P_IOM4_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <10 0>;
+			interrupts = <APOLLO4P_IOMSTR4_IRQ 0>;
 			cs-gpios = <&gpio32_63 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
 			clock-frequency = <DT_FREQ_M(24)>;
 			status = "disabled";
@@ -192,160 +193,160 @@
 			};
 		};
 
-		spi5: spi@40055000 {
-			reg = <0x40055000 0x1000>;
+		spi5: spi@APOLLO4P_IOM5 {
+			reg = <APOLLO4P_IOM5_BASE APOLLO4P_IOM5_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <11 0>;
+			interrupts = <APOLLO4P_IOMSTR5_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x40>;
 		};
 
-		spi6: spi@40056000 {
-			reg = <0x40056000 0x1000>;
+		spi6: spi@APOLLO4P_IOM6 {
+			reg = <APOLLO4P_IOM6_BASE APOLLO4P_IOM6_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <12 0>;
+			interrupts = <APOLLO4P_IOMSTR6_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x80>;
 		};
 
-		spi7: spi@40057000 {
-			reg = <0x40057000 0x1000>;
+		spi7: spi@APOLLO4P_IOM7 {
+			reg = <APOLLO4P_IOM7_BASE APOLLO4P_IOM7_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <13 0>;
+			interrupts = <APOLLO4P_IOMSTR7_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x100>;
 		};
 
-		i2c0: i2c@40050000 {
-			reg = <0x40050000 0x1000>;
+		i2c0: i2c@APOLLO4P_IOM0 {
+			reg = <APOLLO4P_IOM0_BASE APOLLO4P_IOM0_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <6 0>;
+			interrupts = <APOLLO4P_IOMSTR0_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x2>;
 		};
 
-		i2c1: i2c@40051000 {
-			reg = <0x40051000 0x1000>;
+		i2c1: i2c@APOLLO4P_IOM1 {
+			reg = <APOLLO4P_IOM1_BASE APOLLO4P_IOM1_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <7 0>;
+			interrupts = <APOLLO4P_IOMSTR1_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x4>;
 		};
 
-		i2c2: i2c@40052000 {
-			reg = <0x40052000 0x1000>;
+		i2c2: i2c@APOLLO4P_IOM2 {
+			reg = <APOLLO4P_IOM2_BASE APOLLO4P_IOM2_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <8 0>;
+			interrupts = <APOLLO4P_IOMSTR2_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x8>;
 		};
 
-		i2c3: i2c@40053000 {
-			reg = <0x40053000 0x1000>;
+		i2c3: i2c@APOLLO4P_IOM3 {
+			reg = <APOLLO4P_IOM3_BASE APOLLO4P_IOM3_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <9 0>;
+			interrupts = <APOLLO4P_IOMSTR3_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x10>;
 		};
 
-		i2c4: i2c@40054000 {
-			reg = <0x40054000 0x1000>;
+		i2c4: i2c@APOLLO4P_IOM4 {
+			reg = <APOLLO4P_IOM4_BASE APOLLO4P_IOM4_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <10 0>;
+			interrupts = <APOLLO4P_IOMSTR4_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x20>;
 		};
 
-		i2c5: i2c@40055000 {
-			reg = <0x40055000 0x1000>;
+		i2c5: i2c@APOLLO4P_IOM5 {
+			reg = <APOLLO4P_IOM5_BASE APOLLO4P_IOM5_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <11 0>;
+			interrupts = <APOLLO4P_IOMSTR5_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x40>;
 		};
 
-		i2c6: i2c@40056000 {
-			reg = <0x40056000 0x1000>;
+		i2c6: i2c@APOLLO4P_IOM6 {
+			reg = <APOLLO4P_IOM6_BASE APOLLO4P_IOM6_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <12 0>;
+			interrupts = <APOLLO4P_IOMSTR6_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x80>;
 		};
 
-		i2c7: i2c@40057000 {
-			reg = <0x40057000 0x1000>;
+		i2c7: i2c@APOLLO4P_IOM7 {
+			reg = <APOLLO4P_IOM7_BASE APOLLO4P_IOM7_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <13 0>;
+			interrupts = <APOLLO4P_IOMSTR7_IRQ 0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x100>;
 		};
 
-		mspi0: spi@40060000 {
+		mspi0: spi@APOLLO4P_MSPI0 {
 			compatible = "ambiq,mspi";
-			reg = <0x40060000 0x400>;
-			interrupts = <20 0>;
+			reg = <APOLLO4P_MSPI0_BASE APOLLO4P_MSPI0_SIZE>;
+			interrupts = <APOLLO4P_MSPI0_IRQ 0>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x4000>;
 		};
 
-		mspi1: spi@40061000 {
+		mspi1: spi@APOLLO4P_MSPI1 {
 			compatible = "ambiq,mspi";
-			reg = <0x40061000 0x400>;
-			interrupts = <21 0>;
+			reg = <APOLLO4P_MSPI1_BASE APOLLO4P_MSPI1_SIZE>;
+			interrupts = <APOLLO4P_MSPI1_IRQ 0>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x8000>;
 		};
 
-		mspi2: spi@40062000 {
+		mspi2: spi@APOLLO4P_MSPI2 {
 			compatible = "ambiq,mspi";
-			reg = <0x40062000 0x400>;
-			interrupts = <22 0>;
+			reg = <APOLLO4P_MSPI2_BASE APOLLO4P_MSPI2_SIZE>;
+			interrupts = <APOLLO4P_MSPI2_IRQ 0>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x10000>;
 		};
 
-		usb: usb@400b0000 {
+		usb: usb@APOLLO4P_USB {
 			compatible = "ambiq,usb";
-			reg = <0x400B0000 0x4100>;
-			interrupts = <27 0>;
+			reg = <APOLLO4P_USB_BASE APOLLO4P_USB_SIZE>;
+			interrupts = <APOLLO4P_USB_IRQ 0>;
 			num-bidir-endpoints = <6>;
 			maximum-speed = "full-speed";
 			status = "disabled";
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x400000>;
 		};
 
-		rtc0: rtc@40004800 {
+		rtc0: rtc@APOLLO4P_RTC {
 			compatible = "ambiq,rtc";
-			reg = <0x40004800 0x210>;
-			interrupts = <2 0>;
+			reg = <APOLLO4P_RTC_BASE APOLLO4P_RTC_SIZE>;
+			interrupts = <APOLLO4P_RTC_IRQ 0>;
 			alarms-count = <1>;
 			status = "disabled";
 		};
 
-		pinctrl: pin-controller@40010000 {
+		pinctrl: pin-controller@APOLLO4P_GPIO {
 			compatible = "ambiq,apollo4-pinctrl";
-			reg = <0x40010000 0x800>;
+			reg = <APOLLO4P_GPIO_BASE APOLLO4P_GPIO_SIZE>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 
-			gpio: gpio@40010000 {
+			gpio: gpio@APOLLO4P_GPIO {
 				compatible = "ambiq,gpio";
 				gpio-map-mask = <0xffffffe0 0xffffffc0>;
 				gpio-map-pass-thru = <0x1f 0x3f>;
@@ -355,7 +356,7 @@
 					0x40 0x0 &gpio64_95 0x0 0x0
 					0x60 0x0 &gpio96_127 0x0 0x0
 				>;
-				reg = <0x40010000>;
+				reg = <APOLLO4P_GPIO_BASE>;
 				#gpio-cells = <2>;
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -366,7 +367,7 @@
 					gpio-controller;
 					#gpio-cells = <2>;
 					reg = <0>;
-					interrupts = <56 0>;
+					interrupts = <APOLLO4P_GPIO0_001F_IRQ 0>;
 					status = "disabled";
 				};
 
@@ -375,7 +376,7 @@
 					gpio-controller;
 					#gpio-cells = <2>;
 					reg = <0x80>;
-					interrupts = <57 0>;
+					interrupts = <APOLLO4P_GPIO0_203F_IRQ 0>;
 					status = "disabled";
 				};
 
@@ -384,7 +385,7 @@
 					gpio-controller;
 					#gpio-cells = <2>;
 					reg = <0x100>;
-					interrupts = <58 0>;
+					interrupts = <APOLLO4P_GPIO0_405F_IRQ 0>;
 					status = "disabled";
 				};
 
@@ -393,20 +394,19 @@
 					gpio-controller;
 					#gpio-cells = <2>;
 					reg = <0x180>;
-					interrupts = <59 0>;
+					interrupts = <APOLLO4P_GPIO0_607F_IRQ 0>;
 					status = "disabled";
 				};
 			};
 		};
 
-		wdt0: watchdog@40024000 {
+		wdt0: watchdog@APOLLO4P_WDT {
 			compatible = "ambiq,watchdog";
-			reg = <0x40024000 0x400>;
-			interrupts = <1 0>;
+			reg = <APOLLO4P_WDT_BASE APOLLO4P_WDT_SIZE>;
+			interrupts = <APOLLO4P_WDT_IRQ 0>;
 			clock-frequency = <16>;
 			status = "disabled";
 		};
-
 	};
 };
 
diff --git a/west.yml b/west.yml
index 53a3c8fd03d3a0..d3e9dcbe42ffd9 100644
--- a/west.yml
+++ b/west.yml
@@ -152,7 +152,7 @@ manifest:
       groups:
         - hal
     - name: hal_ambiq
-      revision: 87a188b91aca22ce3ce7deb4a1cbf7780d784673
+      revision: 68bb8adda80a3132562a89f2662c9928f58f77d1
       path: modules/hal/ambiq
       groups:
         - hal