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High-Level Synthesis from Rust

Background

Digital circuits are typically designed using hardware description languages (HDLs) like Verilog or VHDL. High-level synthesis (HLS) is a process that enables the design of digital circuits in a high-level language, such as C or C++. HLS allows designers to write their design at a higher level of abstraction which can be more natural and familiar to software developers.

The generated circuits can be deployed to FPGAs. That can offer higher performance and lower power consumption, which can be particularly useful for applications such as high performance computing, image processing, and telecommunications.

Issue

The source languages used for HLS are usually limited subsets of C/C++ with some additional restrictions. Rust could be a better source for HLS, because it already has some restrictions for dealing with memory that could proof beneficial for HLS. For example its semantics define memory and ownership more clearly than C/C++.

There are some ways how toolchains for HLS from Rust can be built with currently existing tooling. However, it is currently not known how viable these different toolchains would be for practical application specifically what restrictions would apply, if and how they could benefit from the additional information provided by Rust.

Objectives and hypothesis

The main objective is to create an overview about how HLS from Rust can be achieved with state-of-the-art technologies.

Objectives

  • Create and document toolchains for HLS from Rust.

  • Evaluate and compare the toolchains.

  • Package the toolchains in some reusable way.

  • Figure out how to leverage Rust to improve the toolchains. (maybe)

Hypotheses

  • There are ways to build toolchains for HLS from Rust by using existing tools.

  • Rust can be used to improve HLS in some way.

If these objectives are fulfilled a next step could be to analyze how specific features of Rust could be used to improved.

What needs to be done

I identified five main tasks that need to be done.

  1. Discovering possible pathways to perform HLS from Rust with existing tools.

  2. Building and documenting one or more toolchains for each pathway.

  3. Defining a methodology for comparing the toolchains.

  4. Comparing the toolchains.

  5. Analyzing the results.

They could be divided into a group for creating toolchains (1, 2) and for evaluating toolchains (3, 4, 5).

Related work

There is currently one article investigating the viability of Rust as a source for HLS [Har22]. There does not seem to be any other research on this topic.

Until recently HLS was only possible from C/C++ based languages [Nan16]. There is research on performing HLS from intermediate languages/representations such as LLVM IR [Rog20] [Li21] [Lia23] [Fer21] [Sch20]. Recently google created the XLS project which is building a flexible system for HLS [XLS] [Nor18]. They also maintain a language called DSLX [DSLX] which is similar to Rust, but designed for HLS [DSLX].

Bibliography

  • [Har22] Hardin, David, Hardware/Software Co-Assurance using the Rust Programming Language and ACL2, arXiv preprint arXiv:2205.11709, 2022. 🔗

  • [Rog20] Rogers, Samuel and Slycord, Joshua and Baharani, Mohammadreza and Tabkhi, Hamed, gem5-SALAM: A System Architecture for LLVM-based Accelerator Modeling, 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 471-482, 2020. 🔗

  • [Li21] Li, Rui and Berkley, Lincoln and Yang, Yihang and Manohar, Rajit, Fluid: An Asynchronous High-level Synthesis Tool for Complex Program Structures, 2021 27th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 1-8, 2020. 🔗

  • [Lia23] Liang, Geng-Ming and Yuan, Chuan-Yue and Yuan, Meng-Shiun and Chen, Tai-Liang and Chen, Kuan-Hsun and Lee, Jenq-Kuen, The Support of MLIR HLS Adaptor for LLVM IR, Workshop Proceedings of the 51st International Conference on Parallel Processing, 1-8, 2020. 🔗

  • [Fer21] F. Ferrandi et al., Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications, 2021 58th ACM/IEEE Design Automation Conference (DAC), 1327-1330, 2021. 🔗

  • [Rot10] F. Ferrandi et al., C-to-Verilog. com: High-Level Synthesis Using LLVM, University of Haifa, 2010. 🔗

  • [Sch20] Fabian Schuiki, Andreas Kurth, Tobias Grosser, and Luca Benini, LLHD: a multi-level intermediate representation for hardware description languages, In Proceedings of the 41st ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI 2020), 258–271, 2020. 🔗

  • [Nan16] R. Nane et al., A Survey and Evaluation of FPGA High-Level Synthesis Tools, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1591-1604, 2016. 🔗

  • [Nor18] D. H. Noronha, B. Salehpour and S. J. E. Wilton, LeFlow: Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks, Fifth International Workshop on FPGAs for Software Programmers, 1-8, 2018. 🔗

  • [Soz22] Sozzo, Emanuele Del, et al., Pushing the level of abstraction of digital system design: A survey on how to program FPGAs, ACM Computing Surveys, 1-48, 2022. 🔗

  • [XLS] XLS project page 🔗

  • [DSLX] DSLX Reference 🔗