-
Notifications
You must be signed in to change notification settings - Fork 5
/
Copy pathgpu1024.conf
executable file
·182 lines (165 loc) · 5.14 KB
/
gpu1024.conf
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
#NO WHITESPACE BETWEEN TEXT DELIMETERS!
[borphserver]
#List of servers to connect to.
servers = pf1:7147,pf2:7147,pf3:7147,pf4:7147,pf5:7147,pf6:7147,pf7:7147,pf8:7147
timeserver = pool.ntp.org
#bitstream to load Fengine FPGAs. Should be present and loadable by ROACH KATCP server.
#bitstream = roachf_2048_bak_2012_Apr_01_2324.bof
#bitstream = roachf_2048_bak_2012_Apr_25_1547.bof
#bitstream = roachf_2048_bak_2012_May_01_0019.bof
#this boffile has options to be a 16 through 512 input f engine. (changes packet format)
#bitstream = roachf_1024ch_ma_2012_May_17_0932.bof
bitstream = roachf_1024ch_ma_2012_May_30_1841.bof
[correlator]
#xengine mode (0 = roach, 1 = gpu)
xmode = 1
#number of frequency channels
n_chans = 1024
#number of total inputs.
n_ants = 64
#fft shifting schedule. should be in decimal?
fft_shift = 65535
#number of antennas per fengine.
n_ants_per_feng = 4
#Trigger using external 1PPS or internal sync pulse sent using serial port, eg, int, ext, soft (no quotation marks)
trig_mode = ext
#Serial port device name (if using internal trigger for F-engines), i.e., /dev/ttyS0, /dev/ttyS1, etc (no quotation marks)
int_trig_serial_port = /dev/ttyS1
acc_len = 4096
#Number of integrations performed inherently in the X engine.
xeng_acc_len = 128
#Clockrate of ADCs in GHz.
adc_clk = 0.200
#Number of stokes parameters calculated.
n_stokes = 4
#Number of X engines per FPGA
x_per_fpga = 2
#Number of F engine clock cycles between X engine syncs. This is generated by the descramble block in the X engines. 2^18 = 262144
clk_per_sync = 262144
#Mixing freqency as a fraction of the sampling frequency. (the DDC block in the F engines). eg, 0.25. Set to zero if no DDC is present.
ddc_mix_freq = 0
#Frequency decimation of the DDC block in the F engines. eg, 4
ddc_decimation = 1
#adc clock rate in Ghz
adc_clk = .2
#number of quantisation bits
feng_bits = 4
#strided (chan mode 0) or interleaved (chan mode 1)
xeng_chan_mode = 1
#logical binary point of position of f engine data
feng_fix_pnt_pos = 3
#pkt length of 10gbe data in 64 bit words (going to and coming from switch, as well as to gpu). this is of payload.
10gbe_pkt_len = 1024
#udp port for 10gbe data to switch.
10gbe_sw_port = 8888
#starting ip address to use for 10gbe to switch (will be auto incrementd)
10gbe_sw_ip = 10.0.0.128
#port for 10gbe to gpu
10gbe_gpu_port = 8511
#ip address for 10gbe core that send data to gpu.
#this is the same for all fpgas since gpu is direct connect to this core.
10gbe_gpu_ip = 192.168.2.128
#pkt len of 10GbE data in 64 bit words
10gbe_pkt_len = 32
#UDP data port
10gbe_port = 8888
#Starting ip address to use (will be auto-incremented for different x engines)
10gbe_ip = 10.0.0.128
x_eng_clk = 215
#Number of dual-pol antennas' data coming over one XAUI link
n_ants_per_xaui = 4
#Number of XAUI ports in use per X engine FPGA
n_xaui_ports_per_fpga = 1
#Number of accumulations used during ADC amplitude averaging
adc_levels_acc_len = 65536
#starting ip address of gpu machines. should be auto incremented.
#alternatively we can specify ipaddressess. doesnt really matter since roach and gpu hosts are direct connect.
gpu_ip = px1,px2,px3,px4,px5,px6,px7,px7
#number of bits in adc
adc_bits = 8
#XAUI userspace-address on F engines for base_ant_offset
antenna_offset_addr = 8193
#Payload data type. 0 = Big Endian Integers. 1 = Little Endian Floats.
payload_data_type = 1
[receiver]
#UDP receiver for output data
rx_udp_port = 7148
#rx_udp_ip = 192.168.100.1
#rx_udp_ip = 10.0.0.1
rx_udp_ip = 169.254.145.1
#instance ID is populated in lower bits of SPEAD packet option field ID 2
instance_id=0
#Output packet payload length in bytes. Does not include SPEAD options fields.
rx_pkt_payload_len = 1024
[equalisation]
#decimation. Adjacent frequency channels share coefficients. The center equalization value is chosen for adjacent bins. n_eq_coeffs_per_polarisation == n_chans/eq_decimation.
eq_decimation = 64
#Tolerance to use for auto-equalization
tolerance = 0.01
#Perform automatic equalization (=1) or set to fixed EQ_poly values (=0)
auto_eq = 0
#coefficients. These are the same across the band. On input bases (not dual ant pol)
eq_poly_0x =700
eq_poly_0y =700
eq_poly_1x =700
eq_poly_1y =700
eq_poly_2x =700
eq_poly_2y =700
eq_poly_3x =700
eq_poly_3y =700
eq_poly_4x =700
eq_poly_4y =700
eq_poly_5x =700
eq_poly_5y =700
eq_poly_6x =700
eq_poly_6y =700
eq_poly_7x =700
eq_poly_7y =700
eq_poly_8x =700
eq_poly_8y =700
eq_poly_9x =700
eq_poly_9y =700
eq_poly_10x =700
eq_poly_10y =700
eq_poly_11x =700
eq_poly_11y =700
eq_poly_12x =700
eq_poly_12y =700
eq_poly_13x =700
eq_poly_13y =700
eq_poly_14x =700
eq_poly_14y =700
eq_poly_15x =700
eq_poly_15y =700
eq_poly_16x =700
eq_poly_16y =700
eq_poly_17x =700
eq_poly_17y =700
eq_poly_18x =700
eq_poly_18y =700
eq_poly_19x =700
eq_poly_19y =700
eq_poly_20x =700
eq_poly_20y =700
eq_poly_21x =700
eq_poly_21y =700
eq_poly_22x =700
eq_poly_22y =700
eq_poly_23x =700
eq_poly_23y =700
eq_poly_24x =700
eq_poly_24y =700
eq_poly_25x =700
eq_poly_25y =700
eq_poly_26x =700
eq_poly_26y =700
eq_poly_27x =700
eq_poly_27y =700
eq_poly_28x =700
eq_poly_28y =700
eq_poly_29x =700
eq_poly_29y =700
eq_poly_30x =700
eq_poly_30y =700
eq_poly_31x =700
eq_poly_31y =700