-
Notifications
You must be signed in to change notification settings - Fork 5
/
Copy pathcn_i_128w_2k_do_al_r303.mdl
25340 lines (25336 loc) · 601 KB
/
cn_i_128w_2k_do_al_r303.mdl
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
Model {
Name "cn_i_128w_2k_do_al_r303"
Version 6.2
MdlSubVersion 0
GraphicalInterface {
NumRootInports 0
NumRootOutports 0
ParameterArgumentNames ""
ComputedModelVersion "1.422"
NumModelReferences 0
NumTestPointedSignals 0
}
SavedCharacterEncoding "ibm-5348_P100-1997"
SaveDefaultBlockParams on
SampleTimeColors off
LibraryLinkDisplay "all"
WideLines off
ShowLineDimensions on
ShowPortDataTypes on
ShowLoopsOnError on
IgnoreBidirectionalLines off
ShowStorageClass off
ShowTestPointIcons on
ShowViewerIcons on
SortedOrder off
ExecutionContextIcon off
ShowLinearizationAnnotations on
RecordCoverage off
CovPath "/"
CovSaveName "covdata"
CovMetricSettings "dw"
CovNameIncrementing off
CovHtmlReporting on
covSaveCumulativeToWorkspaceVar on
CovSaveSingleToWorkspaceVar on
CovCumulativeVarName "covCumulativeData"
CovCumulativeReport off
CovReportOnPause on
ScopeRefreshTime 0.035000
OverrideScopeRefreshTime on
DisableAllScopes off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
MinMaxOverflowArchiveMode "Overwrite"
BlockNameDataTip off
BlockParametersDataTip off
BlockDescriptionStringDataTip off
ToolBar on
StatusBar on
BrowserShowLibraryLinks off
BrowserLookUnderMasks off
Created "Thu Jan 19 08:22:55 2006"
UpdateHistory "UpdateHistoryNever"
ModifiedByFormat "%<Auto>"
LastModifiedBy "manley"
ModifiedDateFormat "%<Auto>"
LastModifiedDate "Thu Mar 06 14:02:34 2008"
ModelVersionFormat "1.%<AutoIncrement:422>"
ConfigurationManager "None"
LinearizationMsg "none"
Profile off
ParamWorkspaceSource "MATLABWorkspace"
AccelSystemTargetFile "accel.tlc"
AccelTemplateMakefile "accel_default_tmf"
AccelMakeCommand "make_rtw"
TryForcingSFcnDF off
ExtModeBatchMode off
ExtModeEnableFloating on
ExtModeTrigType "manual"
ExtModeTrigMode "normal"
ExtModeTrigPort "1"
ExtModeTrigElement "any"
ExtModeTrigDuration 1000
ExtModeTrigDurationFloating "auto"
ExtModeTrigHoldOff 0
ExtModeTrigDelay 0
ExtModeTrigDirection "rising"
ExtModeTrigLevel 0
ExtModeArchiveMode "off"
ExtModeAutoIncOneShot off
ExtModeIncDirWhenArm off
ExtModeAddSuffixToVar off
ExtModeWriteAllDataToWs off
ExtModeArmWhenConnect on
ExtModeSkipDownloadWhenConnect off
ExtModeLogAll on
ExtModeAutoUpdateStatusClock on
BufferReuse on
StrictBusMsg "None"
ProdHWDeviceType "32-bit Generic"
ShowModelReferenceBlockVersion off
ShowModelReferenceBlockIO off
Array {
Type "Handle"
Dimension 1
Simulink.ConfigSet {
$ObjectID 1
Version "1.1.0"
Array {
Type "Handle"
Dimension 7
Simulink.SolverCC {
$ObjectID 2
Version "1.1.0"
StartTime "0.0"
StopTime "10"
AbsTol "auto"
FixedStep "auto"
InitialStep "auto"
MaxNumMinSteps "-1"
MaxOrder 5
ExtrapolationOrder 4
NumberNewtonIterations 1
MaxStep "auto"
MinStep "auto"
RelTol "1e-3"
SolverMode "Auto"
Solver "ode45"
SolverName "ode45"
ZeroCrossControl "UseLocalSettings"
AlgebraicLoopSolver "TrustRegion"
SolverResetMethod "Fast"
PositivePriorityOrder off
AutoInsertRateTranBlk off
SampleTimeConstraint "Unconstrained"
RateTranMode "Deterministic"
}
Simulink.DataIOCC {
$ObjectID 3
Version "1.1.0"
Decimation "1"
ExternalInput "[t, u]"
FinalStateName "xFinal"
InitialState "xInitial"
LimitDataPoints on
MaxDataPoints "1000"
LoadExternalInput off
LoadInitialState off
SaveFinalState off
SaveFormat "Array"
SaveOutput on
SaveState off
SignalLogging on
SaveTime on
StateSaveName "xout"
TimeSaveName "tout"
OutputSaveName "yout"
SignalLoggingName "logsout"
OutputOption "RefineOutputTimes"
OutputTimes "[]"
Refine "1"
}
Simulink.OptimizationCC {
$ObjectID 4
Array {
Type "Cell"
Dimension 5
Cell "ZeroExternalMemoryAtStartup"
Cell "ZeroInternalMemoryAtStartup"
Cell "InitFltsAndDblsToZero"
Cell "OptimizeModelRefInitCode"
Cell "NoFixptDivByZeroProtection"
PropName "DisabledProps"
}
Version "1.1.0"
BlockReduction on
BooleanDataType on
ConditionallyExecuteInputs on
InlineParams off
InlineInvariantSignals off
OptimizeBlockIOStorage on
BufferReuse on
EnforceIntegerDowncast on
ExpressionFolding on
FoldNonRolledExpr on
LocalBlockOutputs on
ParameterPooling on
RollThreshold 5
SystemCodeInlineAuto off
StateBitsets off
DataBitsets off
UseTempVars off
ZeroExternalMemoryAtStartup on
ZeroInternalMemoryAtStartup on
InitFltsAndDblsToZero on
NoFixptDivByZeroProtection off
EfficientFloat2IntCast off
OptimizeModelRefInitCode off
LifeSpan "inf"
BufferReusableBoundary on
}
Simulink.DebuggingCC {
$ObjectID 5
Version "1.1.0"
RTPrefix "error"
ConsistencyChecking "none"
ArrayBoundsChecking "none"
SignalInfNanChecking "none"
AlgebraicLoopMsg "warning"
ArtificialAlgebraicLoopMsg "warning"
CheckSSInitialOutputMsg on
CheckExecutionContextPreStartOutputMsg off
CheckExecutionContextRuntimeOutputMsg off
SignalResolutionControl "TryResolveAllWithWarning"
BlockPriorityViolationMsg "warning"
MinStepSizeMsg "warning"
SolverPrmCheckMsg "warning"
InheritedTsInSrcMsg "warning"
DiscreteInheritContinuousMsg "warning"
MultiTaskDSMMsg "warning"
MultiTaskRateTransMsg "error"
SingleTaskRateTransMsg "none"
TasksWithSamePriorityMsg "warning"
CheckMatrixSingularityMsg "none"
IntegerOverflowMsg "warning"
Int32ToFloatConvMsg "warning"
ParameterDowncastMsg "error"
ParameterOverflowMsg "error"
ParameterPrecisionLossMsg "warning"
UnderSpecifiedDataTypeMsg "none"
UnnecessaryDatatypeConvMsg "none"
VectorMatrixConversionMsg "none"
InvalidFcnCallConnMsg "error"
FcnCallInpInsideContextMsg "Use local settings"
SignalLabelMismatchMsg "none"
UnconnectedInputMsg "warning"
UnconnectedOutputMsg "warning"
UnconnectedLineMsg "warning"
SFcnCompatibilityMsg "none"
UniqueDataStoreMsg "none"
BusObjectLabelMismatch "warning"
RootOutportRequireBusObject "warning"
AssertControl "UseLocalSettings"
EnableOverflowDetection off
ModelReferenceIOMsg "none"
ModelReferenceVersionMismatchMessage "none"
ModelReferenceIOMismatchMessage "none"
ModelReferenceCSMismatchMessage "none"
ModelReferenceSimTargetVerbose off
UnknownTsInhSupMsg "warning"
ModelReferenceDataLoggingMessage "warning"
ModelReferenceSymbolNameMessage "warning"
ModelReferenceExtraNoncontSigs "error"
}
Simulink.HardwareCC {
$ObjectID 6
Version "1.1.0"
ProdBitPerChar 8
ProdBitPerShort 16
ProdBitPerInt 32
ProdBitPerLong 32
ProdIntDivRoundTo "Undefined"
ProdEndianess "Unspecified"
ProdWordSize 32
ProdShiftRightIntArith on
ProdHWDeviceType "32-bit Generic"
TargetBitPerChar 8
TargetBitPerShort 16
TargetBitPerInt 32
TargetBitPerLong 32
TargetShiftRightIntArith on
TargetIntDivRoundTo "Undefined"
TargetEndianess "Unspecified"
TargetWordSize 32
TargetTypeEmulationWarnSuppressLevel 0
TargetPreprocMaxBitsSint 32
TargetPreprocMaxBitsUint 32
TargetHWDeviceType "Specified"
TargetUnknown off
ProdEqTarget on
}
Simulink.ModelReferenceCC {
$ObjectID 7
Version "1.1.0"
UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange"
CheckModelReferenceTargetMessage "error"
ModelReferenceNumInstancesAllowed "Multi"
ModelReferencePassRootInputsByReference on
ModelReferenceMinAlgLoopOccurrences off
}
Simulink.RTWCC {
$BackupClass "Simulink.RTWCC"
$ObjectID 8
Array {
Type "Cell"
Dimension 1
Cell "IncludeHyperlinkInReport"
PropName "DisabledProps"
}
Version "1.1.0"
SystemTargetFile "grt.tlc"
GenCodeOnly off
MakeCommand "make_rtw"
TemplateMakefile "grt_default_tmf"
GenerateReport off
SaveLog off
RTWVerbose on
RetainRTWFile off
ProfileTLC off
TLCDebug off
TLCCoverage off
TLCAssert off
ProcessScriptMode "Default"
ConfigurationMode "Optimized"
ConfigAtBuild off
IncludeHyperlinkInReport off
LaunchReport off
TargetLang "C"
Array {
Type "Handle"
Dimension 2
Simulink.CodeAppCC {
$ObjectID 9
Array {
Type "Cell"
Dimension 9
Cell "IgnoreCustomStorageClasses"
Cell "InsertBlockDesc"
Cell "SFDataObjDesc"
Cell "SimulinkDataObjDesc"
Cell "DefineNamingRule"
Cell "SignalNamingRule"
Cell "ParamNamingRule"
Cell "InlinedPrmAccess"
Cell "CustomSymbolStr"
PropName "DisabledProps"
}
Version "1.1.0"
ForceParamTrailComments off
GenerateComments on
IgnoreCustomStorageClasses on
IncHierarchyInIds off
MaxIdLength 31
PreserveName off
PreserveNameWithParent off
ShowEliminatedStatement off
IncAutoGenComments off
SimulinkDataObjDesc off
SFDataObjDesc off
IncDataTypeInIds off
PrefixModelToSubsysFcnNames on
CustomSymbolStr "$R$N$M"
MangleLength 1
DefineNamingRule "None"
ParamNamingRule "None"
SignalNamingRule "None"
InsertBlockDesc off
SimulinkBlockComments on
EnableCustomComments off
InlinedPrmAccess "Literals"
ReqsInCode off
}
Simulink.GRTTargetCC {
$BackupClass "Simulink.TargetCC"
$ObjectID 10
Array {
Type "Cell"
Dimension 12
Cell "IncludeMdlTerminateFcn"
Cell "CombineOutputUpdateFcns"
Cell "SuppressErrorStatus"
Cell "ERTCustomFileBanners"
Cell "GenerateSampleERTMain"
Cell "MultiInstanceERTCode"
Cell "PurelyIntegerCode"
Cell "SupportNonFinite"
Cell "SupportComplex"
Cell "SupportAbsoluteTime"
Cell "SupportContinuousTime"
Cell "SupportNonInlinedSFcns"
PropName "DisabledProps"
}
Version "1.1.0"
TargetFcnLib "ansi_tfl_tmw.mat"
TargetLibSuffix ""
TargetPreCompLibLocation ""
GenFloatMathFcnCalls "ANSI_C"
UtilityFuncGeneration "Auto"
GenerateFullHeader on
GenerateSampleERTMain off
IsPILTarget off
ModelReferenceCompliant on
IncludeMdlTerminateFcn on
CombineOutputUpdateFcns off
SuppressErrorStatus off
IncludeFileDelimiter "Auto"
ERTCustomFileBanners off
SupportAbsoluteTime on
LogVarNameModifier "rt_"
MatFileLogging on
MultiInstanceERTCode off
SupportNonFinite on
SupportComplex on
PurelyIntegerCode off
SupportContinuousTime on
SupportNonInlinedSFcns on
ExtMode off
ExtModeStaticAlloc off
ExtModeTesting off
ExtModeStaticAllocSize 1000000
ExtModeTransport 0
ExtModeMexFile "ext_comm"
RTWCAPISignals off
RTWCAPIParams off
RTWCAPIStates off
GenerateASAP2 off
}
PropName "Components"
}
}
PropName "Components"
}
Name "Configuration"
SimulationMode "normal"
CurrentDlgPage "Solver"
}
PropName "ConfigurationSets"
}
Simulink.ConfigSet {
$PropName "ActiveConfigurationSet"
$ObjectID 1
}
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType Bias
Bias "0"
SaturateOnIntegerOverflow on
}
Block {
BlockType Constant
Value "1"
VectorParams1D on
OutDataTypeMode "Inherit from 'Constant value'"
OutDataType "sfix(16)"
ConRadixGroup "Use specified scaling"
OutScaling "2^0"
SampleTime "inf"
}
Block {
BlockType DiscretePulseGenerator
PulseType "Sample based"
TimeSource "Use simulation time"
Amplitude "1"
Period "2"
PulseWidth "1"
PhaseDelay "0"
SampleTime "1"
VectorParams1D on
}
Block {
BlockType From
IconDisplay "Tag"
}
Block {
BlockType Gain
Gain "1"
Multiplication "Element-wise(K.*u)"
ParameterDataTypeMode "Same as input"
ParameterDataType "sfix(16)"
ParameterScalingMode "Best Precision: Matrix-wise"
ParameterScaling "2^0"
OutDataTypeMode "Same as input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Goto
IconDisplay "Tag"
}
Block {
BlockType Inport
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
Interpolate on
}
Block {
BlockType Logic
Operator "AND"
Inputs "2"
AllPortsSameDT on
OutDataTypeMode "Logical (see Configuration Parameters: Optimiza"
"tion)"
LogicDataType "uint(8)"
SampleTime "-1"
}
Block {
BlockType Outport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType RandomNumber
Mean "0"
Variance "1"
Seed "0"
SampleTime "-1"
VectorParams1D on
}
Block {
BlockType RelationalOperator
Operator ">="
InputSameDT on
LogicOutDataTypeMode "Logical (see Configuration Parameters: Optimiza"
"tion)"
LogicDataType "uint(8)"
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Scope
Floating off
ModelBased off
TickLabels "OneTimeTick"
ZoomMode "on"
Grid "on"
TimeRange "auto"
YMin "-5"
YMax "5"
SaveToWorkspace off
SaveName "ScopeData"
LimitDataPoints on
MaxDataPoints "5000"
Decimation "1"
SampleInput off
SampleTime "0"
}
Block {
BlockType "S-Function"
FunctionName "system"
SFunctionModules "''"
PortCounts "[]"
}
Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Terminator
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "cn_i_128w_2k_do_al_r303"
Location [2, 70, 1422, 836]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "89"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name " System Generator"
Tag "genX"
Ports []
Position [22, 15, 73, 65]
ShowName off
AttributesFormatString "System\\nGenerator"
UserDataPersistent on
UserData "DataTag0"
SourceBlock "xbsIndex_r3/ System Generator"
SourceType "Xilinx System Generator"
ShowPortLabels on
xilinxfamily "Virtex2P"
part "xc2vp50"
speed "-7"
package "ff1152"
synthesis_tool "XST"
directory "./cn_i_128w_2k_do_al_r303/sysgen"
testbench off
simulink_period "1"
sysclk_period "5"
incr_netlist off
trim_vbits "Everywhere in SubSystem"
dbl_ovrd "According to Block Masks"
core_generation "According to Block Masks"
run_coregen off
deprecated_control off
eval_field "0"
}
Block {
BlockType Reference
Name "Band-Limited\nWhite Noise"
Ports [0, 1]
Position [35, 155, 65, 185]
SourceBlock "simulink/Sources/Band-Limited\nWhite Noise"
SourceType "Band-Limited White Noise."
ShowPortLabels on
Cov "[0.1]"
Ts "0.1"
seed "[23341]"
VectorParams1D on
}
Block {
BlockType Reference
Name "Concat"
Ports [4, 1]
Position [1340, 896, 1390, 949]
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "4"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Concat3"
Ports [2, 1]
Position [2085, 349, 2130, 391]
ShowName off
SourceBlock "xbsIndex_r3/Concat"
SourceType "Xilinx Bus Concatenator"
num_inputs "2"
explicit_period off
period "1"
dbl_ovrd off
}
Block {
BlockType Constant
Name "Constant1"
Position [35, 355, 65, 375]
ShowName off
}
Block {
BlockType Reference
Name "Constant14"
Ports [0, 1]
Position [3330, 226, 3345, 244]
ShowName off
SourceBlock "xbsIndex_r3/Constant"
SourceType "Xilinx Constant Block"
const "1"
equ "P=C"
arith_type "Unsigned"
n_bits "1"
bin_pt "0"
opselect "C"
inp2 "PCIN>>17"
opr "+"
inp1 "P"
carry "CIN"
iostate "0"
explicit_period on
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Constant15"
Ports [0, 1]
Position [3330, 263, 3345, 277]
ShowName off
SourceBlock "xbsIndex_r3/Constant"
SourceType "Xilinx Constant Block"
const "0"
equ "P=C"
arith_type "Unsigned"
n_bits "1"
bin_pt "0"
opselect "C"
inp2 "PCIN>>17"
opr "+"
inp1 "P"
carry "CIN"
iostate "0"
explicit_period on
period "1"
dbl_ovrd off
}
Block {
BlockType Constant
Name "Constant19"
Position [425, 680, 455, 710]
Value "3"
}
Block {
BlockType Constant
Name "Constant2"
Position [425, 750, 455, 780]
Value "0"
}
Block {
BlockType Constant
Name "Constant3"
Position [425, 825, 455, 855]
}
Block {
BlockType Reference
Name "Constant4"
Ports [0, 1]
Position [3330, 471, 3345, 489]
ShowName off
SourceBlock "xbsIndex_r3/Constant"
SourceType "Xilinx Constant Block"
const "1"
equ "P=C"
arith_type "Unsigned"
n_bits "1"
bin_pt "0"
opselect "C"
inp2 "PCIN>>17"
opr "+"
inp1 "P"
carry "CIN"
iostate "0"
explicit_period on
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Constant5"
Ports [0, 1]
Position [3330, 508, 3345, 522]
ShowName off
SourceBlock "xbsIndex_r3/Constant"
SourceType "Xilinx Constant Block"
const "0"
equ "P=C"
arith_type "Unsigned"
n_bits "1"
bin_pt "0"
opselect "C"
inp2 "PCIN>>17"
opr "+"
inp1 "P"
carry "CIN"
iostate "0"
explicit_period on
period "1"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Counter"
Ports [0, 1]
Position [785, 1005, 825, 1035]
SourceBlock "xbsIndex_r3/Counter"
SourceType "Xilinx Counter Block"
cnt_type "Free Running"
n_bits "16"
bin_pt "0"
arith_type "Unsigned"
start_count "0"
cnt_to "Inf"
cnt_by_val "1"
operation "Up"
explicit_period off
period "1"
load_pin off
rst off
en off
dbl_ovrd off
show_param off
use_rpm on
gen_core off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "DDC0_0"
Ports [5, 2]
Position [710, 233, 795, 307]
BackgroundColor "magenta"
UserDataPersistent on
UserData "DataTag1"
SourceBlock "ddc_library/DDC"
SourceType "DDC"
ShowPortLabels on
freq_div "4"
lo_freq "1"
num_inputs "4"
lo_bitwidth "8"
lpfir_coeff ".9 * [-0.0161 -0.0428 -0.0504 -0.0249 "
"0.0354 0.1170 0.1948 0.2422 0.2422 0.1948 0.1170 0.0354 "
"-0.0249 -0.0504 -0.0428 -0.0161]"
BitWidthOut "8"
quantization "Round (unbiased: Even Values)"
add_latency "1"
mult_latency "2"
}
Block {
BlockType Reference
Name "DDC0_1"
Ports [5, 2]
Position [710, 323, 795, 397]
BackgroundColor "magenta"
UserDataPersistent on
UserData "DataTag2"
SourceBlock "ddc_library/DDC"
SourceType "DDC"
ShowPortLabels on
freq_div "4"
lo_freq "1"
num_inputs "4"
lo_bitwidth "8"
lpfir_coeff ".9 * [-0.0161 -0.0428 -0.0504 -0.0249 "
"0.0354 0.1170 0.1948 0.2422 0.2422 0.1948 0.1170 0.0354 "
"-0.0249 -0.0504 -0.0428 -0.0161]"
BitWidthOut "8"
quantization "Round (unbiased: Even Values)"
add_latency "1"
mult_latency "2"
}
Block {
BlockType Reference
Name "DDC0_2"
Ports [5, 2]
Position [710, 428, 795, 502]
BackgroundColor "magenta"
UserDataPersistent on
UserData "DataTag3"
SourceBlock "ddc_library/DDC"
SourceType "DDC"
ShowPortLabels on
freq_div "4"
lo_freq "1"
num_inputs "4"
lo_bitwidth "8"
lpfir_coeff ".9 * [-0.0161 -0.0428 -0.0504 -0.0249 "
"0.0354 0.1170 0.1948 0.2422 0.2422 0.1948 0.1170 0.0354 "
"-0.0249 -0.0504 -0.0428 -0.0161]"
BitWidthOut "8"
quantization "Round (unbiased: Even Values)"
add_latency "1"
mult_latency "2"
}
Block {
BlockType Reference
Name "DDC0_3"
Ports [5, 2]
Position [710, 518, 795, 592]
BackgroundColor "magenta"
UserDataPersistent on
UserData "DataTag4"
SourceBlock "ddc_library/DDC"
SourceType "DDC"
ShowPortLabels on
freq_div "4"
lo_freq "1"
num_inputs "4"
lo_bitwidth "8"
lpfir_coeff ".9 * [-0.0161 -0.0428 -0.0504 -0.0249 "
"0.0354 0.1170 0.1948 0.2422 0.2422 0.1948 0.1170 0.0354 "
"-0.0249 -0.0504 -0.0428 -0.0161]"
BitWidthOut "8"
quantization "Round (unbiased: Even Values)"
add_latency "1"
mult_latency "2"
}
Block {
BlockType Reference
Name "Delay"
Ports [1, 1]
Position [3735, 279, 3755, 301]
SourceBlock "xbsIndex_r3/Delay"
SourceType "Xilinx Delay Block"
latency "1"
reg_retiming off
explicit_period off
period "1"
en off
accept_only_valid off
init_zero on
dbl_ovrd off
show_param off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Delay1"
Ports [1, 1]
Position [2340, 781, 2365, 809]
ShowName off
SourceBlock "xbsIndex_r3/Delay"
SourceType "Xilinx Delay Block"
latency "1"
reg_retiming off
explicit_period off
period "1"
en off
accept_only_valid off
init_zero on
dbl_ovrd off
show_param off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Delay2"
Ports [1, 1]
Position [1175, 255, 1195, 275]
ShowName off
SourceBlock "xbsIndex_r3/Delay"
SourceType "Xilinx Delay Block"
latency "2"
reg_retiming off
explicit_period off
period "1"
en off
accept_only_valid off
init_zero on
dbl_ovrd off
show_param off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType Reference
Name "Delay4"
Ports [1, 1]
Position [1175, 435, 1195, 455]
ShowName off
SourceBlock "xbsIndex_r3/Delay"
SourceType "Xilinx Delay Block"
latency "2"
reg_retiming off
explicit_period off
period "1"
en off
accept_only_valid off
init_zero on
dbl_ovrd off
show_param off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
xl_use_area off
}
Block {
BlockType SubSystem
Name "Feng_ctl"
Ports [3, 2]
Position [2230, 773, 2310, 847]
AttributesFormatString "Mapped address: 8192"