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MANDELBROT_HW.fit.rpt
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Fitter report for MANDELBROT_HW
Sat Jul 6 13:29:06 2024
Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Parallel Compilation
5. Fitter Netlist Optimizations
6. Incremental Compilation Preservation Summary
7. Incremental Compilation Partition Settings
8. Incremental Compilation Placement Preservation
9. Pin-Out File
10. Fitter Resource Usage Summary
11. Fitter Partition Statistics
12. Input Pins
13. Output Pins
14. Bidir Pins
15. I/O Bank Usage
16. All Package Pins
17. I/O Assignment Warnings
18. PLL Usage Summary
19. Fitter Resource Utilization by Entity
20. Delay Chain Summary
21. Pad To Core Delay Chain Fanout
22. Control Signals
23. Global & Other Fast Signals
24. Non-Global High Fan-Out Signals
25. Fitter RAM Summary
26. Fitter DSP Block Usage Summary
27. DSP Block Details
28. Routing Usage Summary
29. I/O Rules Summary
30. I/O Rules Details
31. I/O Rules Matrix
32. Fitter Device Options
33. Operating Settings and Conditions
34. Estimated Delay Added for Hold Timing Summary
35. Estimated Delay Added for Hold Timing Details
36. Fitter Messages
37. Fitter Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2023 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+----------------------------------------------------------------------------------+
; Fitter Summary ;
+---------------------------------+------------------------------------------------+
; Fitter Status ; Successful - Sat Jul 6 13:29:06 2024 ;
; Quartus Prime Version ; 23.1std.0 Build 991 11/28/2023 SC Lite Edition ;
; Revision Name ; MANDELBROT_HW ;
; Top-level Entity Name ; MANDELBROT_HW ;
; Family ; Cyclone V ;
; Device ; 5CSEBA6U23I7 ;
; Timing Models ; Final ;
; Logic utilization (in ALMs) ; 473 / 41,910 ( 1 % ) ;
; Total registers ; 607 ;
; Total pins ; 73 / 314 ( 23 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 2,621,440 / 5,662,720 ( 46 % ) ;
; Total RAM Blocks ; 320 / 553 ( 58 % ) ;
; Total DSP Blocks ; 3 / 112 ( 3 % ) ;
; Total HSSI RX PCSs ; 0 ;
; Total HSSI PMA RX Deserializers ; 0 ;
; Total HSSI TX PCSs ; 0 ;
; Total HSSI PMA TX Serializers ; 0 ;
; Total PLLs ; 2 / 6 ( 33 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
+---------------------------------+------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
; Device ; 5CSEBA6U23I7 ; ;
; Use smart compilation ; On ; Off ;
; Maximum processors allowed for parallel compilation ; 1 ; ;
; Minimum Core Junction Temperature ; -40 ; ;
; Maximum Core Junction Temperature ; 100 ; ;
; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
; Placement Effort Multiplier ; 1.0 ; 1.0 ;
; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ;
; Optimize Hold Timing ; All Paths ; All Paths ;
; Optimize Multi-Corner Timing ; On ; On ;
; Auto RAM to MLAB Conversion ; On ; On ;
; Equivalent RAM and MLAB Power Up ; Auto ; Auto ;
; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ;
; Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
; SSN Optimization ; Off ; Off ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize Timing for ECOs ; Off ; Off ;
; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
; Weak Pull-Up Resistor ; Off ; Off ;
; Enable Bus-Hold Circuitry ; Off ; Off ;
; Auto Packed Registers ; Auto ; Auto ;
; Auto Delay Chains ; On ; On ;
; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
; Perform Register Duplication for Performance ; Off ; Off ;
; Perform Register Retiming for Performance ; Off ; Off ;
; Perform Asynchronous Signal Pipelining ; Off ; Off ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
; Physical Synthesis Effort Level ; Normal ; Normal ;
; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
; Auto Register Duplication ; Auto ; Auto ;
; Auto Global Clock ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
; Synchronizer Identification ; Auto ; Auto ;
; Enable Beneficial Skew Optimization ; On ; On ;
; Optimize Design for Metastability ; On ; On ;
; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ;
; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
; Clamping Diode ; Off ; Off ;
; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
; Advanced Physical Optimization ; On ; On ;
+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 16 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+---------------------------------------------------+----------------------------+-----------+----------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+
; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+---------------------------------------------------+----------------------------+-----------+----------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+
; mandebrot_plot:u0|mandebrot_plot_pll_0:pll_0|altera_pll:altera_pll_i|outclk_wire[0]~CLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;
; pll:my_pll|pll_0002:pll_inst|altera_pll:altera_pll_i|outclk_wire[0]~CLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;
; FPGA_CLK1_50~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;
; FPGA_CLK2_50~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[1] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[1]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[1]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[1]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[1]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[1]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[1]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[1]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[2] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[2] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[2]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[2]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[2]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[2]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[2]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[2]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[2]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[3] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[3]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[3]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[3]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[3]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[3]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[3]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[3]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[4] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[4]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[4]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[4]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[4]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[4]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[4]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[4]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[5] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[5] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[5]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[5]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[5]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[5]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[5]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[5]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[5]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[6] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[6] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[6]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[6]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[6]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[6]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[6]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[6]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[6]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[7] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[7] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[7]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[7]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[7]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[7]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[7]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[7]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[7]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[8] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[8] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[8]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[8]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[8]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[8]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[8]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[8]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[8]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[9] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[9] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[9]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[9]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[9]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[9]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[9]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[9]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[9]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[10] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[10] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[10]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[10]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[10]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[10]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[10]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[10]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[10]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[11] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[11] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[11]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[11]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[11]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[11]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[11]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[11]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[11]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[12] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[12] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[12]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[12]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[12]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[12]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[12]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[12]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[12]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[13] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[13] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[13]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[13]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[13]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[13]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[13]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[13]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[13]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[14] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[14] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[14]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[14]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[14]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[14]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[14]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[14]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[14]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[15] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[15] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[15]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[15]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[15]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[15]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[15]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[15]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[15]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[16] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[16] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[16]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[16]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[16]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[16]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[16]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[16]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[16]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[17] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[17] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[17]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[17]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[17]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[17]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[17]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[17]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[17]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[18] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[18] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[18]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[18]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[18]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[18]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[18]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[18]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[18]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[19] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[19] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[19]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[19]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[19]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[19]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[19]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[19]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[19]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[20] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[20] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[20]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[20]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[20]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[20]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[20]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[20]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[20]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[21] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[21] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[21]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[21]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[21]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[21]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[21]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[21]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[21]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[22] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[22] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[22]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[22]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[22]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[22]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[22]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[22]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[22]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[23] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[23] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[23]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[23]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[23]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[23]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[23]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[23]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[23]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[24] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[24] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[24]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[24]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[24]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[24]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[24]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[24]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[24]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[25] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[25] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[25]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[25]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[25]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[25]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[25]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[25]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[25]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[26] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[26] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[26]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[26]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_imag_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[26]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[26]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[26]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[26]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_imag[26]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[0] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[0]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[0]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[0]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[0]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[0]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[0]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[0]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[1] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[1]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[1]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[1]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[1]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[1]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[1]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[1]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[2] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[2] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[2]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[2]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[2]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[2]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[2]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[2]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[2]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[3] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[3]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[3]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[3]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[3]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[3]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[3]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[3]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[4] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[4]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[4]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[4]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[4]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[4]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[4]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[4]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[5] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[5] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[5]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[5]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[5]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[5]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[5]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[5]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[5]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[6] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[6] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[6]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[6]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[6]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[6]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[6]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[6]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[6]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[7] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[7] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[7]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[7]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[7]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[7]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[7]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[7]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[7]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[8] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[8] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[8]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[8]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[8]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[8]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[8]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[8]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[8]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[9] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[9] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[9]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[9]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[9]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[9]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[9]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[9]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[9]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[10] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[10] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[10]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[10]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[10]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[10]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[10]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[10]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[10]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[11] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[11] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[11]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[11]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[11]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[11]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[11]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[11]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[11]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[12] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[12] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[12]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[12]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[12]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[12]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[12]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[12]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[12]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[13] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[13] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[13]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[13]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[13]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[13]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[13]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[13]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[13]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[14] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[14] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[14]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[14]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[14]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[14]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[14]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[14]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[14]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[15] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[15] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[15]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[15]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[15]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[15]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[15]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[15]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[15]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[16] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[16] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[16]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[16]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[16]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[16]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[16]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[16]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[16]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[17] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[17] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[17]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[17]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[17]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[17]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[17]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[17]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[17]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[18] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[18] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[18]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[18]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[18]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[18]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[18]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[18]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[18]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[19] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[19] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[19]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[19]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[19]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[19]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[19]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[19]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[19]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[20] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[20] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[20]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[20]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[20]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[20]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[20]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[20]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[20]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[21] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[21] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[21]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[21]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[21]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[21]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[21]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[21]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[21]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[22] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[22] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[22]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[22]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[22]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[22]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[22]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[22]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[22]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[23] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[23] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[23]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[23]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[23]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[23]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[23]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[23]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[23]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[24] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[24] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[24]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[24]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[24]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[24]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[24]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[24]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[24]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[25] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[25] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[25]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[25]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[25]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[25]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[25]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[25]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[25]~_Duplicate_3 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[26] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AY ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[26] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[26]~_Duplicate_1 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[26]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_real_sq|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[26]~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[26]~_Duplicate_2 ; Q ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[26]~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|fxp_mult:mult_two_real_imag|Mult0~8 ; AX ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[26]~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|z_real[26]~_Duplicate_3 ; Q ; ;
; I2C_HDMI_Config:u_I2C_HDMI_Config|I2C_Controller:u0|I2C_WRITE_WDATA:wrd|SDAO ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; I2C_HDMI_Config:u_I2C_HDMI_Config|I2C_Controller:u0|I2C_WRITE_WDATA:wrd|SDAO~DUPLICATE ; ; ;
; counter[7] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; counter[7]~DUPLICATE ; ; ;
; counter[12] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; counter[12]~DUPLICATE ; ; ;
; counter[19] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; counter[19]~DUPLICATE ; ; ;
; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|framebuffer_dpram:fb|dpram:mem_64k|altsyncram:ram_rtl_0|altsyncram_gdn1:auto_generated|address_reg_b[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|framebuffer_dpram:fb|dpram:mem_64k|altsyncram:ram_rtl_0|altsyncram_gdn1:auto_generated|address_reg_b[1]~DUPLICATE ; ; ;
; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|framebuffer_dpram:fb|raddr[6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|framebuffer_dpram:fb|raddr[6]~DUPLICATE ; ; ;
; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|framebuffer_dpram:fb|raddr[15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|framebuffer_dpram:fb|raddr[15]~DUPLICATE ; ; ;
; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|framebuffer_dpram:fb|waddr[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|framebuffer_dpram:fb|waddr[2]~DUPLICATE ; ; ;
; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|framebuffer_dpram:fb|waddr[13] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|framebuffer_dpram:fb|waddr[13]~DUPLICATE ; ; ;
; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|framebuffer_dpram:fb|waddr[14] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|framebuffer_dpram:fb|waddr[14]~DUPLICATE ; ; ;
; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|h_count[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|h_count[1]~DUPLICATE ; ; ;
; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|h_count[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|h_count[2]~DUPLICATE ; ; ;
; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|h_count[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|h_count[4]~DUPLICATE ; ; ;
; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|h_count[8] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|h_count[8]~DUPLICATE ; ; ;
; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|h_count[9] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|h_count[9]~DUPLICATE ; ; ;
; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|pixel_x[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|pixel_x[0]~DUPLICATE ; ; ;
; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|pixel_x[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|pixel_x[1]~DUPLICATE ; ; ;
; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|pixel_x[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|pixel_x[2]~DUPLICATE ; ; ;
; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|pixel_x[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|pixel_x[3]~DUPLICATE ; ; ;
; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|pixel_x[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|pixel_x[4]~DUPLICATE ; ; ;
; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|pixel_x[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|pixel_x[5]~DUPLICATE ; ; ;
; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|pixel_x[6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|pixel_x[6]~DUPLICATE ; ; ;
; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|pixel_x[7] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|pixel_x[7]~DUPLICATE ; ; ;
; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|pixel_x[8] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|pixel_x[8]~DUPLICATE ; ; ;
; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|pixel_y[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|pixel_y[0]~DUPLICATE ; ; ;
; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|pixel_y[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|pixel_y[1]~DUPLICATE ; ; ;
; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|pixel_y[8] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|pixel_y[8]~DUPLICATE ; ; ;
; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|v_act ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|v_act~DUPLICATE ; ; ;
; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|v_count[6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|hdmi_display_sys:hdmi_driver_0|hdmi_tx:tx|v_count[6]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|avm_m0_writedata[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|avm_m0_writedata[4]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|avm_m0_writedata[7] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|avm_m0_writedata[7]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|avm_m0_writedata[8] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|avm_m0_writedata[8]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|avm_m0_writedata[9] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|avm_m0_writedata[9]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|avm_m0_writedata[19] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|avm_m0_writedata[19]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|avm_m0_writedata[20] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|avm_m0_writedata[20]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|avm_m0_writedata[21] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|avm_m0_writedata[21]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|c_im[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|c_im[5]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|c_im[16] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|c_im[16]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|c_re[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|c_re[0]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|c_re[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|c_re[1]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|c_re[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|c_re[2]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|c_re[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|c_re[4]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|c_re[6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|c_re[6]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|c_re[7] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|c_re[7]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|c_re[9] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|c_re[9]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|c_re[12] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|c_re[12]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|c_re[24] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|c_re[24]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|done ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|done~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|done ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|done~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|iter[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|iter[0]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|iter[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|iter[2]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|iter[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|iter[5]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|iter[6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|iter[6]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|state.FIN ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|mandelbrot_core:core|mandelbrot_calc:mandelbrot_inst|state.FIN~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|pix_x[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|pix_x[2]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|pix_x[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|pix_x[3]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|pix_x[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|pix_x[5]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|pix_y[7] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|pix_y[7]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|pix_y[9] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|pix_y[9]~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|start_en ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|start_en~DUPLICATE ; ; ;
; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|state.CALC ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; mandebrot_plot:u0|mand_total_sys:mand_total_single_sys_0|mandelbrot_single_sys:mand_sys|state.CALC~DUPLICATE ; ; ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+---------------------------------------------------+----------------------------+-----------+----------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+
+---------------------------------------------------------------------------------------------------+
; Incremental Compilation Preservation Summary ;
+---------------------+---------------------+----------------------------+--------------------------+
; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
+---------------------+---------------------+----------------------------+--------------------------+
; Placement (by node) ; ; ; ;
; -- Requested ; 0.00 % ( 0 / 1806 ) ; 0.00 % ( 0 / 1806 ) ; 0.00 % ( 0 / 1806 ) ;
; -- Achieved ; 0.00 % ( 0 / 1806 ) ; 0.00 % ( 0 / 1806 ) ; 0.00 % ( 0 / 1806 ) ;
; ; ; ; ;
; Routing (by net) ; ; ; ;
; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
+---------------------+---------------------+----------------------------+--------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Partition Settings ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Placement Preservation ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
; Top ; 0.00 % ( 0 / 1789 ) ; N/A ; Source File ; N/A ; ;
; hard_block:auto_generated_inst ; 0.00 % ( 0 / 17 ) ; N/A ; Source File ; N/A ; ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/software/verilog/MANDELBROT_HW/MANDELBROT_HW.pin.
+---------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+-------------------------------------------------------------+-----------------------+-------+
; Resource ; Usage ; % ;
+-------------------------------------------------------------+-----------------------+-------+
; Logic utilization (ALMs needed / total ALMs on device) ; 473 / 41,910 ; 1 % ;
; ALMs needed [=A-B+C] ; 473 ; ;
; [A] ALMs used in final placement [=a+b+c+d] ; 562 / 41,910 ; 1 % ;
; [a] ALMs used for LUT logic and registers ; 153 ; ;
; [b] ALMs used for LUT logic ; 299 ; ;
; [c] ALMs used for registers ; 110 ; ;
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;
; [B] Estimate of ALMs recoverable by dense packing ; 93 / 41,910 ; < 1 % ;
; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 4 / 41,910 ; < 1 % ;
; [a] Due to location constrained logic ; 0 ; ;
; [b] Due to LAB-wide signal conflicts ; 0 ; ;
; [c] Due to LAB input limits ; 4 ; ;
; [d] Due to virtual I/Os ; 0 ; ;
; ; ; ;
; Difficulty packing design ; Low ; ;
; ; ; ;
; Total LABs: partially or completely used ; 109 / 4,191 ; 3 % ;
; -- Logic LABs ; 109 ; ;
; -- Memory LABs (up to half of total LABs) ; 0 ; ;
; ; ; ;
; Combinational ALUT usage for logic ; 757 ; ;
; -- 7 input functions ; 13 ; ;
; -- 6 input functions ; 172 ; ;
; -- 5 input functions ; 99 ; ;
; -- 4 input functions ; 110 ; ;
; -- <=3 input functions ; 363 ; ;
; Combinational ALUT usage for route-throughs ; 118 ; ;
; ; ; ;
; Dedicated logic registers ; 607 ; ;
; -- By type: ; ; ;
; -- Primary logic registers ; 526 / 83,820 ; < 1 % ;
; -- Secondary logic registers ; 81 / 83,820 ; < 1 % ;
; -- By function: ; ; ;
; -- Design implementation registers ; 546 ; ;
; -- Routing optimization registers ; 61 ; ;
; ; ; ;
; Virtual pins ; 0 ; ;
; I/O pins ; 73 / 314 ; 23 % ;
; -- Clock pins ; 5 / 8 ; 63 % ;
; -- Dedicated input pins ; 0 / 21 ; 0 % ;
; ; ; ;
; Hard processor system peripheral utilization ; ; ;
; -- Boot from FPGA ; 0 / 1 ( 0 % ) ; ;
; -- Clock resets ; 0 / 1 ( 0 % ) ; ;
; -- Cross trigger ; 0 / 1 ( 0 % ) ; ;
; -- S2F AXI ; 0 / 1 ( 0 % ) ; ;
; -- F2S AXI ; 0 / 1 ( 0 % ) ; ;
; -- AXI Lightweight ; 0 / 1 ( 0 % ) ; ;
; -- SDRAM ; 0 / 1 ( 0 % ) ; ;
; -- Interrupts ; 0 / 1 ( 0 % ) ; ;
; -- JTAG ; 0 / 1 ( 0 % ) ; ;
; -- Loan I/O ; 0 / 1 ( 0 % ) ; ;
; -- MPU event standby ; 0 / 1 ( 0 % ) ; ;
; -- MPU general purpose ; 0 / 1 ( 0 % ) ; ;
; -- STM event ; 0 / 1 ( 0 % ) ; ;
; -- TPIU trace ; 0 / 1 ( 0 % ) ; ;
; -- DMA ; 0 / 1 ( 0 % ) ; ;
; -- CAN ; 0 / 2 ( 0 % ) ; ;
; -- EMAC ; 0 / 2 ( 0 % ) ; ;
; -- I2C ; 0 / 4 ( 0 % ) ; ;
; -- NAND Flash ; 0 / 1 ( 0 % ) ; ;
; -- QSPI ; 0 / 1 ( 0 % ) ; ;
; -- SDMMC ; 0 / 1 ( 0 % ) ; ;
; -- SPI Master ; 0 / 2 ( 0 % ) ; ;
; -- SPI Slave ; 0 / 2 ( 0 % ) ; ;
; -- UART ; 0 / 2 ( 0 % ) ; ;
; -- USB ; 0 / 2 ( 0 % ) ; ;
; ; ; ;
; M10K blocks ; 320 / 553 ; 58 % ;
; Total MLAB memory bits ; 0 ; ;
; Total block memory bits ; 2,621,440 / 5,662,720 ; 46 % ;
; Total block memory implementation bits ; 3,276,800 / 5,662,720 ; 58 % ;
; ; ; ;
; Total DSP Blocks ; 3 / 112 ; 3 % ;
; ; ; ;
; Fractional PLLs ; 2 / 6 ; 33 % ;
; Global signals ; 4 ; ;
; -- Global clocks ; 4 / 16 ; 25 % ;
; -- Quadrant clocks ; 0 / 66 ; 0 % ;
; -- Horizontal periphery clocks ; 0 / 18 ; 0 % ;
; SERDES Transmitters ; 0 / 100 ; 0 % ;
; SERDES Receivers ; 0 / 100 ; 0 % ;
; JTAGs ; 0 / 1 ; 0 % ;
; ASMI blocks ; 0 / 1 ; 0 % ;
; CRC blocks ; 0 / 1 ; 0 % ;
; Remote update blocks ; 0 / 1 ; 0 % ;
; Oscillator blocks ; 0 / 1 ; 0 % ;
; Impedance control blocks ; 0 / 4 ; 0 % ;
; Hard Memory Controllers ; 0 / 1 ; 0 % ;
; Average interconnect usage (total/H/V) ; 3.3% / 3.3% / 3.4% ; ;
; Peak interconnect usage (total/H/V) ; 12.8% / 12.1% / 14.9% ; ;
; Maximum fan-out ; 733 ; ;
; Highest non-global fan-out ; 640 ; ;
; Total fan-out ; 14732 ; ;
; Average fan-out ; 7.42 ; ;
+-------------------------------------------------------------+-----------------------+-------+
+----------------------------------------------------------------------------------------------------------------------+
; Fitter Partition Statistics ;
+-------------------------------------------------------------+-----------------------+--------------------------------+
; Statistic ; Top ; hard_block:auto_generated_inst ;
+-------------------------------------------------------------+-----------------------+--------------------------------+
; Logic utilization (ALMs needed / total ALMs on device) ; 473 / 41910 ( 1 % ) ; 0 / 41910 ( 0 % ) ;
; ALMs needed [=A-B+C] ; 473 ; 0 ;
; [A] ALMs used in final placement [=a+b+c+d] ; 562 / 41910 ( 1 % ) ; 0 / 41910 ( 0 % ) ;
; [a] ALMs used for LUT logic and registers ; 153 ; 0 ;
; [b] ALMs used for LUT logic ; 299 ; 0 ;
; [c] ALMs used for registers ; 110 ; 0 ;
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ;
; [B] Estimate of ALMs recoverable by dense packing ; 93 / 41910 ( < 1 % ) ; 0 / 41910 ( 0 % ) ;
; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 4 / 41910 ( < 1 % ) ; 0 / 41910 ( 0 % ) ;
; [a] Due to location constrained logic ; 0 ; 0 ;
; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ;
; [c] Due to LAB input limits ; 4 ; 0 ;
; [d] Due to virtual I/Os ; 0 ; 0 ;
; ; ; ;
; Difficulty packing design ; Low ; Low ;
; ; ; ;
; Total LABs: partially or completely used ; 109 / 4191 ( 3 % ) ; 0 / 4191 ( 0 % ) ;
; -- Logic LABs ; 109 ; 0 ;
; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ;
; ; ; ;
; Combinational ALUT usage for logic ; 757 ; 0 ;
; -- 7 input functions ; 13 ; 0 ;
; -- 6 input functions ; 172 ; 0 ;
; -- 5 input functions ; 99 ; 0 ;
; -- 4 input functions ; 110 ; 0 ;
; -- <=3 input functions ; 363 ; 0 ;
; Combinational ALUT usage for route-throughs ; 118 ; 0 ;
; Memory ALUT usage ; 0 ; 0 ;
; -- 64-address deep ; 0 ; 0 ;
; -- 32-address deep ; 0 ; 0 ;
; ; ; ;
; Dedicated logic registers ; 0 ; 0 ;
; -- By type: ; ; ;
; -- Primary logic registers ; 526 / 83820 ( < 1 % ) ; 0 / 83820 ( 0 % ) ;
; -- Secondary logic registers ; 81 / 83820 ( < 1 % ) ; 0 / 83820 ( 0 % ) ;
; -- By function: ; ; ;
; -- Design implementation registers ; 546 ; 0 ;
; -- Routing optimization registers ; 61 ; 0 ;
; ; ; ;
; ; ; ;
; Virtual pins ; 0 ; 0 ;
; I/O pins ; 70 ; 3 ;
; I/O registers ; 0 ; 0 ;
; Total block memory bits ; 2621440 ; 0 ;
; Total block memory implementation bits ; 3276800 ; 0 ;
; M10K block ; 320 / 553 ( 57 % ) ; 0 / 553 ( 0 % ) ;
; DSP block ; 3 / 112 ( 2 % ) ; 0 / 112 ( 0 % ) ;
; Clock enable block ; 1 / 116 ( < 1 % ) ; 3 / 116 ( 2 % ) ;
; Fractional PLL ; 0 / 6 ( 0 % ) ; 2 / 6 ( 33 % ) ;
; PLL Output Counter ; 0 / 54 ( 0 % ) ; 2 / 54 ( 3 % ) ;
; PLL Reconfiguration Block ; 0 / 6 ( 0 % ) ; 2 / 6 ( 33 % ) ;
; PLL Reference Clock Select Block ; 0 / 6 ( 0 % ) ; 2 / 6 ( 33 % ) ;
; ; ; ;
; Connections ; ; ;
; -- Input Connections ; 1051 ; 0 ;
; -- Registered Input Connections ; 696 ; 0 ;
; -- Output Connections ; 23 ; 1028 ;
; -- Registered Output Connections ; 0 ; 0 ;
; ; ; ;
; Internal Connections ; ; ;
; -- Total Connections ; 19614 ; 1097 ;
; -- Registered Connections ; 16409 ; 0 ;
; ; ; ;
; External Connections ; ; ;
; -- Top ; 46 ; 1028 ;
; -- hard_block:auto_generated_inst ; 1028 ; 0 ;
; ; ; ;
; Partition Interface ; ; ;
; -- Input Ports ; 11 ; 2 ;
; -- Output Ports ; 39 ; 5 ;
; -- Bidir Ports ; 23 ; 0 ;
; ; ; ;
; Registered Ports ; ; ;
; -- Registered Input Ports ; 0 ; 0 ;
; -- Registered Output Ports ; 0 ; 0 ;
; ; ; ;
; Port Connectivity ; ; ;
; -- Input Ports driven by GND ; 0 ; 0 ;
; -- Output Ports driven by GND ; 0 ; 0 ;
; -- Input Ports driven by VCC ; 0 ; 0 ;
; -- Output Ports driven by VCC ; 0 ; 0 ;
; -- Input Ports with no Source ; 0 ; 0 ;
; -- Output Ports with no Source ; 0 ; 0 ;
; -- Input Ports with no Fanout ; 0 ; 0 ;
; -- Output Ports with no Fanout ; 0 ; 0 ;
+-------------------------------------------------------------+-----------------------+--------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
+--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
; ADC_SDO ; AD4 ; 3A ; 6 ; 0 ; 51 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
; FPGA_CLK1_50 ; V11 ; 3B ; 32 ; 0 ; 0 ; 32 ; 0 ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
; FPGA_CLK2_50 ; Y13 ; 4A ; 56 ; 0 ; 0 ; 17 ; 0 ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
; FPGA_CLK3_50 ; E11 ; 8A ; 32 ; 81 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
; HDMI_TX_INT ; AF11 ; 3B ; 34 ; 0 ; 40 ; 5 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
; KEY[0] ; AH17 ; 4A ; 64 ; 0 ; 34 ; 1 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
; KEY[1] ; AH16 ; 4A ; 64 ; 0 ; 51 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
; SW[0] ; Y24 ; 5B ; 89 ; 25 ; 3 ; 3 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
; SW[1] ; W24 ; 5B ; 89 ; 25 ; 20 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
; SW[2] ; W21 ; 5B ; 89 ; 23 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
; SW[3] ; W20 ; 5B ; 89 ; 23 ; 20 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
+--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins ;
+---------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
+---------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
; ADC_CONVST ; U9 ; 3A ; 4 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; ADC_SCK ; V10 ; 3A ; 6 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; ADC_SDI ; AC4 ; 3A ; 6 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_CLK ; AG5 ; 3B ; 38 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_DE ; AD19 ; 4A ; 66 ; 0 ; 57 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_D[0] ; AD12 ; 3B ; 38 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_D[10] ; AE9 ; 3B ; 26 ; 0 ; 57 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_D[11] ; AB4 ; 3A ; 4 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_D[12] ; AE7 ; 3B ; 28 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_D[13] ; AF6 ; 3B ; 32 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_D[14] ; AF8 ; 3B ; 28 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_D[15] ; AF5 ; 3B ; 32 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_D[16] ; AE4 ; 3B ; 26 ; 0 ; 74 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_D[17] ; AH2 ; 3B ; 36 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_D[18] ; AH4 ; 3B ; 38 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_D[19] ; AH5 ; 3B ; 40 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_D[1] ; AE12 ; 3B ; 38 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_D[20] ; AH6 ; 3B ; 40 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_D[21] ; AG6 ; 3B ; 34 ; 0 ; 91 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_D[22] ; AF9 ; 3B ; 30 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_D[23] ; AE8 ; 3B ; 30 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_D[2] ; W8 ; 3A ; 2 ; 0 ; 40 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_D[3] ; Y8 ; 3A ; 2 ; 0 ; 57 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_D[4] ; AD11 ; 3B ; 30 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_D[5] ; AD10 ; 3B ; 26 ; 0 ; 40 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_D[6] ; AE11 ; 3B ; 30 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_D[7] ; Y5 ; 3A ; 2 ; 0 ; 74 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_D[8] ; AF10 ; 3B ; 34 ; 0 ; 57 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_D[9] ; Y4 ; 3A ; 2 ; 0 ; 91 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_HS ; T8 ; 3A ; 4 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; HDMI_TX_VS ; V13 ; 4A ; 60 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; LED[0] ; W15 ; 5A ; 89 ; 8 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; LED[1] ; AA24 ; 5A ; 89 ; 9 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; LED[2] ; V16 ; 5A ; 89 ; 9 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; LED[3] ; V15 ; 5A ; 89 ; 9 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; LED[4] ; AF26 ; 5A ; 89 ; 4 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; LED[5] ; AE26 ; 5A ; 89 ; 4 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; LED[6] ; Y16 ; 5A ; 89 ; 8 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
; LED[7] ; AA23 ; 5A ; 89 ; 9 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
+---------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Bidir Pins ;
+-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+-------------------+--------------------+---------------------------+----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------------------------------------------------------------------------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Input Termination ; Output Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
+-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+-------------------+--------------------+---------------------------+----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------------------------------------------------------------------------------------+
; ARDUINO_IO[0] ; AG13 ; 4A ; 50 ; 0 ; 40 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; no ; 0 ; Off ; User ; 0 pF ; - ;
; ARDUINO_IO[10] ; AF15 ; 4A ; 54 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; no ; 0 ; Off ; User ; 0 pF ; - ;
; ARDUINO_IO[11] ; AG16 ; 4A ; 58 ; 0 ; 57 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; no ; 0 ; Off ; User ; 0 pF ; - ;
; ARDUINO_IO[12] ; AH11 ; 4A ; 56 ; 0 ; 51 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; no ; 0 ; Off ; User ; 0 pF ; - ;
; ARDUINO_IO[13] ; AH12 ; 4A ; 58 ; 0 ; 74 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; no ; 0 ; Off ; User ; 0 pF ; - ;
; ARDUINO_IO[14] ; AH9 ; 4A ; 54 ; 0 ; 51 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; no ; 0 ; Off ; User ; 0 pF ; - ;
; ARDUINO_IO[15] ; AG11 ; 4A ; 56 ; 0 ; 34 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; no ; 0 ; Off ; User ; 0 pF ; - ;
; ARDUINO_IO[1] ; AF13 ; 4A ; 50 ; 0 ; 57 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; no ; 0 ; Off ; User ; 0 pF ; - ;
; ARDUINO_IO[2] ; AG10 ; 4A ; 54 ; 0 ; 34 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; no ; 0 ; Off ; User ; 0 pF ; - ;
; ARDUINO_IO[3] ; AG9 ; 4A ; 52 ; 0 ; 34 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; no ; 0 ; Off ; User ; 0 pF ; - ;
; ARDUINO_IO[4] ; U14 ; 4A ; 52 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; no ; 0 ; Off ; User ; 0 pF ; - ;
; ARDUINO_IO[5] ; U13 ; 4A ; 52 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; no ; 0 ; Off ; User ; 0 pF ; - ;
; ARDUINO_IO[6] ; AG8 ; 4A ; 50 ; 0 ; 74 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; no ; 0 ; Off ; User ; 0 pF ; - ;
; ARDUINO_IO[7] ; AH8 ; 4A ; 52 ; 0 ; 51 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; no ; 0 ; Off ; User ; 0 pF ; - ;
; ARDUINO_IO[8] ; AF17 ; 4A ; 58 ; 0 ; 40 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; no ; 0 ; Off ; User ; 0 pF ; - ;
; ARDUINO_IO[9] ; AE15 ; 4A ; 54 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; no ; 0 ; Off ; User ; 0 pF ; - ;
; ARDUINO_RESET_N ; AH7 ; 4A ; 50 ; 0 ; 91 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; no ; 0 ; Off ; User ; 0 pF ; - ;
; HDMI_I2C_SCL ; U10 ; 3A ; 6 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; no ; 0 ; Off ; User ; 0 pF ; - ;
; HDMI_I2C_SDA ; AA4 ; 3A ; 4 ; 0 ; 34 ; 1 ; 0 ; no ; no ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; no ; 0 ; Off ; User ; 0 pF ; I2C_HDMI_Config:u_I2C_HDMI_Config|I2C_Controller:u0|I2C_WRITE_WDATA:wrd|SDAO~DUPLICATE (inverted) ;
; HDMI_I2S ; T13 ; 3B ; 36 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; no ; 0 ; Off ; User ; 0 pF ; - ;
; HDMI_LRCLK ; T11 ; 3B ; 28 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; no ; 0 ; Off ; User ; 0 pF ; - ;
; HDMI_MCLK ; U11 ; 3B ; 28 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; no ; 0 ; Off ; User ; 0 pF ; - ;
; HDMI_SCLK ; T12 ; 3B ; 36 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; 1 ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; Off ; -- ; no ; 0 ; Off ; User ; 0 pF ; - ;
+-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+-------------------+--------------------+---------------------------+----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------------------------------------------------------------------------------------+
+----------------------------------------------------------------------------+
; I/O Bank Usage ;
+----------+------------------+---------------+--------------+---------------+
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
+----------+------------------+---------------+--------------+---------------+
; B2L ; 0 / 0 ( -- ) ; -- ; -- ; -- ;
; B1L ; 0 / 0 ( -- ) ; -- ; -- ; -- ;
; 3A ; 12 / 16 ( 75 % ) ; 3.3V ; -- ; 3.3V ;
; 3B ; 26 / 32 ( 81 % ) ; 3.3V ; -- ; 3.3V ;
; 4A ; 22 / 68 ( 32 % ) ; 3.3V ; -- ; 3.3V ;
; 5A ; 8 / 16 ( 50 % ) ; 3.3V ; -- ; 3.3V ;
; 5B ; 4 / 7 ( 57 % ) ; 3.3V ; -- ; 3.3V ;
; 6B ; 0 / 44 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
; 6A ; 0 / 56 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
; 7A ; 0 / 19 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
; 7B ; 0 / 22 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
; 7C ; 0 / 12 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
; 7D ; 0 / 14 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
; 8A ; 1 / 6 ( 17 % ) ; 3.3V ; -- ; 3.3V ;
+----------+------------------+---------------+--------------+---------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins ;
+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
; A2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
; A3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; A4 ; 435 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; A5 ; 431 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; A6 ; 425 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; A7 ; 423 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; A8 ; 421 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; A9 ; 419 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; A10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; A11 ; 417 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; A12 ; 415 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; A13 ; 413 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; A14 ; 411 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; A15 ; 409 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; A16 ; 407 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; A17 ; 399 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; A18 ; 395 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; A19 ; 393 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; A20 ; 391 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; A21 ; 389 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; A22 ; 387 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; A23 ; 374 ; 7A ; ^HPS_nRST ; ; ; ; -- ; ; -- ; -- ;
; A24 ; 361 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; A25 ; 359 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; A26 ; 357 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; A27 ; 353 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; AA1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AA3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AA4 ; 59 ; 3A ; HDMI_I2C_SDA ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; AA5 ; ; 3A ; VCCIO3A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; AA6 ; 43 ; 3A ; ^nCSO, DATA4 ; ; ; ; Weak Pull Up ; ; -- ; On ;
; AA8 ; 50 ; 3A ; ^DCLK ; ; ; ; Weak Pull Up ; ; -- ; On ;
; AA9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AA10 ; ; 3A ; VCCPD3A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; AA11 ; 64 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AA12 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; AA13 ; 144 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AA14 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; AA15 ; 160 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AA16 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; AA17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AA18 ; 168 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AA19 ; 170 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AA20 ; 213 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; AA21 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; AA23 ; 226 ; 5A ; LED[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; AA24 ; 224 ; 5A ; LED[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; AA25 ; ; 5B ; VREFB5BN0 ; power ; ; ; -- ; ; -- ; -- ;
; AA26 ; 255 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; AA27 ; 279 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; AA28 ; 289 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AB2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AB3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AB4 ; 57 ; 3A ; HDMI_TX_D[11] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; AB5 ; 46 ; 3A ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
; AB6 ; 45 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ;
; AB23 ; 222 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; AB24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AB25 ; 259 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; AB26 ; 253 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; AB27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AB28 ; 277 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; AC1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AC2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AC3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; AC4 ; 63 ; 3A ; ADC_SDI ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; AC5 ; 47 ; 3A ; ^AS_DATA2, DATA2 ; ; ; ; Weak Pull Up ; ; -- ; On ;
; AC6 ; 49 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ;
; AC7 ; 44 ; 3A ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
; AC8 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; AC21 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
; AC22 ; 202 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AC23 ; 200 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; AC24 ; 220 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; AC25 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; AC26 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ;
; AC27 ; 275 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; AC28 ; 273 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
; AD1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
; AD2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
; AD3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;