build-ram.ys

# read design 
read_verilog ExternalRam.v

# elaborate design hierarchy
hierarchy -check -top ExternalRam

# the high-level stuff
proc; opt; fsm; opt; memory; opt

# mapping to internal cell library
techmap; opt

#To make easy to parse for V2TT
flatten;

# mapping logic to gates.
abc -g gates,MUX

# cleanup
clean -purge

# write synthesized design
write_json ram-16bit.json