From 3179b51ad2efc39230820015a5dce76cccb0896e Mon Sep 17 00:00:00 2001
From: Iztok Jeras <iztok.jeras@redpitaya.com>
Date: Wed, 22 Mar 2017 17:56:28 +0100
Subject: [PATCH] FPGA: renamed logic_orig into logic

---
 Makefile.x86                                         | 6 +++---
 TODO.md                                              | 1 -
 fpga/fpga.rst                                        | 2 +-
 fpga/prj/{logic_orig => logic}/dts/fpga.dts          | 0
 fpga/prj/{logic_orig => logic}/ip/system.tcl         | 0
 fpga/prj/{logic_orig => logic}/rtl/red_pitaya_ps.sv  | 0
 fpga/prj/{logic_orig => logic}/rtl/red_pitaya_top.sv | 0
 7 files changed, 4 insertions(+), 5 deletions(-)
 rename fpga/prj/{logic_orig => logic}/dts/fpga.dts (100%)
 rename fpga/prj/{logic_orig => logic}/ip/system.tcl (100%)
 rename fpga/prj/{logic_orig => logic}/rtl/red_pitaya_ps.sv (100%)
 rename fpga/prj/{logic_orig => logic}/rtl/red_pitaya_top.sv (100%)

diff --git a/Makefile.x86 b/Makefile.x86
index 467804453..264f554fd 100644
--- a/Makefile.x86
+++ b/Makefile.x86
@@ -84,8 +84,8 @@ UBOOT_CFLAGS = "-O2 -mtune=cortex-a9 -mfpu=neon -mfloat-abi=hard"
 
 FPGA_TAR = fpga.zip
 
-FPGA_PRJ_LST = classic logic_orig v0.94 axi4lite mercury
-FPGA_PRJ = logic_orig
+FPGA_PRJ_LST = classic logic v0.94 axi4lite mercury
+FPGA_PRJ = logic
 
 .PHONY: fpga fpga_all
 
@@ -99,7 +99,7 @@ $(INSTALL_DIR)/fpga: | $(FPGA_TAR)
 	cp fpga/archive/*.xz  $(INSTALL_DIR)/fpga
 	cd                    $(INSTALL_DIR)/fpga; xz -df *.xz
 	# backward compatibility, TODO, should be removed at next OS release
-	cp $(INSTALL_DIR)/fpga/logic_orig/fpga.bit  $(INSTALL_DIR)/fpga/fpga_la.bit
+	cp $(INSTALL_DIR)/fpga/logic/fpga.bit  $(INSTALL_DIR)/fpga/fpga_la.bit
 	cp $(INSTALL_DIR)/fpga/v0.94/fpga.bit       $(INSTALL_DIR)/fpga/fpga_0.94.bit
 	cp $(INSTALL_DIR)/fpga/classic/fpga.bit     $(INSTALL_DIR)/fpga/fpga_classic.bit
 
diff --git a/TODO.md b/TODO.md
index 027ace05c..137020ed9 100644
--- a/TODO.md
+++ b/TODO.md
@@ -6,7 +6,6 @@ Jupyter:
 - there is this error in the log:
   `404 GET /jupyter/nbextensions/widgets/notebook/js/extension.js`
   so some widgets are not working
-- use generator/acquire from logic_orig
 - rethink start/trigger/stop synchronization
 - each channel should have own UIO DT node and driver,
   so they could be used by separate applications
diff --git a/fpga/fpga.rst b/fpga/fpga.rst
index bcd6f79ba..21dc9f0b4 100644
--- a/fpga/fpga.rst
+++ b/fpga/fpga.rst
@@ -90,7 +90,7 @@ on the first Red Pitaya release.
 |                   |    Linux kernel features for GPIO (IRQ, SPI, I2C, 1-wire) and    |
 |                   |    LED (triggers).                                               |
 +-------------------+------------------------------------------------------------------+
-| logic_orig        | This image is used by the logic analyzer, it is using DMA to     |
+| logic             | This image is used by the logic analyzer, it is using DMA to     |
 |                   | transfer data to man DDR3 RAM. ADC and DAS code is unfinished.   |
 +-------------------+------------------------------------------------------------------+
 | axi4lite          | Image intended for testing various AXI4 bus implementations.     |
diff --git a/fpga/prj/logic_orig/dts/fpga.dts b/fpga/prj/logic/dts/fpga.dts
similarity index 100%
rename from fpga/prj/logic_orig/dts/fpga.dts
rename to fpga/prj/logic/dts/fpga.dts
diff --git a/fpga/prj/logic_orig/ip/system.tcl b/fpga/prj/logic/ip/system.tcl
similarity index 100%
rename from fpga/prj/logic_orig/ip/system.tcl
rename to fpga/prj/logic/ip/system.tcl
diff --git a/fpga/prj/logic_orig/rtl/red_pitaya_ps.sv b/fpga/prj/logic/rtl/red_pitaya_ps.sv
similarity index 100%
rename from fpga/prj/logic_orig/rtl/red_pitaya_ps.sv
rename to fpga/prj/logic/rtl/red_pitaya_ps.sv
diff --git a/fpga/prj/logic_orig/rtl/red_pitaya_top.sv b/fpga/prj/logic/rtl/red_pitaya_top.sv
similarity index 100%
rename from fpga/prj/logic_orig/rtl/red_pitaya_top.sv
rename to fpga/prj/logic/rtl/red_pitaya_top.sv