diff --git a/Applications b/Applications index 15fbd007c..b50f2409f 160000 --- a/Applications +++ b/Applications @@ -1 +1 @@ -Subproject commit 15fbd007cc7246e710f0b0f39f91d9f824a42f48 +Subproject commit b50f2409fddc9092c307e0fdde4ae2f833e0ab72 diff --git a/Bazaar/nginx/ngx_ext_modules/ngx_http_rp_module/config b/Bazaar/nginx/ngx_ext_modules/ngx_http_rp_module/config index d8d4d2409..587857add 100644 --- a/Bazaar/nginx/ngx_ext_modules/ngx_http_rp_module/config +++ b/Bazaar/nginx/ngx_ext_modules/ngx_http_rp_module/config @@ -22,7 +22,7 @@ NGX_ADDON_SRCS="$NGX_ADDON_SRCS \ $rp_src_dir/rp_data_cmd.c \ $rp_src_dir/cJSON.c" -CORE_LIBS="$CORE_LIBS -Wl,--no-as-needed -L$ngx_addon_dir/../ws_server -lws_server -lm -ldl -lssl -lcryptopp -lcurl -lboost_system -lboost_regex -lboost_thread" +CORE_LIBS="$CORE_LIBS -Wl,--no-as-needed -L$ngx_addon_dir/../ws_server -lws_server -lm -ldl -lcryptopp -lcurl -lboost_system -lboost_regex -lboost_thread" CFLAGS="$CFLAGS -I $rp_include_dir -I$ngx_addon_dir/../ws_server" CFLAGS="$CFLAGS -DVERSION=$VERSION -DREVISION=$REVISION" diff --git a/Bazaar/nginx/ngx_ext_modules/ngx_http_rp_module/src/rp_bazaar_cmd.c b/Bazaar/nginx/ngx_ext_modules/ngx_http_rp_module/src/rp_bazaar_cmd.c index f3e4db091..88ddae5ea 100644 --- a/Bazaar/nginx/ngx_ext_modules/ngx_http_rp_module/src/rp_bazaar_cmd.c +++ b/Bazaar/nginx/ngx_ext_modules/ngx_http_rp_module/src/rp_bazaar_cmd.c @@ -456,8 +456,8 @@ int rp_bazaar_start(ngx_http_request_t *r, /* Get FPGA config file in //fpga.conf */ char *fpga_name = NULL; - if (system("/opt/redpitaya/rmamba_pl.sh")) - fprintf(stderr, "Problem running /opt/redpitaya/rmamba_pl.sh\n"); + if (system("/opt/redpitaya/sbin/rmoverlay.sh")) + fprintf(stderr, "Problem running /opt/redpitaya/sbin/rmoverlay.sh\n"); if(get_fpga_path((const char *)argv[0], (const char *)lc->bazaar_dir.data, &fpga_name) == 0) { // FIXME !!! /* Here we do not have application running anymore - load new FPGA */ fprintf(stderr, "Loading specific FPGA from: '%s'\n", fpga_name); diff --git a/Test/uio/Makefile b/Examples/gpio_sysfs/Makefile similarity index 61% rename from Test/uio/Makefile rename to Examples/gpio_sysfs/Makefile index 50bf7165f..f65332342 100644 --- a/Test/uio/Makefile +++ b/Examples/gpio_sysfs/Makefile @@ -1,16 +1,12 @@ -#Cross compiler definition CC = $(CROSS_COMPILE)gcc CFLAGS = -g -std=gnu99 -Wall -Werror -CFLAGS += -I../include -CFLAGS += -I../src -I../include -CFLAGS += -L ../lib -lm -lpthread +CFLAGS += -lm -lpthread SRCS=$(wildcard *.c) OBJS=$(SRCS:.c=) all: $(OBJS) - %.o: %.c $(CC) -c $(CFLAGS) $< -o $@ diff --git a/Examples/gpio_sysfs/README b/Examples/gpio_sysfs/README new file mode 100644 index 000000000..63f8655b7 --- /dev/null +++ b/Examples/gpio_sysfs/README @@ -0,0 +1,21 @@ +Simple C gpio test application shows how to export/unexport different pins and +set direction on exported pins. + +Requierment for using sysfs gpio interface for working with gpios is to load appropriate fpga bitstream +/opt/redpitaya/fpga/classic/fpga.bit and /opt/redpitaya/mercury/fpga.bit fit that requierments. +You can load bitstream using "cat /opt/redpitaya/fpga/classic/fpga.bit > /dev/xdevcfg" command. + +Usaly exporting and setting direction to pins is done in external script that sets up all +required gpio in this example that is done using "system" call(same can also be achived using calls to functions open read and write). + +Actual read and writes on /sys/class/gpio/gpio_PIN_NO_/value (where _PIN_NO_ represents pin number of +exported pin) is done with simple open, read and write comands. + +If you connect pins DIO0_N to DIO0_P using jumper wire, value read from PIN DIO0_P +should match value written to POUT DIO0_P. + +Documentation related to numbering of GPIO pins on redpitaya board is available at: +https://github.com/RedPitaya/RedPitaya/blob/master/doc/developerGuide/gpio/gpio.rst + +General documentation related to gpio/sysfs interface is available at: +https://github.com/RedPitaya/linux-xlnx/blob/master/Documentation/gpio/sysfs.txt diff --git a/Examples/gpio_sysfs/gpioblink.c b/Examples/gpio_sysfs/gpioblink.c new file mode 100644 index 000000000..9c9ecaa07 --- /dev/null +++ b/Examples/gpio_sysfs/gpioblink.c @@ -0,0 +1,135 @@ +#include +#include +#include +#include +#include +#include + +#define IN 0 +#define OUT 1 + +#define LOW 0 +#define HIGH 1 + +#define PIN 976 +#define POUT 968 + +#define VALUE_MAX 30 +#define BUFFER_MAX 3 + +#define MAX_PATH 64 + + +static int pin_export(int pin) +{ + char shell[MAX_PATH]; + sprintf(shell,"echo %d > /sys/class/gpio/export", pin); + system(shell); + return 0; +} + +static int pin_unexport(int pin) +{ + char shell[MAX_PATH]; + sprintf(shell,"echo %d > /sys/class/gpio/unexport", pin); + system(shell); + + return 0; +} + +static int pin_direction(int pin, int dir){ + + char shell[MAX_PATH]; + snprintf(shell, MAX_PATH, "echo %s > /sys/class/gpio/gpio%d/direction",((dir==IN)?"in":"out"),pin); + system(shell); + + return 0; +} + +static int pin_read(int pin){ + + char path[VALUE_MAX]; + char value_str[3]; + int fd; + + snprintf(path, VALUE_MAX, "/sys/class/gpio/gpio%d/value", pin); + + // get pin file descriptor for reading its state + fd = open(path, O_RDONLY); + if (-1 == fd) { + fprintf(stderr, "Unable to open gpio sysfs pin value file %s for reading\n",path); + return -1; + } + + // read value + if (-1 == read(fd, value_str, 3)) { + fprintf(stderr, "Unable to read value\n"); + return -1; + } + + // close file + close(fd); + + // return integar value + return atoi(value_str); +} + +static int pin_write(int pin, int value) +{ + char path[VALUE_MAX]; + int fd; + + snprintf(path, VALUE_MAX, "/sys/class/gpio/gpio%d/value", pin); + // get pin value file descrptor + fd = open(path, O_WRONLY); + if (-1 == fd) { + fprintf(stderr, "Unable to to open sysfs pins value file %s for writing\n",path); + return -1; + } + if(value==LOW){ + //write low + if (1 != write(fd, "0", 1)) { + fprintf(stderr, "Unable to write value\n"); + return -1; + } + } + else if(value==HIGH){ + //write high + if (1 != write(fd, "1", 1)) { + fprintf(stderr, "Unable to write value\n"); + return -1; + } + }else fprintf(stderr, "Nonvalid pin value requested\n"); + + //close file + close(fd); + return 0; +} + +int main(int argc, char *argv[]) +{ + // apply required fpga bitstream mercury or classic + // system("cat /opt/redpitaya/fpga/fpga_classic.bit > /dev/xdevcfg"); + + int repeat = 10; + if (argc==2) + repeat=atoi(argv[1]); + // export pins + if (-1 == pin_export(POUT) || -1 == pin_export(PIN)) return 1; + + // set pin direction + if (-1 == pin_direction(POUT, OUT) || -1 == pin_direction(PIN, IN)) return 2; + int i; + for (i = 1; i <= repeat; i++){ + // set pin value + if (-1 == pin_write( POUT, i % 2)) return 3; + printf("Setting pin %d to %d\n", POUT,i % 2); + // read and printout pin value + printf("Reading pin %d got %d\n", PIN,pin_read(PIN)); + usleep(10000); + } + // unexport pins on exit + if (-1 == pin_unexport(POUT) || -1 == pin_unexport(PIN)) + return 4; + return 0; +} diff --git a/Examples/scpi/MATLAB/gen_arbitrary_signal.m b/Examples/scpi/MATLAB/gen_arbitrary_signal.m index 61ce5df63..f6a7c8b44 100644 --- a/Examples/scpi/MATLAB/gen_arbitrary_signal.m +++ b/Examples/scpi/MATLAB/gen_arbitrary_signal.m @@ -1,61 +1,77 @@ % %% Define Red Pitaya as TCP/IP object clc close all -IP= '192.168.178.103'; % Input IP of your Red Pitaya... +% IP= '192.168.101.108'; % IP of your Red Pitaya... +IP= 'rp-f01b63.local'; % rp-MAC.local MAC are the last 6 characters of your Red Pitaya port = 5000; % If you are using WiFi then IP is: -RP=tcpip(IP, port,'OutputBufferSize',32784*5); % 192.168.128.1 - +RP=tcpip(IP, port,'OutputBufferSize',32784*5); fopen(RP); RP.Terminator = 'CR/LF'; %% Prepare an arbitrary waveform -% Values of arbitrary waveform must be in range from -1 to 1. -length = 2^14; + +% select data transmittion BIN/ASCII (0 - binary, any other value - ASCII) +bin=1; +% select buffer length (max = 2^14) +length = 2^3; +% STEMlab 14 - 1 sign + 13 data bits +bitsize= 0; % generates x axis in range 0 to 6 with length number of points X0=0; -XN=6; +XN=length-1; x = X0:(XN-X0)/(length-1):XN ; +% Values of arbitrary waveform must be in range from -1 to 1. y1 = 0.8 * sin(x); % the first sinus signal with the amplitude 0.8 y2 = 0.2 * sin(21*x); % the second sinus signal with a frequency 20 times higher than the first one and the amplitude of 0.2 -y_sum = y1+y2; +% y2 = 0.2 * sin(5*x); % the second sinus signal with a frequency 20 times higher than the first one and the amplitude of 0.2 +y_sum = x; -% plot(x,y_sum); +% uncomment the following line to show the plot of the arbitrary function +plot(x,y_sum); %% transmit data and configure genertor -%%% transmit data in binary format -% binary write still needs to be debuged -% disp(y_sum) -% binblockwrite(RP, y_sum,'int16','SOURce1:TRACe:DATA:RAW '); -% fprintf(RP,'\n'); - -%%% transmit data in ascii format -% convert float to string -waveform_ch_1_0 = num2str(y_sum,'%1.5f,'); -% remove the last “,”. -waveform_ch_1 = waveform_ch_1_0(1,1: size(waveform_ch_1_0,2)-3); - % set output amplitude and offset fprintf(RP,'SOURce1:VOLTage:IMMediate:AMPlitude 1'); fprintf(RP,'SOURce1:VOLTage:IMMediate:OFFSet 0'); -% # specify peridic mode, sinusoidal waveform and 1kHZ frequency +% specify peridic mode fprintf(RP,'SOURce1:MODE PERiodic'); -fprintf(RP,['SOURce1:TRACe:DATA:DATA ' waveform_ch_1]); -fprintf(RP,'SOURce1:FREQuency:FIXed 1000'); -% -% # reset and start state machine +%%% transmit arbitrary waveform in either BINARY or ASCII format +if bin + disp('INFO: Sending data in BINARY format'); + binblockwrite(RP, y_sum * (2^bitsize),'int16','SOURce1:TRACe:DATA:RAW '); + fprintf(RP,''); %binblockwrite does not complete with /n, hence one is added here + + y_sum * (2^bitsize) + fprintf(RP,'SOURce1:TRACe:DATA:RAW? 8 '); + data1 = binblockread(RP,'int16') +else + disp('INFO: Sending data in ASCII format'); + % convert float to string + waveform_ch_1_0 = num2str(y_sum,'%1.5f,'); + % remove the last “,”. + waveform_ch_1 = waveform_ch_1_0(1,1: size(waveform_ch_1_0,2)-1); + fprintf(RP,['SOURce1:TRACe:DATA:DATA ' waveform_ch_1]); +end + +% set 1kHZ frequency +fprintf(RP,'SOURce1:FREQuency:FIXed 2000'); + +% reset and start state machine fprintf(RP,'SOURce1:RESET'); fprintf(RP,'SOURce1:START'); -% + % # enable output fprintf(RP,'OUTPUT1:STATe ON'); -% + % # trigger state machine fprintf(RP,'SOURce1:TRIGger'); +% RA = binblockread(RP,'int16'); + %% Close connection to the Red Pitaya fclose(RP); diff --git a/Examples/scpi/MATLAB/gen_burst.m b/Examples/scpi/MATLAB/gen_burst.m index a768af582..b16490b0d 100644 --- a/Examples/scpi/MATLAB/gen_burst.m +++ b/Examples/scpi/MATLAB/gen_burst.m @@ -1,9 +1,10 @@ %% Define Red Pitaya as TCP/IP object clc close all -IP= '192.168.178.103'; % Input IP of your Red Pitaya... +% IP= '192.168.101.108'; % IP of your Red Pitaya... +IP= 'rp-f01b63.local'; % rp-MAC.local MAC are the last 6 characters of your Red Pitaya port = 5000; % If you are using WiFi then IP is: -RP=tcpip(IP, port); % 192.168.128.1 +RP=tcpip(IP, port); fopen(RP); RP.Terminator = 'CR/LF'; diff --git a/Examples/scpi/MATLAB/gen_sine_signal.m b/Examples/scpi/MATLAB/gen_sine_signal.m index d818111e5..b38cb8203 100644 --- a/Examples/scpi/MATLAB/gen_sine_signal.m +++ b/Examples/scpi/MATLAB/gen_sine_signal.m @@ -1,9 +1,10 @@ %% Define Red Pitaya as TCP/IP object clc close all -IP= '192.168.178.103'; % Input IP of your Red Pitaya... +% IP= '192.168.101.108'; % IP of your Red Pitaya... +IP= 'rp-f01b63.local'; % rp-MAC.local MAC are the last 6 characters of your Red Pitaya port = 5000; % If you are using WiFi then IP is: -RP=tcpip(IP, port); % 192.168.128.1 +RP=tcpip(IP, port); fopen(RP); RP.Terminator = 'CR/LF'; @@ -11,7 +12,7 @@ % specify peridic mode, sinusoidal waveform and 1kHZ frequency fprintf(RP,'SOURce1:MODE PERiodic'); % periodic fprintf(RP,'SOURce1:FUNCtion:SHAPe SINusoid'); % select signal shape as sinusoid -fprintf(RP,'SOURce1:FREQuency:FIXed 1000'); % Set frequency of output signal to 3kHz +fprintf(RP,'SOURce1:FREQuency:FIXed 10000'); % Set frequency of output signal to 3kHz % set output amplitude and offset fprintf(RP,'SOURce1:VOLTage:IMMediate:AMPlitude 1'); % Set amplitude of the output signal diff --git a/Examples/scpi/MATLAB/gen_sync_two_channel.m b/Examples/scpi/MATLAB/gen_sync_two_channel.m index 838dd5623..875498162 100644 --- a/Examples/scpi/MATLAB/gen_sync_two_channel.m +++ b/Examples/scpi/MATLAB/gen_sync_two_channel.m @@ -1,9 +1,10 @@ %% Define Red Pitaya as TCP/IP object clc close all -IP= '192.168.178.103'; % Input IP of your Red Pitaya... +% IP= '192.168.101.108'; % IP of your Red Pitaya... +IP= 'rp-f01b63.local'; % rp-MAC.local MAC are the last 6 characters of your Red Pitaya port = 5000; % If you are using WiFi then IP is: -RP=tcpip(IP, port); % 192.168.128.1 +RP=tcpip(IP, port); fopen(RP); RP.Terminator = 'CR/LF'; diff --git a/Examples/scpi/MATLAB/osc_sync_two_chnannel.m b/Examples/scpi/MATLAB/osc_sync_two_chnannel.m new file mode 100644 index 000000000..8844885e0 --- /dev/null +++ b/Examples/scpi/MATLAB/osc_sync_two_chnannel.m @@ -0,0 +1,55 @@ +%% Define Red Pitaya as TCP/IP object +clc +close all +% IP= '192.168.101.108'; % IP of your Red Pitaya... +IP= 'rp-f01b63.local'; % rp-MAC.local MAC are the last 6 characters of your Red Pitaya +port = 5000; % If you are using WiFi then IP is: +RP=tcpip(IP, port,'InputBufferSize',32784*6); +fopen(RP); +RP.Terminator = 'CR/LF'; + +%% SCPI exchange +% select data transmittion BIN/ASCII (0 - binary, any other value - ASCII) +bin=1; +% set buffer size on Red Pitaya +buffer_size = 2^14; + + +% wait for data to be captured by RedPitaya +while( str2double(query(RP,'ACQuire1:RUN?')) ) + continue +end +fprintf ('triggered\n'); + +%% read back table data +% if bin + % read ch 1 + fprintf(RP,'ACQuire1:TRACe:DATA:RAW? 16000 '); + data1 = binblockread(RP,'int16'); + data1 = data1 ./ 2^15; + + % read ch 2 + fprintf(RP,'ACQuire2:TRACe:DATA:RAW? 16000 '); + data2 = binblockread(RP,'int16'); + data2 = data2 ./ 2^15; +plot(data1); +hold on; +plot(data2,'r'); + +% else + + string1= query(RP,'ACQuire1:TRACe:DATA:DATA? 16000 '); + string2= query(RP,'ACQuire2:TRACe:DATA:DATA? 16000 '); + % convert string to numbers + data1=str2num(string1); + data2=str2num(string2); +% end + +% plot gethered data +figure(); +plot(data1); +hold on; +plot(data2,'r'); + +%% Close connection to the Red Pitaya +fclose(RP); \ No newline at end of file diff --git a/Examples/scpi/MATLAB/osc_sync_with_gen.m b/Examples/scpi/MATLAB/osc_sync_with_gen.m new file mode 100644 index 000000000..08e2dc129 --- /dev/null +++ b/Examples/scpi/MATLAB/osc_sync_with_gen.m @@ -0,0 +1,88 @@ +%% Define Red Pitaya as TCP/IP object +clc +close all +% IP= '192.168.101.108'; % IP of your Red Pitaya... +IP= 'rp-f01b63.local'; % rp-MAC.local MAC are the last 6 characters of your Red Pitaya +port = 5000; % If you are using WiFi then IP is: +RP=tcpip(IP, port,'InputBufferSize',32784*5); +fopen(RP); +RP.Terminator = 'CR/LF'; + +%% SCPI exchange +% select data transmittion BIN/ASCII (0 - binary, any other value - ASCII) +bin=1; +% set buffer size on Red Pitaya +buffer_size = 2^14; + +%% generator setting + +% specify burst mode, sinusoidal waveform +fprintf(RP,'SOURce1:MODE BURSt'); +fprintf(RP,'SOURce1:FUNCtion:SHAPe SINusoid'); + +% burst half the buffer with then idle for quarter buffer, repeat 4 times +fprintf(RP,'SOURce1:BURSt:DATA:REPetitions 1'); +fprintf(RP,'SOURce1:BURSt:DATA:LENgth %d ', 1 * buffer_size / 2 ); +fprintf(RP,''); % fprintf does not complete with /n, hence one is added here +fprintf(RP,'SOURce1:BURSt:PERiod:LENgth %d ', 3 * buffer_size / 4); +fprintf(RP,''); % fprintf does not complete with /n, hence one is added here +fprintf(RP,'SOURce1:BURSt:PERiod:NUMber 4'); + +% set output amplitude and offset +fprintf(RP,'SOURce1:VOLTage:IMMediate:AMPlitude 1'); +fprintf(RP,'SOURce1:VOLTage:IMMediate:OFFSet 0'); +% enable output +fprintf(RP,'OUTPUT1:STATe ON'); + +% define event synchronization source +fprintf(RP,'SOURce1:EVENT:SYNChronization:SOURce GEN1'); + +%% oscilloscope setting + +% data rate decimation +fprintf(RP,'ACQuire1:INPut:DECimation 4'); + +% trigger timing [sample periods] +fprintf(RP,'ACQuire1:SAMPle:PRE 0 '); +fprintf(RP,'ACQuire1:SAMPle:POST %d ', buffer_size); +fprintf(RP,''); % fprintf does not complete with /n, hence one is added here + +% define event synchronization source +fprintf(RP,'ACQuire1:EVENT:SYNChronization:SOURce GEN1'); +% there are no HW trigger sources +fprintf(RP,'ACQuire1:EVENT:TRIGger:SOURce NONE'); + +%% start measurement + +% reset and start state machine +fprintf(RP,'SOURce1:RESET'); +fprintf(RP,'SOURce1:START'); +% trigger state machine +fprintf(RP,'SOURce1:TRIGger'); + +% wait for data to be captured by RedPitaya +while( str2double(query(RP,'ACQuire1:RUN?')) ) + continue +end +fprintf ('triggered\n'); + +%% read back table data +% if bin + fprintf(RP,'ACQuire1:TRACe:DATA:RAW? 16000 '); + data1 = binblockread(RP,'int16'); + data1 = data1 ./ 2^15; +plot(data1) + +% else + + string= query(RP,'ACQuire1:TRACe:DATA:DATA? 16000 '); + % convert string to numbers + data=str2num(string); +% end + +% plot gethered data +figure(); +plot(data) + +%% Close connection to the Red Pitaya +fclose(RP); \ No newline at end of file diff --git a/Examples/scpi/MATLAB/osc_trigger_forced.m b/Examples/scpi/MATLAB/osc_trigger_forced.m new file mode 100644 index 000000000..b22f3bbcb --- /dev/null +++ b/Examples/scpi/MATLAB/osc_trigger_forced.m @@ -0,0 +1,61 @@ +%% Define Red Pitaya as TCP/IP object +clc +close all +% IP= '192.168.101.108'; % IP of your Red Pitaya... +IP= 'rp-f01b63.local'; % rp-MAC.local MAC are the last 6 characters of your Red Pitaya +port = 5000; % If you are using WiFi then IP is: +RP=tcpip(IP, port,'InputBufferSize',32784*5); +fopen(RP); +RP.Terminator = 'CR/LF'; + +%% SCPI exchange +% select data transmittion BIN/ASCII (0 - binary, any other value - ASCII) +bin=1; +% set buffer size on Red Pitaya +buffer_size = 2^14; + +% data rate decimation +fprintf(RP,'ACQuire1:INPut:DECimation 10'); + +% trigger timing [sample periods] +fprintf(RP,'ACQuire1:SAMPle:PRE 0'); +fprintf(RP,'ACQuire1:SAMPle:POST %d ', buffer_size); +fprintf(RP,''); % fprintf does not complete with /n, hence one is added here + +% define event synchronization source +fprintf(RP,'ACQuire1:EVENT:SYNChronization:SOURce OSC1'); +% disable hardware trigger sources +fprintf(RP,'ACQuire1:EVENT:TRIGger:SOURce NONE'); + +% synchronization source is the default, which is the module itself +% reset and start state machine +fprintf(RP,'ACQuire1:RESET'); +fprintf(RP,'ACQuire1:START'); +fprintf(RP,'ACQuire1:TRIGger'); + +% wait for data to be captured by RedPitaya +while( str2double(query(RP,'ACQuire1:RUN?')) ) + continue +end +fprintf ('triggered\n'); + +%% read back table data +% if bin + fprintf(RP,'ACQuire1:TRACe:DATA:RAW? 16000 '); + data1 = binblockread(RP,'int16'); + data1 = data1 ./ 2^15; +plot(data1) + +% else + + string= query(RP,'ACQuire1:TRACe:DATA:DATA? 16000 '); + % convert string to numbers + data=str2num(string); +% end + +% plot gethered data +figure(); +plot(data) + +%% Close connection to the Red Pitaya +fclose(RP); \ No newline at end of file diff --git a/Examples/scpi/MATLAB/osc_trigger_level.m b/Examples/scpi/MATLAB/osc_trigger_level.m new file mode 100644 index 000000000..9eb26c6a1 --- /dev/null +++ b/Examples/scpi/MATLAB/osc_trigger_level.m @@ -0,0 +1,62 @@ +%% Define Red Pitaya as TCP/IP object +clc +close all +% IP= '192.168.101.108'; % IP of your Red Pitaya... +IP= 'rp-f01b63.local'; % rp-MAC.local MAC are the last 6 characters of your Red Pitaya +port = 5000; % If you are using WiFi then IP is: +RP=tcpip(IP, port,'InputBufferSize',32784*5); +fopen(RP); +RP.Terminator = 'CR/LF'; +%% SCPI exchange +% select data transmittion BIN/ASCII (0 - binary, any other value - ASCII) +bin=1; +% set buffer size on Red Pitaya +buffer_size = 2^14; + +% data rate decimation +fprintf(RP,'ACQuire1:INPut:DECimation 1'); + +% trigger timing [sample periods] +fprintf(RP,'ACQuire1:SAMPle:PRE %d \n', buffer_size/4 * 1); +fprintf(RP,'ACQuire1:SAMPle:POST %d \n',buffer_size/4 * 3); + +% trigger level and slope +fprintf(RP,'ACQuire1:TRIGger:LEVel 0.4, 0.5'); +fprintf(RP,'ACQuire1:TRIGger:SLOPe POSitive'); + +% define event synchronization source +fprintf(RP,'ACQuire1:EVENT:SYNChronization:SOURce OSC1'); +% use OSC1 as hardware trigger source +fprintf(RP,'ACQuire1:EVENT:TRIGger:SOURce OSC1'); + +% synchronization source is the default, which is the module itself +% reset and start state machine +fprintf(RP,'ACQuire1:RESET'); +fprintf(RP,'ACQuire1:START'); + +% wait for data to be captured by RedPitaya +while( str2double(query(RP,'ACQuire1:RUN?')) ) + continue +end +fprintf ('triggered\n'); + +%% read back table data +% if bin + fprintf(RP,'ACQuire1:TRACe:DATA:RAW? 16000 '); + data1 = binblockread(RP,'int16'); + data1 = data1 ./ 2^15; +plot(data1) + +% else + + string= query(RP,'ACQuire1:TRACe:DATA:DATA? 16000 '); + % convert string to numbers + data=str2num(string); +% end + +% plot gethered data +figure(); +plot(data) + +%% Close connection to the Red Pitaya +fclose(RP); \ No newline at end of file diff --git a/Examples/scpi/Python/gen_arbitrary_signal.py b/Examples/scpi/Python/gen_arbitrary_signal.py index c4866b428..52e684378 100755 --- a/Examples/scpi/Python/gen_arbitrary_signal.py +++ b/Examples/scpi/Python/gen_arbitrary_signal.py @@ -64,7 +64,7 @@ if args.bin: values = rp.query_binary_values(":SOURce1:TRACe:DATA:RAW? {}".format(length), datatype='h') else: - values = rp.query(":SOURce1:TRACe:DATA:DATA? {}".format(length)) + values = rp.query_ascii_values(":SOURce1:TRACe:DATA:DATA? {}".format(length)) print(values) rp.close() diff --git a/Examples/scpi/Python/gen_burst.py b/Examples/scpi/Python/gen_burst.py index f64ce8c0c..5e10c0d5c 100755 --- a/Examples/scpi/Python/gen_burst.py +++ b/Examples/scpi/Python/gen_burst.py @@ -29,10 +29,8 @@ rp.write(":SOURce1:VOLTage:IMMediate:AMPlitude 1") rp.write(":SOURce1:VOLTage:IMMediate:OFFSet 0") -# specify peridic mode, sinusoidal waveform +# specify burst mode, sinusoidal waveform rp.write(":SOURce1:MODE BURSt") -rp.write(":SOURce1:BURSt:MODE FINite") -#rp.write(":SOURce1:BURSt:MODE INFinite") rp.write(":SOURce1:FUNCtion:SHAPe SINusoid") # burst half the buffer with then idle for quarter buffer, repeat 4 times @@ -40,6 +38,7 @@ rp.write(":SOURce1:BURSt:DATA:LENgth " + str(1 * buffer_size // 2)) rp.write(":SOURce1:BURSt:PERiod:LENgth " + str(3 * buffer_size // 4)) rp.write(":SOURce1:BURSt:PERiod:NUMber 4") +#rp.write(":SOURce1:BURSt:PERiod:NUMber INFinity") # reset and start state machine rp.write(":SOURce1:RESET") diff --git a/Examples/scpi/Python/gen_sync_two_channel.py b/Examples/scpi/Python/gen_sync_two_channel.py index 08f421daa..3b41594e5 100755 --- a/Examples/scpi/Python/gen_sync_two_channel.py +++ b/Examples/scpi/Python/gen_sync_two_channel.py @@ -34,14 +34,14 @@ rp.write(":SOURce2:MODE PERiodic") rp.write(":SOURce1:FUNCtion:SHAPe SINusoid") rp.write(":SOURce2:FUNCtion:SHAPe SINusoid") -rp.write(":SOURce1:FREQuency:FIXed 1000") -rp.write(":SOURce2:FREQuency:FIXed 1000") +rp.write(":SOURce1:FREQuency:FIXed 10000") +rp.write(":SOURce2:FREQuency:FIXed 10000") rp.write(":SOURce1:PHASe:ADJust 0") rp.write(":SOURce2:PHASe:ADJust 90") # both generator should be synchronously driven -rp.write(":SOURce1:EVENT:SYNChronization:SOURce GEN0") -rp.write(":SOURce2:EVENT:SYNChronization:SOURce GEN0") +rp.write(":SOURce1:EVENT:SYNChronization:SOURce GEN1") +rp.write(":SOURce2:EVENT:SYNChronization:SOURce GEN1") # reset and start state machine rp.write(":SOURce:RESET") diff --git a/Examples/scpi/Python/gpio.py b/Examples/scpi/Python/gpio.py new file mode 100755 index 000000000..a175f672f --- /dev/null +++ b/Examples/scpi/Python/gpio.py @@ -0,0 +1,38 @@ +#!/usr/bin/env python3 + +import argparse + +parser = argparse.ArgumentParser(description='SCPI: read identification.') +parser.add_argument('adr', type=str, default='127.0.0.1', help='provide IP address or URL') +parser.add_argument('-p', '--port', type=int, default=5000, help='specify SCPI port (default is 5000)') +parser.add_argument('-b', '--bin', action="store_true", help='use binary data transfer instead of the default ASCII') +parser.add_argument('--py', action="store_true", help='use PyVISA-py (by default the system visa library is used)') +args = parser.parse_args() + +############################################################################### +# connect to the instrument +############################################################################### + +import visa + +rm = visa.ResourceManager('@py' if args.py else '') +#rm.list_resources() +rp = rm.open_resource('TCPIP::{}::{}::SOCKET'.format(args.adr, args.port), read_termination = '\r\n') + +############################################################################### +# SCPI exchange +############################################################################### + +# read GPIO +for i in range(16): + value = rp.query(":GPIO:PIN? {}".format(i)) + print("get GPIO[{}] = {}".format(i, value)) + +# write GPIO +values = [0, 1, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1] +for i in range(16): + value = values[i] + rp.write(":GPIO:PIN {}, {}".format(i, value)) + print("set GPIO[{}] = {}".format(i, value)) + +rp.close() diff --git a/Examples/scpi/Python/identification.py b/Examples/scpi/Python/identification.py index 97bae6b45..d4a0f2ad7 100755 --- a/Examples/scpi/Python/identification.py +++ b/Examples/scpi/Python/identification.py @@ -28,4 +28,10 @@ # read SCPI standard version print("SCPI standard version = " + rp.query("SYSTem:VERSion?")) +# HWID +print("Red Pitaya HWID: HWID = " + rp.query("HWIDentification:HWID?")) +print("Red Pitaya HWID: EFUSE = " + rp.query("HWIDentification:EFUSE?")) +print("Red Pitaya HWID: DNA = " + rp.query("HWIDentification:DNA?")) +print("Red Pitaya HWID: GITH = " + rp.query("HWIDentification:GITH?")) + rp.close() diff --git a/Examples/scpi/Python/lg_counter.py b/Examples/scpi/Python/lg_counter.py new file mode 100755 index 000000000..44a9c0dc1 --- /dev/null +++ b/Examples/scpi/Python/lg_counter.py @@ -0,0 +1,63 @@ +#!/usr/bin/env python3 + +import argparse + +parser = argparse.ArgumentParser(description='SCPI: generate sinusoidal signal.') +parser.add_argument('adr', type=str, default='127.0.0.1', help='provide IP address or URL') +parser.add_argument('-p', '--port', type=int, default=5000, help='specify SCPI port (default is 5000)') +parser.add_argument('-b', '--bin', action="store_true", help='use binary data transfer instead of the default ASCII') +parser.add_argument('--py', action="store_true", help='use PyVISA-py (by default the system visa library is used)') +args = parser.parse_args() + +############################################################################### +# connect to the instrument +############################################################################### + +import visa + +rm = visa.ResourceManager('@py' if args.py else '') +#rm.list_resources() +rp = rm.open_resource('TCPIP::{}::{}::SOCKET'.format(args.adr, args.port), read_termination = '\r\n') + +############################################################################### +# SCPI exchange +############################################################################### + +buffer_size = 2**14 + +# GPIO mode, all GPIO signals are connected to logic generator +rp.write(":MANAGement:GPIO:MODE #hFFFF") + +# buffer waveform and sample timing +waveform = range(buffer_size) + +if args.bin: + rp.write_binary_values(":LG:TRACe:DATA:RAW ", waveform, datatype='h') +else: + # TODO: due to a bug in PyVISA the documented use of write_ascii_values does not work + #rp.write_ascii_values(":LG:TRACe:DATA:DATA", y_sum) + rp.write(":LG:TRACe:DATA:DATA " + ','.join(map(str, waveform))) + +# burst half the buffer with then idle for quarter buffer, repeat 4 times +rp.write(":LG:BURSt:DATA:REPetitions 2") +rp.write(":LG:BURSt:DATA:LENgth " + str(buffer_size)) +rp.write(":LG:BURSt:PERiod:LENgth " + str(buffer_size)) +rp.write(":LG:BURSt:PERiod:NUMber INFinity") + +# set output amplitude, offset and enable it +rp.write(":LG:OUTPut:ENABle " + str(0xffff) + + "," + str(0xffff)) # all pins have outputs enabled (for both output values 0/1) +rp.write(":LG:OUTPut:MASK " + str(0x0000)) # all bits come from ASG, none are constants +rp.write(":LG:OUTPut:VALue " + str(0x0000)) # the constant pin values are irrelevant since they are not used + +# define event synchronization source +rp.write(":LG:EVENT:SYNChronization:SOURce LG") +# there are no HW trigger sources +rp.write(":LG:EVENT:TRIGger:SOURce NONE") + +# reset, start, trigger state machine +rp.write(":LG:RESET") +rp.write(":LG:START") +rp.write(":LG:TRIGger") + +rp.close() diff --git a/Examples/scpi/Python/osc_sync_two_channel.py b/Examples/scpi/Python/osc_sync_two_channel.py new file mode 100755 index 000000000..7ffde2b63 --- /dev/null +++ b/Examples/scpi/Python/osc_sync_two_channel.py @@ -0,0 +1,79 @@ +#!/usr/bin/env python3 + +import argparse + +parser = argparse.ArgumentParser(description='SCPI: generate sinusoidal signal.') +parser.add_argument('adr', type=str, default='127.0.0.1', help='provide IP address or URL') +parser.add_argument('-p', '--port', type=int, default=5000, help='specify SCPI port (default is 5000)') +parser.add_argument('-b', '--bin', action="store_true", help='use binary data transfer instead of the default ASCII') +parser.add_argument('--py', action="store_true", help='use PyVISA-py (by default the system visa library is used)') +args = parser.parse_args() + +############################################################################### +# connect to the instrument +############################################################################### + +import visa + +rm = visa.ResourceManager('@py' if args.py else '') +#rm.list_resources() +rp = rm.open_resource('TCPIP::{}::{}::SOCKET'.format(args.adr, args.port), read_termination = '\r\n') + +############################################################################### +# SCPI exchange +############################################################################### + +buffer_size = 2**14 + +for dev in range(2): + # SCPI channels are indexed from 1 while API is indexed from 0 + ch = dev+1 + + # data rate decimation + rp.write(":ACQuire{}:INPut:DECimation 1".format(ch)) + + # trigger timing [sample periods] + rp.write(":ACQuire{}:SAMPle:PRE ".format(ch) + str(buffer_size//4 * 1)) + rp.write(":ACQuire{}:SAMPle:POST ".format(ch) + str(buffer_size//4 * 3)) + + # define event synchronization source + rp.write(":ACQuire1:EVENT:SYNChronization:SOURce OSC1") + # use OSC1 as hardware trigger source + rp.write(":ACQuire1:EVENT:TRIGger:SOURce OSC1") + +# trigger level and slope +rp.write(":ACQuire1:TRIGger:LEVel 0.4, 0.5") +rp.write(":ACQuire1:TRIGger:SLOPe POSitive") +rp.write(":ACQuire2:TRIGger:LEVel -0.2, -0.15") +rp.write(":ACQuire2:TRIGger:SLOPe NEGative") + +# synchronization source is the default, which is the module itself +# reset and start state machine +rp.write(":ACQuire1:RESET") +rp.write(":ACQuire1:START") +#rp.write(":ACQuire1:TRIGGER") + +# wait for data +while (int(rp.query(":ACQuire1:RUN?"))): + pass +print ('triggered') + +# read back table data +values = [None, None] +for dev in range(2): + # SCPI channels are indexed from 1 while API is indexed from 0 + ch = dev+1 + + if args.bin: + values[dev] = rp.query_binary_values(":ACQuire{}:TRACe:DATA:RAW? {}".format(ch, buffer_size), datatype='h') + else: + values[dev] = rp.query_ascii_values(":ACQuire{}:TRACe:DATA:DATA? {}".format(ch, buffer_size)) + +print(values) + +import matplotlib.pyplot as plt +t = range(0, buffer_size) +plt.plot(t, values[0], t, values[1]) +plt.show() + +rp.close() diff --git a/Examples/scpi/Python/osc_sync_with_gen.py b/Examples/scpi/Python/osc_sync_with_gen.py new file mode 100755 index 000000000..679f363e8 --- /dev/null +++ b/Examples/scpi/Python/osc_sync_with_gen.py @@ -0,0 +1,94 @@ +#!/usr/bin/env python3 + +import argparse + +parser = argparse.ArgumentParser(description='SCPI: generate sinusoidal signal.') +parser.add_argument('adr', type=str, default='127.0.0.1', help='provide IP address or URL') +parser.add_argument('-p', '--port', type=int, default=5000, help='specify SCPI port (default is 5000)') +parser.add_argument('-b', '--bin', action="store_true", help='use binary data transfer instead of the default ASCII') +parser.add_argument('--py', action="store_true", help='use PyVISA-py (by default the system visa library is used)') +args = parser.parse_args() + +############################################################################### +# connect to the instrument +############################################################################### + +import visa + +rm = visa.ResourceManager('@py' if args.py else '') +#rm.list_resources() +rp = rm.open_resource('TCPIP::{}::{}::SOCKET'.format(args.adr, args.port), read_termination = '\r\n') + +############################################################################### +# SCPI exchange +############################################################################### + +buffer_size = 2**14 + +############################################################################### +# generator setting +############################################################################### + +# specify burst mode, sinusoidal waveform +rp.write(":SOURce1:MODE BURSt") +rp.write(":SOURce1:FUNCtion:SHAPe SINusoid") + +# burst half the buffer with then idle for quarter buffer, repeat 4 times +rp.write(":SOURce1:BURSt:DATA:REPetitions 1") +rp.write(":SOURce1:BURSt:DATA:LENgth " + str(1 * buffer_size // 2)) +rp.write(":SOURce1:BURSt:PERiod:LENgth " + str(3 * buffer_size // 4)) +rp.write(":SOURce1:BURSt:PERiod:NUMber 4") +#rp.write(":SOURce1:BURSt:PERiod:NUMber INFinity") + +# set output amplitude and offset +rp.write(":SOURce1:VOLTage:IMMediate:AMPlitude 1") +rp.write(":SOURce1:VOLTage:IMMediate:OFFSet 0") +# enable output +rp.write(":OUTPUT1:STATe ON") + +# define event synchronization source +rp.write(":SOURce1:EVENT:SYNChronization:SOURce GEN1") + +############################################################################### +# oscilloscope setting +############################################################################### + +# data rate decimation +rp.write(":ACQuire1:INPut:DECimation 4") + +# trigger timing [sample periods] +rp.write(":ACQuire1:SAMPle:PRE " + str(0)) +rp.write(":ACQuire1:SAMPle:POST " + str(buffer_size)) + +# define event synchronization source +rp.write(":ACQuire1:EVENT:SYNChronization:SOURce GEN1") +# there are no HW trigger sources +rp.write(":ACQuire1:EVENT:TRIGger:SOURce NONE") + +############################################################################### +# start measurement +############################################################################### + +# reset and start state machine +rp.write(":SOURce1:RESET") +rp.write(":SOURce1:START") +# trigger state machine +rp.write(":SOURce1:TRIGger") + +# wait for data +while (int(rp.query(":ACQuire1:RUN?"))): + pass +print ('triggered') + +# read back table data +if args.bin: + values = rp.query_binary_values(":ACQuire1:TRACe:DATA:RAW? {}".format(buffer_size), datatype='h') +else: + values = rp.query_ascii_values(":ACQuire1:TRACe:DATA:DATA? {}".format(buffer_size)) +print(values) + +import matplotlib.pyplot as plt +plt.plot(values) +plt.show() + +rp.close() diff --git a/Examples/scpi/Python/osc_trigger_forced.py b/Examples/scpi/Python/osc_trigger_forced.py new file mode 100755 index 000000000..bb4467ebf --- /dev/null +++ b/Examples/scpi/Python/osc_trigger_forced.py @@ -0,0 +1,62 @@ +#!/usr/bin/env python3 + +import argparse + +parser = argparse.ArgumentParser(description='SCPI: generate sinusoidal signal.') +parser.add_argument('adr', type=str, default='127.0.0.1', help='provide IP address or URL') +parser.add_argument('-p', '--port', type=int, default=5000, help='specify SCPI port (default is 5000)') +parser.add_argument('-b', '--bin', action="store_true", help='use binary data transfer instead of the default ASCII') +parser.add_argument('--py', action="store_true", help='use PyVISA-py (by default the system visa library is used)') +args = parser.parse_args() + +############################################################################### +# connect to the instrument +############################################################################### + +import visa + +rm = visa.ResourceManager('@py' if args.py else '') +#rm.list_resources() +rp = rm.open_resource('TCPIP::{}::{}::SOCKET'.format(args.adr, args.port), read_termination = '\r\n') + +############################################################################### +# SCPI exchange +############################################################################### + +buffer_size = 2**14 + +# data rate decimation +rp.write(":ACQuire1:INPut:DECimation 1") + +# trigger timing [sample periods] +rp.write(":ACQuire1:SAMPle:PRE " + str(0)) +rp.write(":ACQuire1:SAMPle:POST " + str(buffer_size)) + +# define event synchronization source +rp.write(":ACQuire1:EVENT:SYNChronization:SOURce OSC1") +# disable hardware trigger sources +rp.write(":ACQuire1:EVENT:TRIGger:SOURce NONE") + +# synchronization source is the default, which is the module itself +# reset and start state machine +rp.write(":ACQuire1:RESET") +rp.write(":ACQuire1:START") +rp.write(":ACQuire1:TRIGger") + +# wait for data +while (int(rp.query(":ACQuire1:RUN?"))): + pass +print ('triggered') + +# read back table data +if args.bin: + values = rp.query_binary_values(":ACQuire1:TRACe:DATA:RAW? {}".format(buffer_size), datatype='h') +else: + values = rp.query_ascii_values(":ACQuire1:TRACe:DATA:DATA? {}".format(buffer_size)) +print(values) + +import matplotlib.pyplot as plt +plt.plot(values) +plt.show() + +rp.close() diff --git a/Examples/scpi/Python/osc_trigger_level.py b/Examples/scpi/Python/osc_trigger_level.py new file mode 100755 index 000000000..ef3bb127f --- /dev/null +++ b/Examples/scpi/Python/osc_trigger_level.py @@ -0,0 +1,65 @@ +#!/usr/bin/env python3 + +import argparse + +parser = argparse.ArgumentParser(description='SCPI: generate sinusoidal signal.') +parser.add_argument('adr', type=str, default='127.0.0.1', help='provide IP address or URL') +parser.add_argument('-p', '--port', type=int, default=5000, help='specify SCPI port (default is 5000)') +parser.add_argument('-b', '--bin', action="store_true", help='use binary data transfer instead of the default ASCII') +parser.add_argument('--py', action="store_true", help='use PyVISA-py (by default the system visa library is used)') +args = parser.parse_args() + +############################################################################### +# connect to the instrument +############################################################################### + +import visa + +rm = visa.ResourceManager('@py' if args.py else '') +#rm.list_resources() +rp = rm.open_resource('TCPIP::{}::{}::SOCKET'.format(args.adr, args.port), read_termination = '\r\n') + +############################################################################### +# SCPI exchange +############################################################################### + +buffer_size = 2**14 + +# data rate decimation +rp.write(":ACQuire1:INPut:DECimation 1") + +# trigger timing [sample periods] +rp.write(":ACQuire1:SAMPle:PRE " + str(buffer_size//4 * 1)) +rp.write(":ACQuire1:SAMPle:POST " + str(buffer_size//4 * 3)) + +# trigger level and slope +rp.write(":ACQuire1:TRIGger:LEVel 0.4, 0.5") +rp.write(":ACQuire1:TRIGger:SLOPe POSitive") + +# define event synchronization source +rp.write(":ACQuire1:EVENT:SYNChronization:SOURce OSC1") +# use OSC1 as hardware trigger source +rp.write(":ACQuire1:EVENT:TRIGger:SOURce OSC1") + +# synchronization source is the default, which is the module itself +# reset and start state machine +rp.write(":ACQuire1:RESET") +rp.write(":ACQuire1:START") + +# wait for data +while (int(rp.query(":ACQuire1:RUN?"))): + pass +print ('triggered') + +# read back table data +if args.bin: + values = rp.query_binary_values(":ACQuire1:TRACe:DATA:RAW? {}".format(buffer_size), datatype='h') +else: + values = rp.query_ascii_values(":ACQuire1:TRACe:DATA:DATA? {}".format(buffer_size)) +print(values) + +import matplotlib.pyplot as plt +plt.plot(values) +plt.show() + +rp.close() diff --git a/Examples/scpi/Python/test.py b/Examples/scpi/Python/test.py new file mode 100755 index 000000000..07f73f8c3 --- /dev/null +++ b/Examples/scpi/Python/test.py @@ -0,0 +1,121 @@ +#!/usr/bin/env python3 + +import argparse + +parser = argparse.ArgumentParser(description='SCPI: read identification.') +parser.add_argument('adr', type=str, default='127.0.0.1', help='provide IP address or URL') +parser.add_argument('-p', '--port', type=int, default=5000, help='specify SCPI port (default is 5000)') +parser.add_argument('-b', '--bin', action="store_true", help='use binary data transfer instead of the default ASCII') +parser.add_argument('--py', action="store_true", help='use PyVISA-py (by default the system visa library is used)') +args = parser.parse_args() + +############################################################################### +# connect to the instrument +############################################################################### + +import visa + +rm = visa.ResourceManager('@py' if args.py else '') +#rm.list_resources() +rp = rm.open_resource('TCPIP::{}::{}::SOCKET'.format(args.adr, args.port), read_termination = '\r\n') + +############################################################################### +# common code +############################################################################### + +error = 0 + +class test (): + tests = 0 + error = 0 + + def check_query (self, name: str, query: str, read: str = "", expect = True): + # register test + self.tests = self.tests + 1 + # send query + value = rp.query(query) + # check query response + if (value != read): + print ("Test \"" + name + "\" ERROR:") + print (" expected: " + read) + print (" response: " + value) + self.error = self.error + 1 + # check SCPI error status + self.check_errors(name) + + def check_write_query (self, name: str, write: str, query: str, read: str = "", expect = True): + # register test + self.tests = self.tests + 1 + # send write/read + rp.write(write) + value = rp.query(query) + # check read response + if (value != read): + print ("Test \"" + name + "\" value ERROR:") + print (" expected: " + read) + print (" response: " + value) + self.error = self.error + 1 + # check SCPI error status + self.check_errors(name) + + def check_errors (self, name: str): + err_cnt = int(rp.query(":SYSTem:ERRor:COUNt?")) + if (err_cnt): + print ("Test \"" + name + "\" SCPI ERROR (cnt = " + str(err_cnt) + "):") + for err in range(err_cnt): + value = rp.query(":SYSTem:ERRor:NEXT?") + print (" SCPI ERR " + str(err) + ": " + value) + self.error = self.error + 1 + + def report (self): + print ("REPORT:") + print (" PASSED: " + str(self.tests - self.error)) + print (" FAILED: " + str( self.error)) + +t = test() + +############################################################################### +# SCPI integrated commands +############################################################################### + +# read identification string +t.check_query("IDN", "*IDN?", "REDPITAYA,INSTR2017,0,01-02") +# read SCPI standard version +t.check_query("VERSion", "SYSTem:VERSion?", "1999.0") + +############################################################################### +# HWID +############################################################################### + +t.check_query("HWID", "HWIDentification:HWID?", '#H1') +t.check_query("EFUSE", "HWIDentification:EFUSE?", '#H0') +t.check_query("DNA", "HWIDentification:DNA?", '#H11C0DCE4B59085C') +t.check_query("GITH", "HWIDentification:GITH?", '"3c08fd5a94977f8e0118d002520168ef650fa777"') + +############################################################################### +# MGMT +############################################################################### + +# GPIO mode +values = [["#H0", True], ["#HFFFF", True], ["#H1FFFF", False]] +for idx, val in enumerate(values): + t.check_write_query("gpio_mode " + str(idx), ":MANAGement:GPIO:MODE " + val[0], ":MANAGement:GPIO:MODE?", val[0], val[1]) + +# digital loop from generator to oscilloscope + + +# // Management +# {.pattern = ":MANAGement:GPIO[:MODE]", .callback = rpscpi_mgmt_set_gpio_mode, }, +# {.pattern = ":MANAGement:GPIO[:MODE]?", .callback = rpscpi_mgmt_get_gpio_mode, }, +# {.pattern = ":MANAGement:LOOP", .callback = rpscpi_mgmt_set_loop, }, +# {.pattern = ":MANAGement:LOOP?", .callback = rpscpi_mgmt_get_loop, }, +# {.pattern = ":MANAGement:PRINT", .callback = rpscpi_mgmt_print, }, // debug command + + +############################################################################### +# report +############################################################################### + +t.report() + +rp.close() diff --git a/Examples/scpi/Python/xadc.py b/Examples/scpi/Python/xadc.py new file mode 100755 index 000000000..c323c0442 --- /dev/null +++ b/Examples/scpi/Python/xadc.py @@ -0,0 +1,35 @@ +#!/usr/bin/env python3 + +import argparse + +parser = argparse.ArgumentParser(description='SCPI: read identification.') +parser.add_argument('adr', type=str, default='127.0.0.1', help='provide IP address or URL') +parser.add_argument('-p', '--port', type=int, default=5000, help='specify SCPI port (default is 5000)') +parser.add_argument('-b', '--bin', action="store_true", help='use binary data transfer instead of the default ASCII') +parser.add_argument('--py', action="store_true", help='use PyVISA-py (by default the system visa library is used)') +args = parser.parse_args() + +############################################################################### +# connect to the instrument +############################################################################### + +import visa + +rm = visa.ResourceManager('@py' if args.py else '') +#rm.list_resources() +rp = rm.open_resource('TCPIP::{}::{}::SOCKET'.format(args.adr, args.port), read_termination = '\r\n') + +############################################################################### +# SCPI exchange +############################################################################### + +# read temperature +value = rp.query(":XADC:TEMPerature?") +print("XADC temperature = {}°C".format(value)) + +# read input voltage +for i in range(4): + value = rp.query(":XADC:ANALog:INPut? {}".format(i)) + print("XADC input[{}] = {}V".format(i, value)) + +rp.close() diff --git a/Makefile.x86 b/Makefile.x86 index 894a23bbb..d49197a6a 100644 --- a/Makefile.x86 +++ b/Makefile.x86 @@ -11,7 +11,7 @@ export REVISION export VERSION SUBMODULE_UBT = "redpitaya-v2016.4" -SUBMODULE_LIN = "redpitaya-v2016.2-RP4" +SUBMODULE_LIN = "branch-redpitaya-v2017.2" SUBMODULE_APP = $(shell git submodule status Applications) define GREET_MSG @@ -59,8 +59,8 @@ $(INSTALL_DIR): ################################################################################ UBOOT_TAG = redpitaya-v2016.4 -LINUX_TAG = redpitaya-v2016.2-RP4 -DTREE_TAG = xilinx-v2016.4 +LINUX_TAG = branch-redpitaya-v2017.2 +DTREE_TAG = xilinx-v2017.2 UBOOT_DIR = $(TMP)/u-boot-xlnx-$(UBOOT_TAG) LINUX_DIR = $(TMP)/linux-xlnx-$(LINUX_TAG) @@ -82,8 +82,8 @@ UBOOT_CFLAGS = "-O2 -mtune=cortex-a9 -mfpu=neon -mfloat-abi=hard" # FPGA build provides: $(FSBL), $(FPGA), $(DEVICETREE). ################################################################################ -FPGA_PRJ_LST = classic logic v0.94 axi4lite mercury -FPGA_PRJ_LST = classic logic v0.94 mercury +FPGA_PRJ_LST = classic logic v0.94 mercury axi4lite +#FPGA_PRJ_LST = classic logic v0.94 mercury FPGA_PRJ = logic .PHONY: fpga @@ -181,18 +181,14 @@ $(DTREE_DIR): $(DTREE_TAR) $(DEVICETREE): $(DTREE_DIR) $(INSTALL_DIR)/fpga $(TMP) cp -r $(INSTALL_DIR)/fpga/$(FPGA_PRJ)/dts $(TMP) - cat $(TMP)/dts/fpga.dts >> $(TMP)/dts/system.dts - tools/dtc/dtc -@ -I dts -O dtb -o $(DEVICETREE) -i $(TMP)/dts -i fpga/dts $(TMP)/dts/system.dts - tools/dtc/dtc -@ -I dts -O dtb -o $(TMP)/dts/amba_pl.dtbo patches/devicetree/amba_pl.dts + cat $(TMP)/dts/fpga.dts >> $(TMP)/dts/system-top.dts + tools/dtc/dtc -@ -I dts -O dtb -o $(DEVICETREE) -i $(TMP)/dts -i fpga/dts $(TMP)/dts/system-top.dts # create device tree source from binary for reference tools/dtc/dtc -I dtb -O dts --sort -o $(TMP)/dts/dtraw.dts $(DEVICETREE) devicetree-install: $(DEVICETREE) $(INSTALL_DIR) cp $(DEVICETREE) $(INSTALL_DIR) cp $(TMP)/dts/dtraw.dts $(INSTALL_DIR) - cp $(TMP)/dts/amba_pl.dtbo $(INSTALL_DIR) - cp patches/devicetree/amba_pl.sh $(INSTALL_DIR) - cp patches/devicetree/rmamba_pl.sh $(INSTALL_DIR) ################################################################################ # boot file generator diff --git a/OS/debian/debian.sh b/OS/debian/debian.sh new file mode 100644 index 000000000..c2dbc9e2e --- /dev/null +++ b/OS/debian/debian.sh @@ -0,0 +1,194 @@ +################################################################################ +# Authors: +# - Pavel Demin +# - Iztok Jeras +# License: +# https://raw.githubusercontent.com/RedPitaya/RedPitaya/master/COPYING +################################################################################ + +# Added by DM; 2017/10/17 to check ROOT_DIR setting +if [ $ROOT_DIR ]; then + echo ROOT_DIR is "$ROOT_DIR" +else + echo Error: ROOT_DIR is not set + echo exit with error + exit +fi + +# Install Debian base system to the root file system +ARCH=armhf +DISTRO=stretch +MIRROR=http://deb.debian.org/debian/ +#echo debootstrap --foreign --arch $ARCH $DISTRO $ROOT_DIR $MIRROR +#exit +debootstrap --foreign --arch $ARCH $DISTRO $ROOT_DIR $MIRROR + +OVERLAY=OS/debian/overlay + +# enable chroot access with native execution +cp /etc/resolv.conf $ROOT_DIR/etc/ +cp /usr/bin/qemu-arm-static $ROOT_DIR/usr/bin/ + +export LC_ALL=en_US.UTF-8 + +chroot $ROOT_DIR <<- EOF_CHROOT +export LANG=C +/debootstrap/debootstrap --second-stage +EOF_CHROOT + +################################################################################ +# APT settings +################################################################################ + +cat <<- EOF_CAT > $ROOT_DIR/etc/apt/sources.list +deb $MIRROR $DISTRO main contrib non-free +deb-src $MIRROR $DISTRO main contrib non-free +deb $MIRROR $DISTRO-updates main contrib non-free +deb-src $MIRROR $DISTRO-updates main contrib non-free +deb http://security.debian.org/debian-security $DISTRO/updates main contrib non-free +deb-src http://security.debian.org/debian-security $DISTRO/updates main contrib non-free +EOF_CAT + +cat <<- EOF_CAT > $ROOT_DIR/etc/apt/apt.conf.d/99norecommends +APT::Install-Recommends "0"; +APT::Install-Suggests "0"; +EOF_CAT + +chroot $ROOT_DIR <<- EOF_CHROOT +apt-get update +apt-get -y upgrade +EOF_CHROOT + +################################################################################ +# locale and keyboard +# setting LC_ALL overides values for all LC_* variables, this avids complaints +# about missing locales if some of this variables are inherited over SSH +################################################################################ + +chroot $ROOT_DIR <<- EOF_CHROOT +# this is needed by systemd services 'keyboard-setup.service' and 'console-setup.service' +DEBIAN_FRONTEND=noninteractive \ +apt-get -y install console-setup + +# setup locale +apt-get -y install locales +locale-gen en_US.UTF-8 +update-locale LANG=en_US.UTF-8 LANGUAGE=en_US LC_ALL=en_US.UTF-8 + +# TODO seems sytemd is not running without /proc/cmdline or something +#localectl set-locale LANG=en_US.UTF-8 LANGUAGE=en_US LC_ALL=en_US.UTF-8 +#localectl set-keymap us + +# Debug log +locale -a +locale +cat /etc/default/locale +cat /etc/default/keyboard +EOF_CHROOT + +################################################################################ +# hostname +# NOTE: redpitaya.py enables a systemd service +# which changes the hostname on boot, to an unique value +################################################################################ + +#chroot $ROOT_DIR <<- EOF_CHROOT +# TODO seems sytemd is not running without /proc/cmdline or something +#hostnamectl set-hostname redpitaya +#EOF_CHROOT + +install -v -m 664 -o root -D $OVERLAY/etc/hostname $ROOT_DIR/etc/hostname + +################################################################################ +# timezone and fake HW time +################################################################################ + +chroot $ROOT_DIR <<- EOF_CHROOT +# install fake hardware clock +apt-get -y install fake-hwclock + +dpkg-reconfigure --frontend=noninteractive tzdata + +# TODO seems sytemd is not running without /proc/cmdline or something +#timedatectl set-timezone Europe/Ljubljana +EOF_CHROOT + +# set default timezone +if [ "$TIMEZONE" = "" ]; then + TIMEZONE="Etc/UTC" +fi +# set timezone and fake RTC time +echo timezone = $TIMEZONE +echo $TIMEZONE > $ROOT_DIR/etc/timezone + +# the fake HW clock will be UTC, so an adjust file is not needed +#echo $MYADJTIME > $ROOT_DIR/etc/adjtime +# fake HW time is set to the image build time +DATETIME=`date -u +"%F %T"` +echo date/time = $DATETIME +echo $DATETIME > $ROOT_DIR/etc/fake-hwclock.data + +################################################################################ +# File System table +################################################################################ + +install -v -m 664 -o root -D $OVERLAY/etc/fstab $ROOT_DIR/etc/fstab + +################################################################################ +# run other scripts +################################################################################ + +#. OS/debian/tools.sh +#. OS/debian/network.sh +#. OS/debian/zynq.sh +#. OS/debian/redpitaya.sh +#. OS/debian/jupyter.sh +#. OS/debian/tft.sh + +################################################################################ +# handle users +################################################################################ + +# http://0pointer.de/blog/projects/serial-console.html + +install -v -m 664 -o root -D $OVERLAY/etc/securetty $ROOT_DIR/etc/securetty +install -v -m 664 -o root -D $OVERLAY/etc/systemd/system/serial-getty@ttyPS0.service.d/override.conf \ + $ROOT_DIR/etc/systemd/system/serial-getty@ttyPS0.service.d/override.conf + +chroot $ROOT_DIR <<- EOF_CHROOT +echo root:root | chpasswd +EOF_CHROOT + +################################################################################ +# cleanup +################################################################################ + +chroot $ROOT_DIR <<- EOF_CHROOT +apt-get clean +history -c +EOF_CHROOT + +# kill -k file users and list them -m before Unmount file systems +fuser -km $BOOT_DIR +fuser -km $ROOT_DIR + +# file system cleanup for better compression +cat /dev/zero > $ROOT_DIR/zero.file +sync -f $ROOT_DIR/zero.file +rm -f $ROOT_DIR/zero.file + +# remove ARM emulation +rm $ROOT_DIR/usr/bin/qemu-arm-static + +################################################################################ +# archiving image +################################################################################ + +# create a tarball (without resolv.conf link, since it causes schroot issues) +rm $ROOT_DIR/etc/resolv.conf +tar -cpzf redpitaya_OS_${DATE}.tar.gz --one-file-system -C $ROOT_DIR . +# recreate resolv.conf link +ln -sf /run/systemd/resolve/resolv.conf $ROOT_DIR/etc/resolv.conf + +# one final sync to be sure +sync diff --git a/OS/debian/image.sh b/OS/debian/image.sh index 83f300698..257667499 100755 --- a/OS/debian/image.sh +++ b/OS/debian/image.sh @@ -23,7 +23,7 @@ DATE=`date +"%H-%M-%S_%d-%b-%Y"` SIZE=3500 #IMAGE=$1 -IMAGE=redpitaya_ubuntu_${DATE}.img +IMAGE=redpitaya_OS_${DATE}.img dd if=/dev/zero of=$IMAGE bs=1M count=$SIZE @@ -60,6 +60,7 @@ mount $ROOT_DEV $ROOT_DIR ################################################################################ . OS/debian/ubuntu.sh 2>&1 | tee $ROOT_DIR/buildlog.txt +#. OS/debian/debian.sh 2>&1 | tee $ROOT_DIR/buildlog.txt ################################################################################ # umount image diff --git a/OS/debian/jupyter.sh b/OS/debian/jupyter.sh index fef2295ab..85e84ffb0 100644 --- a/OS/debian/jupyter.sh +++ b/OS/debian/jupyter.sh @@ -9,6 +9,15 @@ # install packages ############################################################################### +# Added by DM; 2017/10/17 to check ROOT_DIR setting +if [ $ROOT_DIR ]; then + echo ROOT_DIR is "$ROOT_DIR" +else + echo Error: ROOT_DIR is not set + echo exit with error + exit +fi + chroot $ROOT_DIR <<- EOF_CHROOT # Sigrok apt-get -y install libsigrok libsigrokdecode sigrok-cli diff --git a/OS/debian/network.sh b/OS/debian/network.sh index b1d7ff133..34fa6724b 100644 --- a/OS/debian/network.sh +++ b/OS/debian/network.sh @@ -1,7 +1,16 @@ +# Added by DM; 2017/10/17 to check ROOT_DIR setting +if [ $ROOT_DIR ]; then + echo ROOT_DIR is "$ROOT_DIR" +else + echo Error: ROOT_DIR is not set + echo exit with error + exit +fi + # systemd-networkd wired/wireless network configuration (DHCP and WPA supplicant for WiFi) mkdir $ROOT_DIR/etc/iptables install -v -m 664 -o root -D $OVERLAY/etc/iptables/iptables.rules $ROOT_DIR/etc/iptables/iptables.rules -install -V -m 755 -o root -D $OVERLAY/etc/systemd/system/iptables-flush $ROOT_DIR/etc/systemd/system/iptables-flush +install -v -m 644 -o root -D $OVERLAY/etc/systemd/system/iptables-flush $ROOT_DIR/etc/systemd/system/iptables-flush install -v -m 664 -o root -D $OVERLAY/etc/systemd/network/wired.network $ROOT_DIR/etc/systemd/network/wired.network install -v -m 664 -o root -D $OVERLAY/etc/systemd/network/wireless.network.client $ROOT_DIR/etc/systemd/network/wireless.network.client install -v -m 664 -o root -D $OVERLAY/etc/systemd/network/wireless.network.ap $ROOT_DIR/etc/systemd/network/wireless.network.ap @@ -21,10 +30,6 @@ install -v -m 664 -o root -D $OVERLAY/etc/avahi/services/bazaar.service install -v -m 664 -o root -D $OVERLAY/etc/avahi/services/scpi.service $ROOT_DIR/etc/avahi/services/scpi.service install -v -m 664 -o root -D $OVERLAY/etc/systemd/system/hostname-mac.service $ROOT_DIR/etc/systemd/system/hostname-mac.service -# hostapd versions -export HOSTAPD_VER=2.6 -export HAPATCH_VER=hostapd_2_6 - chroot $ROOT_DIR <<- EOF_CHROOT # network tools apt-get -y install iproute2 iputils-ping curl diff --git a/OS/debian/overlay/etc/avahi/services/scpi.srvice b/OS/debian/overlay/etc/avahi/services/scpi.service similarity index 100% rename from OS/debian/overlay/etc/avahi/services/scpi.srvice rename to OS/debian/overlay/etc/avahi/services/scpi.service diff --git a/OS/debian/overlay/etc/udev/rules.d/10-redpitaya.rules b/OS/debian/overlay/etc/udev/rules.d/10-redpitaya.rules index d979c3805..53f61d3b7 100644 --- a/OS/debian/overlay/etc/udev/rules.d/10-redpitaya.rules +++ b/OS/debian/overlay/etc/udev/rules.d/10-redpitaya.rules @@ -13,6 +13,12 @@ SUBSYSTEM=="uio", SYMLINK+="uio/%s{name}", GROUP="uio" #SUBSYSTEM=="leds", ACTION=="add", RUN+="/bin/chgrp -R led /sys%p", RUN+="/bin/chmod -R g=u /sys%p" #SUBSYSTEM=="leds", ACTION=="change", ENV{TRIGGER}!="none", RUN+="/bin/chgrp -R led /sys%p", RUN+="/bin/chmod -R g=u /sys%p" +# GPIO character device +# rename devices and give group access rights +# NOTE: this rule does not create a symlink for ZYNQ GPIO controller, since there is no "name" attribute +#SUBSYSTEM=="gpio", SYMLINK+="gpio/%s{name}", GROUP="gpio" +SUBSYSTEM=="gpio", GROUP="gpio" + # GPIO # give group access rights # https://www.raspberrypi.org/forums/viewtopic.php?f=29&t=9667 diff --git a/OS/debian/redpitaya.sh b/OS/debian/redpitaya.sh index 5c180fcae..b938074db 100644 --- a/OS/debian/redpitaya.sh +++ b/OS/debian/redpitaya.sh @@ -10,6 +10,15 @@ # install various packages ################################################################################ +# Added by DM; 2017/10/17 to check ROOT_DIR setting +if [ $ROOT_DIR ]; then + echo ROOT_DIR is "$ROOT_DIR" +else + echo Error: ROOT_DIR is not set + echo exit with error + exit +fi + chroot $ROOT_DIR <<- EOF_CHROOT # applications used by Bazaar apt-get -y install wget gawk @@ -44,6 +53,21 @@ apt-get -y install gdb cgdb libcunit1-ncurses-dev apt-get -y install bc EOF_CHROOT +################################################################################ +# SCPI parser +################################################################################ + +# GPIO utilities +chroot $ROOT_DIR <<- EOF_CHROOT +git clone --depth 1 https://github.com/RedPitaya/scpi-parser.git --branch meson +cd scpi-parser +meson builddir --buildtype release --prefix /usr +cd builddir +ninja install +cd ../../ +rm -rf scpi-parser +EOF_CHROOT + ################################################################################ # systemd services ################################################################################ diff --git a/OS/debian/tft.sh b/OS/debian/tft.sh index e39d4ffd0..15f51f403 100644 --- a/OS/debian/tft.sh +++ b/OS/debian/tft.sh @@ -1,3 +1,12 @@ +# Added by DM; 2017/10/17 to check ROOT_DIR setting +if [ $ROOT_DIR ]; then + echo ROOT_DIR is "$ROOT_DIR" +else + echo Error: ROOT_DIR is not set + echo exit with error + exit +fi + chroot $ROOT_DIR <<- EOF_CHROOT # install sshfs apt-get -y install sshfs diff --git a/OS/debian/tools.sh b/OS/debian/tools.sh index ded40af89..f22c2066e 100644 --- a/OS/debian/tools.sh +++ b/OS/debian/tools.sh @@ -2,9 +2,21 @@ # miscelaneous tools ################################################################################ +# Added by DM; 2017/10/17 to check ROOT_DIR setting +if [ $ROOT_DIR ]; then + echo ROOT_DIR is "$ROOT_DIR" +else + echo Error: ROOT_DIR is not set + echo exit with error + exit +fi + chroot $ROOT_DIR <<- EOF_CHROOT apt-get -y install dbus udev +# Git can be used to share notebook examples +apt-get -y install git + # development tools apt-get -y install build-essential less vim nano sudo usbutils psmisc lsof apt-get -y install parted dosfstools diff --git a/OS/debian/ubuntu.sh b/OS/debian/ubuntu.sh index 3d4d62fa0..96353735a 100644 --- a/OS/debian/ubuntu.sh +++ b/OS/debian/ubuntu.sh @@ -6,6 +6,15 @@ # https://raw.githubusercontent.com/RedPitaya/RedPitaya/master/COPYING ################################################################################ +# Added by DM; 2017/10/17 to check ROOT_DIR setting +if [ $ROOT_DIR ]; then + echo ROOT_DIR is "$ROOT_DIR" +else + echo Error: ROOT_DIR is not set + echo exit with error + exit +fi + # Install Ubuntu base system to the root file system UBUNTU_BASE_VER=16.04.3 UBUNTU_BASE_TAR=ubuntu-base-${UBUNTU_BASE_VER}-base-armhf.tar.gz @@ -32,6 +41,9 @@ chroot $ROOT_DIR <<- EOF_CHROOT apt-get update apt-get -y upgrade +# install HWE kernell +apt-get -y install --install-recommends linux-tools-generic-hwe-16.04 linux-headers-generic-hwe-16.04 + # add package containing add-apt-repository apt-get -y install software-properties-common # add PPA: https://launchpad.net/~redpitaya/+archive/ubuntu/zynq @@ -165,7 +177,7 @@ rm $ROOT_DIR/usr/bin/qemu-arm-static # create a tarball (without resolv.conf link, since it causes schroot issues) rm $ROOT_DIR/etc/resolv.conf -tar -cpzf redpitaya_ubuntu_${DATE}.tar.gz --one-file-system -C $ROOT_DIR . +tar -cpzf redpitaya_OS_${DATE}.tar.gz --one-file-system -C $ROOT_DIR . # recreate resolv.conf link ln -sf /run/systemd/resolve/resolv.conf $ROOT_DIR/etc/resolv.conf diff --git a/OS/debian/zynq.sh b/OS/debian/zynq.sh index 8b75c2cff..7aa649ec2 100644 --- a/OS/debian/zynq.sh +++ b/OS/debian/zynq.sh @@ -6,6 +6,15 @@ # https://raw.githubusercontent.com/RedPitaya/RedPitaya/master/COPYING ################################################################################ +# Added by DM; 2017/10/17 to check ROOT_DIR setting +if [ $ROOT_DIR ]; then + echo ROOT_DIR is "$ROOT_DIR" +else + echo Error: ROOT_DIR is not set + echo exit with error + exit +fi + # Copy files to the boot file system unzip ecosystem*.zip -d $BOOT_DIR @@ -29,9 +38,6 @@ chroot $ROOT_DIR <<- EOF_CHROOT # I2C libraries apt-get install -y libi2c-dev i2c-tools -# Git can be used to share notebook examples -apt-get -y install git - # Device tree compiler can be used to compile custom overlays apt-get -y install libudev-dev EOF_CHROOT @@ -85,6 +91,17 @@ EOF_CHROOT #rm -rf Ne10 #EOF_CHROOT +# GPIO utilities +chroot $ROOT_DIR <<- EOF_CHROOT +git clone --depth 1 https://github.com/RedPitaya/gpio-utils.git +cd gpio-utils +meson builddir --buildtype release --prefix /usr +cd builddir +ninja install +cd ../../ +rm -rf gpio-utils +EOF_CHROOT + ################################################################################ # create users and groups ################################################################################ diff --git a/OS/filesystem/sbin/mkoverlay.sh b/OS/filesystem/sbin/mkoverlay.sh new file mode 100644 index 000000000..11b92e906 --- /dev/null +++ b/OS/filesystem/sbin/mkoverlay.sh @@ -0,0 +1,16 @@ +#!/bin/bash + +# common directories +FPGAS=/opt/redpitaya/fpga +OVERLAYS=/sys/kernel/config/device-tree/overlays + +# first argument is overlay name +OVERLAY=$1 + +# first load the fpga, then the overlay +mkdir $OVERLAYS/$OVERLAY +cat $FPGAS/$OVERLAY/fpga.dtbo > $OVERLAYS/$OVERLAY/dtbo + +# wait a bit for the kernel to process the overlay, +# before attempts are made to use the new drivers +sleep 0.5s diff --git a/OS/filesystem/sbin/overlay.sh b/OS/filesystem/sbin/overlay.sh index 6f7f38d46..9a5b148da 100755 --- a/OS/filesystem/sbin/overlay.sh +++ b/OS/filesystem/sbin/overlay.sh @@ -14,3 +14,7 @@ rmdir $OVERLAYS/* cat $FPGAS/$OVERLAY/fpga.bit > /dev/xdevcfg mkdir $OVERLAYS/$OVERLAY cat $FPGAS/$OVERLAY/fpga.dtbo > $OVERLAYS/$OVERLAY/dtbo + +# wait a bit for the kernel to process the overlay, +# before attempts are made to use the new drivers +sleep 0.5s diff --git a/OS/filesystem/sbin/rmoverlay.sh b/OS/filesystem/sbin/rmoverlay.sh new file mode 100644 index 000000000..a589bcdc6 --- /dev/null +++ b/OS/filesystem/sbin/rmoverlay.sh @@ -0,0 +1,11 @@ +#!/bin/bash + +# common directories +FPGAS=/opt/redpitaya/fpga +OVERLAYS=/sys/kernel/config/device-tree/overlays + +# first argument is overlay name +OVERLAY=$1 + +# first remove existing overlays, there is no way to unload the FPGA +rmdir $OVERLAYS/* diff --git a/Test/uio/test_uio.c b/Test/uio/test_uio.c deleted file mode 100644 index a1e11a8ee..000000000 --- a/Test/uio/test_uio.c +++ /dev/null @@ -1,86 +0,0 @@ -/** - * @brief Red Pitaya library API interface implementation - * @Author Red Pitaya - * (c) Red Pitaya http://www.redpitaya.com - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#define ioread32(p) (*(volatile uint32_t *)(p)) - -int main (int argc, char **argv) { - int fd; - volatile void *regset; - volatile void *regset1; - size_t length; - off_t offset; - off_t page_size = sysconf(_SC_PAGESIZE); - - printf("DEBUG: page size is 0x%08lx\n", page_size); - - // try opening the device - fd = open("/dev/uio/ps2pl", O_RDWR); - if (fd == -1) { - printf("ERROR: opening UIO file descriptor failed\n"); - return -1; - } - - // get regset pointer - length = 0x1000; // 12 bit page size - offset = 1 * page_size; - regset1 = mmap(NULL, length, PROT_READ|PROT_WRITE, MAP_SHARED, fd, offset); - //printf ("1:0x%08x\n\r", (uint32_t) regset); - if (regset1 == MAP_FAILED) { - printf("ERROR: mmap failed offset=0x%08lx '%s'\n", offset, strerror(errno)); - //printf ("2:0x%08x\n\r", (uint32_t) regset); - return (-1); - } else { - printf("SUCESS: mmap sucess offset=0x%08lx\n", offset); - } - - // get regset pointer - length = 0x1000; // 12 bit page size - offset = 0x0; - regset = mmap(NULL, length, PROT_READ|PROT_WRITE, MAP_SHARED, fd, offset); - //printf ("1:0x%08x\n\r", (uint32_t) regset); - if (regset == MAP_FAILED) { - printf("ERROR: mmap failed offset=0x%08lx '%s'\n", offset, strerror(errno)); - //printf ("2:0x%08x\n\r", (uint32_t) regset); - return (-1); - } else { - printf("SUCESS: mmap sucess offset=0x%08lx\n", offset); - } - - uint64_t dna; - dna = ((uint64_t) ioread32(regset + 0x14) << 32) - | ((uint64_t) ioread32(regset + 0x10) << 0); - printf("DNA=0x%" PRIx64 "\n", dna); - - // release regset pointer - if (munmap((void *) regset, length) == -1) { - printf("ERROR: munmap failed\n"); - return (-1); - } - - // release regset pointer - if (munmap((void *) regset1, length) == -1) { - printf("ERROR: munmap failed\n"); - return (-1); - } - - // close device - if (close (fd) == -1) { - printf("ERROR: closing UIO file descriptor failed\n"); - return (-1); - } - return (0); -} diff --git a/api2/include/redpitaya/rp2.h b/api2/include/redpitaya/rp2.h index 3c4bad167..6ed3c32c4 100644 --- a/api2/include/redpitaya/rp2.h +++ b/api2/include/redpitaya/rp2.h @@ -103,13 +103,6 @@ typedef struct { ///@} -/** - * Returns textual representation of error code. - * @param errorCode Error code returned from API. - * @return Textual representation of error given error code. - */ -const char* rp_GetError(int errorCode); - #ifdef __cplusplus } #endif diff --git a/api2/src/Makefile b/api2/src/Makefile index 887e8c481..d6d7c139a 100644 --- a/api2/src/Makefile +++ b/api2/src/Makefile @@ -34,14 +34,7 @@ STATIC_LIB=$(OUTPUT_DIR)/librp2.a TARGET=$(SHARED_LIB) $(STATIC_LIB) # List of compiled object files -OBJECTS = pdm.o \ - id.o \ - muxctl.o \ - calib.o \ - acquire.o \ - generate.o \ - la_acq.o \ - rp2.o \ +OBJECTS = la_acq.o \ rp_api.o \ rp_dma.o \ common.o diff --git a/api2/src/acquire.c b/api2/src/acquire.c deleted file mode 100644 index e5eb34308..000000000 --- a/api2/src/acquire.c +++ /dev/null @@ -1,169 +0,0 @@ -/** - * $Id: $ - * - * @brief Red Pitaya library oscilloscope module implementation - * - * @Author Red Pitaya - * - * (c) Red Pitaya http://www.redpitaya.com - * - * This part of code is written in C programming language. - * Please visit http://en.wikipedia.org/wiki/C_(programming_language) - * for more details on the language used herein. - */ - -#include -#include -#include -#include -#include - -#include "common.h" -#include "acquire.h" - -// structure containing available ranges -static const float ranges [2] = {1.0, 20.0}; - -int rp_AcqOpen(char *dev, rp_handle_uio_t *handle) { - handle->length = ACQUIRE_BASE_SIZE; - int status = common_Open (dev, handle); - if (status != RP_OK) { - return status; - } - return RP_OK; -} - -int rp_AcqClose(rp_handle_uio_t *handle) { - int status = common_Close (handle); - if (status != RP_OK) { - return status; - } - return RP_OK; -} - -/** - * Equalization filters - */ - -int rp_AcqSetEqFilter(rp_handle_uio_t *handle, rp_adc_eqfilter_regset_t *fil) { - rp_adc_eqfilter_regset_t *regset = (rp_adc_eqfilter_regset_t *) &(((acq_regset_t *) handle->regset)->fil); - iowrite32(fil->byp, ®set->byp); - iowrite32(fil->aa , ®set->aa ); - iowrite32(fil->bb , ®set->bb ); - iowrite32(fil->kk , ®set->kk ); - iowrite32(fil->pp , ®set->pp ); - return RP_OK; -} - -int rp_AcqGetEqFilter(rp_handle_uio_t *handle, rp_adc_eqfilter_regset_t *fil) { - rp_adc_eqfilter_regset_t *regset = (rp_adc_eqfilter_regset_t *) &(((acq_regset_t *) handle->regset)->fil); - fil->byp = ioread32(®set->byp); - fil->aa = ioread32(®set->aa ); - fil->bb = ioread32(®set->bb ); - fil->kk = ioread32(®set->kk ); - fil->pp = ioread32(®set->pp ); - return RP_OK; -} - -/** - * Decimation - */ - -int rp_AcqSetDecimation(rp_handle_uio_t *handle, rp_scope_decimation_regset_t *dec) { - rp_scope_decimation_regset_t *regset = (rp_scope_decimation_regset_t *) &(((acq_regset_t *) handle->regset)->dec); - iowrite32(dec->avg, ®set->avg); - iowrite32(dec->dec, ®set->dec); - iowrite32(dec->shr, ®set->shr); - return RP_OK; -} - -int rp_AcqGetDecimation(rp_handle_uio_t *handle, rp_scope_decimation_regset_t *dec) { - rp_scope_decimation_regset_t *regset = (rp_scope_decimation_regset_t *) &(((acq_regset_t *) handle->regset)->dec); - dec->dec = ioread32(®set->dec); - dec->avg = ioread32(®set->avg); - dec->shr = ioread32(®set->shr); - return RP_OK; -} - -/** - * Trigger - */ - -int rp_AcqSetTrigger(rp_handle_uio_t *handle, float lvl, float hst) { - rp_scope_trigger_regset_t *regset = (rp_scope_trigger_regset_t *) &(((acq_regset_t *) handle->regset)->trg); - float range = ranges[ioread32(®set->rng)]; - iowrite32(( int32_t) (lvl / range * (1 << RP_ACQ_DWI)), ®set->lvl); - iowrite32((uint32_t) (hst / range * (1 << RP_ACQ_DWI)), ®set->hst); - return RP_OK; -} - -int rp_AcqGetTrigger(rp_handle_uio_t *handle, float *lvl, float *hst) { - rp_scope_trigger_regset_t *regset = (rp_scope_trigger_regset_t *) &(((acq_regset_t *) handle->regset)->trg); - float range = ranges[ioread32(®set->rng)]; - *lvl = ((float) (ioread32(®set->lvl) >> RP_ACQ_DWI)) * range; - *hst = ((float) (ioread32(®set->hst) >> RP_ACQ_DWI)) * range; - return RP_OK; -} - -int rp_AcqSetTriggerSrc(rp_handle_uio_t *handle, uint32_t source) { - acq_regset_t *regset = (acq_regset_t *) handle->regset; - iowrite32(source, ®set->cfg_sel); - return RP_OK; -} - -int rp_AcqGetTriggerSrc(rp_handle_uio_t *handle, uint32_t *source) { - acq_regset_t *regset = (acq_regset_t *) handle->regset; - *source = ioread32(®set->cfg_sel); - return RP_OK; -} - -int rp_AcqSetTriggerDelay(rp_handle_uio_t *handle, uint32_t value) { - acq_regset_t *regset = (acq_regset_t *) handle->regset; - iowrite32(value, ®set->cfg_dly); - return RP_OK; -} - -int rp_AcqGetTriggerDelay(rp_handle_uio_t *handle, uint32_t *value) { - acq_regset_t *regset = (acq_regset_t *) handle->regset; - *value = ioread32(®set->cfg_dly); - return RP_OK; -} - -int rp_AcqGetTriggerState(rp_handle_uio_t *handle, uint32_t *state) { - acq_regset_t *regset = (acq_regset_t *) handle->regset; - *state = (ioread32(®set->ctl) & RP_ACQ_CTL_TRG_MASK) != 0; - return RP_OK; -} - -int rp_AcqStart(rp_handle_uio_t *handle) { - acq_regset_t *regset = (acq_regset_t *) handle->regset; - iowrite32(RP_ACQ_CTL_ACQ_MASK, ®set->ctl); - return RP_OK; -} - -int rp_AcqStop(rp_handle_uio_t *handle) { - acq_regset_t *regset = (acq_regset_t *) handle->regset; - iowrite32(0x0, ®set->ctl); - return RP_OK; -} - -int rp_AcqReset(rp_handle_uio_t *handle) { - acq_regset_t *regset = (acq_regset_t *) handle->regset; - iowrite32(RP_ACQ_CTL_RST_MASK, ®set->ctl); - return RP_OK; -} - - - - -int rp_AcqGetPreTriggerCounter(rp_handle_uio_t *handle, uint32_t* value) { - return RP_OK; -} - -int rp_AcqGetData(rp_handle_uio_t *handle, uint32_t *size, int16_t *buffer) { - return RP_OK; -} - -int rp_AcqGetBufSize(rp_handle_uio_t *handle, uint32_t *size) { - return RP_OK; -} diff --git a/api2/src/acquire.h b/api2/src/acquire.h deleted file mode 100644 index ac94ef7df..000000000 --- a/api2/src/acquire.h +++ /dev/null @@ -1,215 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// Red Pitaya library acquire module interface -// Author: Red Pitaya -// (c) Red Pitaya http://www.redpitaya.com -//////////////////////////////////////////////////////////////////////////////// - -#ifndef SRC_ACQIRE_H_ -#define SRC_ACQIRE_H_ - -#include -#include - -#define RP_MNA 2 - -#define RP_ACQ_DWI 14 - -#define RP_ACQ_CTL_RST_MASK 0x1 -#define RP_ACQ_CTL_TRG_MASK 0x2 -#define RP_ACQ_CTL_ACQ_MASK 0x4 - -// Base acquire address -static const int ACQUIRE_BASE_SIZE = 0x00100000; - -// ADC filter -typedef struct { - uint32_t byp; // :1; - int32_t aa; - int32_t bb; - int32_t kk; - int32_t pp; -} rp_adc_eqfilter_regset_t; - -// scope decimation -typedef struct { - uint32_t avg; // :1; - uint32_t dec; // :DWC; - uint32_t shr; // :DWS; -} rp_scope_decimation_regset_t; - -// scope trigger source -typedef struct { - uint32_t rng; // :1; - int32_t lvl; // s14 - uint32_t hst; // u14 -} rp_scope_trigger_regset_t; - -// acquire structure declaration -typedef struct { - // control/status - uint32_t ctl; -// { -// uint32_t rst :1; -// uint32_t trg :1; -// uint32_t acq :1; -// } - // trigger - uint32_t cfg_sel; // TWG - uint32_t cfg_dly; // u32 - rp_scope_trigger_regset_t trg; - rp_scope_decimation_regset_t dec; - rp_adc_eqfilter_regset_t fil; -} acq_regset_t; - -static const uint32_t THRESHOLD_MASK = 0x3FFF; // (14 bits) -static const uint32_t HYSTERESIS_MASK = 0x3FFF; // (14 bits) -static const uint32_t TRIG_DELAY_MASK = 0xFFFFFFFF; // (32 bits) -static const uint32_t WRITE_POINTER_MASK = 0x3FFF; // (14 bits) -static const uint32_t EQ_FILTER_AA = 0x3FFFF; // (18 bits) -static const uint32_t EQ_FILTER = 0x1FFFFFF; // (25 bits) -static const uint32_t RST_WR_ST_MCH_MASK = 0x2; // (1st bit) -static const uint32_t TRIG_ST_MCH_MASK = 0x4; // (2st bit) -static const uint32_t PRE_TRIGGER_COUNTER = 0xFFFFFFFF; // (32 bit) - -/* @brief Default filter equalization coefficients */ -// byp -static const rp_adc_eqfilter_regset_t fil_hi = {0x0, 0x7D93, 0x437C7, 0xd9999a, 0x2666}; -static const rp_adc_eqfilter_regset_t fil_lo = {0x0, 0x4C5F, 0x2F38B, 0xd9999a, 0x2666}; - - -int rp_AcqOpen(char *dev, rp_handle_uio_t *handle); -int rp_AcqClose(rp_handle_uio_t *handle); - -int rp_AcqSetEqFilter(rp_handle_uio_t *handle, rp_adc_eqfilter_regset_t *fil); -int rp_AcqGetEqFilter(rp_handle_uio_t *handle, rp_adc_eqfilter_regset_t *fil); - -/** - * Gets the decimation used at acquiring signal. There is only a set of pre-defined decimation - * values which can be specified. See the #rp_acq_decimation_t enum values. - * @param decimation Returns one of pre-defined decimation values which is currently set. - * @return If the function is successful, the return value is RP_OK. - * If the function is unsuccessful, the return value is any of RP_E* values that indicate an error. - */ -int rp_AcqSetDecimation(rp_handle_uio_t *handle, rp_scope_decimation_regset_t *dec); -int rp_AcqGetDecimation(rp_handle_uio_t *handle, rp_scope_decimation_regset_t *dec); - -/** - * Sets the trigger source used at acquiring signal. When acquiring is started, - * the FPGA waits for the trigger condition on the specified source and when the condition is met, it - * starts writing the signal to the buffer. - * @param source Trigger source. - * @return If the function is successful, the return value is RP_OK. - * If the function is unsuccessful, the return value is any of RP_E* values that indicate an error. - */ -int rp_AcqSetTriggerSrc(rp_handle_uio_t *handle, uint32_t source); -int rp_AcqGetTriggerSrc(rp_handle_uio_t *handle, uint32_t *source); - -/** - * Returns the trigger state. Either it is waiting for a trigger to happen, or it has already been triggered. - * By default it is in the triggered state, which is treated the same as disabled. - * @param state Trigger state - * @return If the function is successful, the return value is RP_OK. - * If the function is unsuccessful, the return value is any of RP_E* values that indicate an error. - */ -int rp_AcqGetTriggerState(rp_handle_uio_t *handle, uint32_t *state); - -/** - * Sets the number of decimated data after trigger written into memory. - * @param decimated_data_num Number of decimated data. It must not be higher than the ADC buffer size. - * @return If the function is successful, the return value is RP_OK. - * If the function is unsuccessful, the return value is any of RP_E* values that indicate an error. - */ -int rp_AcqSetTriggerDelay(rp_handle_uio_t *handle, uint32_t value); -int rp_AcqGetTriggerDelay(rp_handle_uio_t *handle, uint32_t *value); - -/** - * Returns the number of valid data ponts before trigger. - * @param time_ns number of data points. - * @return If the function is successful, the return value is RP_OK. - * If the function is unsuccessful, the return value is any of RP_E* values that indicate an error. - */ -int rp_AcqGetPreTriggerCounter(rp_handle_uio_t *handle, uint32_t* value); - -/** - * Sets the trigger threshold value in volts. Makes the trigger when ADC value crosses this value. - * @param voltage Threshold value for the channel - * @return If the function is successful, the return value is RP_OK. - * If the function is unsuccessful, the return value is any of RP_E* values that indicate an error. - */ -int rp_AcqSetTriggerLevel(rp_handle_uio_t *handle, float voltage); -int rp_AcqGetTriggerLevel(rp_handle_uio_t *handle, float *voltage); - -/** - * Sets the trigger threshold hysteresis value in volts. - * Value must be outside to enable the trigger again. - * @param voltage Threshold hysteresis value for the channel - * @return If the function is successful, the return value is RP_OK. - * If the function is unsuccessful, the return value is any of RP_E* values that indicate an error. - */ -int rp_AcqSetTriggerHyst(rp_handle_uio_t *handle, float voltage); -int rp_AcqGetTriggerHyst(rp_handle_uio_t *handle, float *voltage); - -/** - * Sets the acquire gain state. The gain should be set to the same value as it is set on the Red Pitaya - * hardware by the LV/HV gain jumpers. LV = 1V; HV = 20V. - * @param channel Channel A or B - * @param state High or Low state - * @return If the function is successful, the return value is RP_OK. - * If the function is unsuccessful, the return value is any of RP_E* values that indicate an error. - */ -int rp_AcqSetRange(rp_handle_uio_t *handle, int range); -int rp_AcqGetRange(rp_handle_uio_t *handle, int* range); - -/** - * Returns current position of ADC write pointer. - * @param pos Write pointer position - * @return If the function is successful, the return value is RP_OK. - * If the function is unsuccessful, the return value is any of RP_E* values that indicate an error. - */ -int rp_AcqGetWritePointer(rp_handle_uio_t *handle, uint32_t* pos); - -/** - * Returns position of ADC write pointer at time when trigger arrived. - * @param pos Write pointer position - * @return If the function is successful, the return value is RP_OK. - * If the function is unsuccessful, the return value is any of RP_E* values that indicate an error. - */ -int rp_AcqGetWritePointerAtTrig(rp_handle_uio_t *handle, uint32_t* pos); - -/** - * Starts the acquire. Signals coming from the input channels are acquired and written into memory. - * @return If the function is successful, the return value is RP_OK. - * If the function is unsuccessful, the return value is any of RP_E* values that indicate an error. - */ -int rp_AcqStart(rp_handle_uio_t *handle); - -/** -* Stops the acquire. -* @return If the function is successful, the return value is RP_OK. -* If the function is unsuccessful, the return value is any of RP_E* values that indicate an error. -*/ -int rp_AcqStop(rp_handle_uio_t *handle); - -/** - * Resets the acquire writing state machine. - * @return If the function is successful, the return value is RP_OK. - * If the function is unsuccessful, the return value is any of RP_E* values that indicate an error. - */ -int rp_AcqReset(rp_handle_uio_t *handle); - -/** - * Returns the latest ADC buffer samples in Volt units. - * Output buffer must be at least 'size' long. - * @param channel Channel A or B for which we want to retrieve the ADC buffer. - * @param size Length of the ADC buffer to retrieve. Returns length of filled buffer. In case of too small buffer, required size is returned. - * @param buffer The output buffer gets filled with the selected part of the ADC buffer. - * @return If the function is successful, the return value is RP_OK. - * If the function is unsuccessful, the return value is any of RP_E* values that indicate an error. - */ -int rp_AcqGetData(rp_handle_uio_t *handle, uint32_t* size, int16_t *buffer); - - -int rp_AcqGetBufSize(rp_handle_uio_t *handle, uint32_t* size); - - -#endif // SRC_ACQUIRE_H_ diff --git a/api2/src/calib.c b/api2/src/calib.c deleted file mode 100644 index b96a058bf..000000000 --- a/api2/src/calib.c +++ /dev/null @@ -1,185 +0,0 @@ -/** - * $Id: $ - * - * @brief Red Pitaya Calibration Module. - * - * @Author Red Pitaya - * - * (c) Red Pitaya http://www.redpitaya.com - * - * This part of code is written in C programming language. - * Please visit http://en.wikipedia.org/wiki/C_(programming_language) - * for more details on the language used herein. - */ - -#include -#include -#include -#include - -#include -#include "common.h" -#include "calib.h" - -int rp_CalibOpen(char *dev, rp_handle_uio_t *handle) { - handle->length = RP_CALIB_BASE_SIZE; - int status = common_Open (dev, handle); - if (status != RP_OK) { - return status; - } - - // allocate local context - handle->context = (rp_calib_context_t *) malloc(sizeof(rp_calib_context_t)); - // initialization - rp_calib_context_t *context = (rp_calib_context_t *) handle->context; - context->chn = 2; - for (int unsigned i=0; ichn; i++) { - context->range [i] = 1; - } - rp_CalibReadParams(context); - rp_CalibSetParams(handle); - return RP_OK; -} - -int rp_CalibClose(rp_handle_uio_t *handle) { - int status = common_Close (handle); - if (status != RP_OK) { - return status; - } - // free context - free(handle->context); - return RP_OK; -} - -/** - * @brief Reset calibration parameters to default values and write them into regset. - * - * Default values for calibration are based on an ideal hardware. - * - * @param[out] calib_params Pointer to destination buffer. - * @retval RP_OK - Success - */ -int rp_CalibrationReset(rp_handle_uio_t *handle) { - rp_calib_context_t *context = (rp_calib_context_t *) handle->context; - for (int range=0; range<2; range++) { - for (int ch=0; ch<2; ch++) { - context->acq[ch][range].offset = 0.0; - context->acq[ch][range].gain = 1.0; - } - } - for (int ch=0; ch<2; ch++) { - context->gen[ch].offset = 0.0; - context->gen[ch].gain = 1.0; - } - rp_CalibSetParams(handle); - return RP_OK; -} - -/** - * @brief Read calibration parameters from EEPROM device. - * - * Function reads calibration parameters from EEPROM device and stores them to the - * specified structure. - * - * @param[out] context Pointer to destination buffer. - * @retval RP_OK - Success - * @retval else - Failure - */ -int rp_CalibReadParams(rp_calib_context_t *context) { - int fp; - size_t size; - /* sanity check */ - if (context == NULL) { - return RP_UIA; - } - /* open EEPROM device */ - fp = open(RP_CALIB_EEPROM_PATH, O_RDONLY); - if (!fp) { - return RP_EOED; - } - /* ...and seek to the appropriate storage offset */ - if (lseek(fp, RP_CALIB_EEPROM_ADDR, SEEK_SET) < 0) { - close(fp); - return RP_FCA; - } - /* read data from EEPROM component and store it to the specified buffer */ - size = read(fp, context, sizeof(rp_calib_context_t)); - if (size != sizeof(rp_calib_context_t)) { - close(fp); - return RP_RCA; - } - close(fp); - return RP_OK; -} - -/** - * @brief Write calibration parameters to EEPROM device. - * - * Function writes calibration parameters from specified structure to EEPROM devic. - * - * @param[out] context Pointer to destination buffer. - * @retval RP_OK - Success - * @retval else - Failure - */ -int rp_CalibWriteParams(rp_calib_context_t *context) { - int fp; - size_t size; - /* open EEPROM device */ - fp = open(RP_CALIB_EEPROM_PATH, O_WRONLY); - if (!fp) { - return RP_EOED; - } - /* ...and seek to the appropriate storage offset */ - if (lseek(fp, RP_CALIB_EEPROM_ADDR, SEEK_SET) < 0) { - close(fp); - return RP_FCA; - } - /* write data to EEPROM component */ - size = write(fp, context, sizeof(rp_calib_context_t)); - if (size != sizeof(rp_calib_context_t)) { - close(fp); - return RP_RCA; - } - close(fp); - return RP_OK; -} - -/** - * @return RP_OK - */ -int rp_CalibGetParams(rp_handle_uio_t *handle) { - rp_calib_context_t *context = (rp_calib_context_t *) handle->context; - rp_calib_regset_t *regset = (rp_calib_regset_t *) handle->regset ; - const int ratio_dwm = 1 << (RP_CALIB_DWM-2); - const int ratio_dws = 1 << (RP_CALIB_DWS-1); - for (int ch=0; chchn; ch++) { - float scale = context->range[ch] ? 20 : 1; - context->acq[ch][context->range[ch]].offset = ((float) ioread32 (®set->acq[ch].sum)) * scale / ratio_dws; - context->acq[ch][context->range[ch]].gain = ((float) ioread32 (®set->acq[ch].mul)) * scale / ratio_dwm; - } - for (int ch=0; chchn; ch++) { - context->gen[ch].offset = ((float) ioread32 (®set->gen[ch].sum)) / ratio_dws; - context->gen[ch].gain = ((float) ioread32 (®set->gen[ch].mul)) / ratio_dwm; - } - return RP_OK; -} - -/** - * @return RP_OK - */ -int rp_CalibSetParams(rp_handle_uio_t *handle) { - rp_calib_context_t *context = (rp_calib_context_t *) handle->context; - rp_calib_regset_t *regset = (rp_calib_regset_t *) handle->regset ; - const int ratio_dwm = 1 << (RP_CALIB_DWM-2); - const int ratio_dws = 1 << (RP_CALIB_DWS-1); - for (int ch=0; chchn; ch++) { - float scale = context->range[ch] ? 20 : 1; - iowrite32 ((int32_t) (context->acq[ch][context->range[ch]].offset / scale * ratio_dws), ®set->acq[ch].sum); - iowrite32 ((int32_t) (context->acq[ch][context->range[ch]].gain / scale * ratio_dwm), ®set->acq[ch].mul); - } - for (int ch=0; chchn; ch++) { - iowrite32 ((int32_t) (context->gen[ch].offset * ratio_dws), ®set->gen[ch].sum); - iowrite32 ((int32_t) (context->gen[ch].gain * ratio_dwm), ®set->gen[ch].mul); - } - return RP_OK; -} diff --git a/api2/src/calib.h b/api2/src/calib.h deleted file mode 100644 index 8b03a0d65..000000000 --- a/api2/src/calib.h +++ /dev/null @@ -1,91 +0,0 @@ -/** - * @brief Red Pitaya Calibration Module. - * @Author Red Pitaya - * (c) Red Pitaya http://www.redpitaya.com - */ - -#ifndef __CALIB_H -#define __CALIB_H - -#include "common.h" - -// Base Housekeeping address -#define RP_CALIB_BASE_SIZE 0x00010000 - -#define RP_CALIB_EEPROM_PATH "/sys/bus/i2c/devices/0-0050/eeprom" -#define RP_CALIB_EEPROM_ADDR 0x0008 - -#define RP_CALIB_DWM 16 -#define RP_CALIB_DWS 14 - -// hardware - calibration gain offset pair -typedef struct { - uint32_t mul; // fixed point signed s1.14 (RP_CALIB_DWM bits) - uint32_t sum; // fixed point unsigned u1.13 (RP_CALIB_DWS bits) -} regset_calib_pair_t; - -// hardware - calibration register set structure -typedef struct { - regset_calib_pair_t acq [2]; - regset_calib_pair_t gen [2]; -} rp_calib_regset_t; - -int rp_CalibOpen(char *dev, rp_handle_uio_t *handle); -int rp_CalibClose(rp_handle_uio_t *handle); - -/** - * Calibration parameters, structure stored in the EEPROM device - */ -typedef struct { - float offset; // in Volts - float gain; // correction ratio -} rp_calib_pair_t; - -typedef struct { - int unsigned chn; - int range[2]; - rp_calib_pair_t acq [2] [2]; - rp_calib_pair_t gen [2]; -} rp_calib_context_t; - -/** -* Calibration reset. -* Default values are written into calibration regisers, EEPROM contents are unchanged. -* @return If the function is successful, the return value is RP_OK. -* If the function is unsuccessful, the return value is any of RP_E* values that indicate an error. -*/ -int rp_CalibReset(rp_handle_uio_t *handle); - -/** -* Get calibration parameters. -* Hardware calibration registers are read and stored into calibration parameter structure. -* @return RP_OK -*/ -int rp_CalibGetParams(rp_handle_uio_t *handle); - -/** -* Set calibration parameters. -* Hardware calibration registers are writen based on calibration parameter structure. -* @return RP_OK -*/ -int rp_CalibSetParams(rp_handle_uio_t *handle); - -/** -* Read calibration parameters. -* The given calibration parameter structure is populated from EEPROM contents. -* @return If the function is successful, the return value is RP_OK. -* If the function is unsuccessful, the return value is any of RP_E* values that indicate an error. -*/ -int rp_CalibReadParams(rp_calib_context_t *context); - -/** -* Write calibration parameters. -* The given calibration parameter structure is written into EEPROM. -* @return If the function is successful, the return value is RP_OK. -* If the function is unsuccessful, the return value is any of RP_E* values that indicate an error. -*/ -int rp_CalibWriteParams(rp_calib_context_t *context); -///@} - - -#endif //__CALIB_H diff --git a/api2/src/generate.c b/api2/src/generate.c deleted file mode 100644 index a15b87eb8..000000000 --- a/api2/src/generate.c +++ /dev/null @@ -1,359 +0,0 @@ -/** - * $Id: $ - * - * @brief Red Pitaya library Generate module interface - * - * @Author Red Pitaya - * - * (c) Red Pitaya http://www.redpitaya.com - * - * This part of code is written in C programming language. - * Please visit http://en.wikipedia.org/wiki/C_(programming_language) - * for more details on the language used herein. - */ - -#include -#include -#include -#include -#include -#include - -#include "common.h" -#include "generate.h" - - -const double c_max_waveform_sample_rate_freq=125e6; -const double c_min_waveform_sample_rate_freq=0; - -int rp_GenOpen(const char *dev, rp_handle_uio_t *handle) { - int status; - - handle->length = GENERATE_BASE_SIZE; - handle->struct_size=sizeof(asg_regset_t); - status = common_Open (dev, handle); - if (status != RP_OK) { - return status; - } - - status = rp_GenReset(handle); - if (status != RP_OK) { - return status; - } - - status=rp_GenDefaultSettings(handle); - if (status != RP_OK) { - return status; - } - return RP_OK; -} - -int rp_GenClose(rp_handle_uio_t *handle) { - - int status = common_Close (handle); - if (status != RP_OK) { - return status; - } - return RP_OK; -} - -int rp_GenDefaultSettings(rp_handle_uio_t *handle) { - rp_GenGlobalTrigSet(handle,RP_TRG_ALL_MASK); - //rp_GenSetFreqPhase(handle, 0, 0); // TODO: not used - rp_GenSetMode(handle, RP_GEN_MODE_BURST); - rp_GenSetBurstModeRepetitions(handle, 0); - rp_GenSetBurstModeDataLen(handle, 1); - rp_GenSetBurstModePeriodLen(handle, 1); - rp_GenOutputDisable(handle,RP_GEN_OUT_ALL_MASK); - return RP_OK; -} - -/** Control registers setter & getter */ -static int rp_GenSetControl(rp_handle_uio_t *handle, uint32_t ctl) { - asg_regset_t *regset = (asg_regset_t *) handle->regset; - iowrite32(ctl, ®set->ctl); - return RP_OK; -} - - -static int rp_GenGetControl(rp_handle_uio_t *handle, uint32_t * ctl) { - asg_regset_t *regset = (asg_regset_t *) handle->regset; - *ctl = ioread32(®set->ctl); - return RP_OK; -} - - -/** Control */ -int rp_GenReset(rp_handle_uio_t *handle) { - - return rp_GenSetControl(handle,RP_CTL_RST_MASK); -} - -int rp_GenRun(rp_handle_uio_t *handle) { - return rp_GenSetControl(handle,RP_CTL_STA_MASK); -} - -int rp_GenStop(rp_handle_uio_t *handle) { - return rp_GenSetControl(handle,RP_CTL_STO_MASK); -} - -int rp_GenTrigger(rp_handle_uio_t *handle) { - return rp_GenSetControl(handle,RP_CTL_SWT_MASK); -} - -int rp_GenIsStopped(rp_handle_uio_t *handle, bool * status){ - uint32_t ctl; - rp_GenGetControl(handle, &ctl); - if(ctl&RP_CTL_STO_MASK){ - *status=true; - } - else{ - *status=false; - } - return RP_OK; -} - -int rp_GenGlobalTrigSet(rp_handle_uio_t *handle, uint32_t mask) -{ - asg_regset_t *regset = (asg_regset_t *) handle->regset; - iowrite32(mask, ®set->trig_mask); - return RP_OK; -} - -// TODO: will be used for analog generator -int rp_GenSetLinear(rp_handle_uio_t *handle, float amplitude, float offset) { - asg_regset_t *regset = (asg_regset_t *) handle->regset; - int32_t mul = (int32_t) (amplitude * (1 << RP_GEN_DWM)); - int32_t sum = (int32_t) (offset * (1 << RP_GEN_DWS)); - iowrite32(mul, ®set->gen_spec.ag_spec.mul); - iowrite32(sum, ®set->gen_spec.ag_spec.sum); - return RP_OK; -} - -int rp_GenGetLinear(rp_handle_uio_t *handle, float *amplitude, float *offset) { - asg_regset_t *regset = (asg_regset_t *) handle->regset; - int32_t mul = ioread32(®set->gen_spec.ag_spec.mul); - int32_t sum = ioread32(®set->gen_spec.ag_spec.sum); - *amplitude = ((float) mul) / (1 << RP_GEN_DWM); - *offset = ((float) sum) / (1 << RP_GEN_DWS); - return RP_OK; -} - -// - -int rp_GenSetStepOffset(rp_handle_uio_t *handle, uint32_t stp, uint32_t off) { - asg_regset_t *regset = (asg_regset_t *) handle->regset; - if (stp >= (1 << (RP_GEN_CWM+RP_GEN_CWF))) { - return RP_EOOR; - } - if (off >= (1 << (RP_GEN_CWM+RP_GEN_CWF))) { - return RP_EOOR; - } - iowrite32(stp-1, ®set->cfg_stp); - iowrite32(off , ®set->cfg_off); - return RP_OK; -} - -int rp_GenGetStepOffset(rp_handle_uio_t *handle, uint32_t *stp, uint32_t *off) { - asg_regset_t *regset = (asg_regset_t *) handle->regset; - *stp = ioread32(®set->cfg_stp); - *off = ioread32(®set->cfg_off); - return RP_OK; -} - -int rp_GenSetFreqPhase(rp_handle_uio_t *handle, double frequency, double phase) { - if(!inrangeDouble(frequency,FREQUENCY_MIN,FREQUENCY_MAX)){ - return RP_EOOR; - } - asg_regset_t *regset = (asg_regset_t *) handle->regset; - uint32_t siz = ioread32(®set->cfg_siz) + 1; - uint32_t stp = (uint32_t) ((double) siz * (frequency / RP_GEN_SR)) - 1; - uint32_t off = (uint32_t) ((double) siz * fmod(phase,360)/360 ) ; - return rp_GenSetStepOffset(handle, stp, off); -} - -int rp_GenGetFreqPhase(rp_handle_uio_t *handle, double *frequency, double *phase) { - asg_regset_t *regset = (asg_regset_t *) handle->regset; - uint32_t siz = ioread32(®set->cfg_siz) + 1; - uint32_t stp, off; - int status = rp_GenGetStepOffset(handle, &stp, &off); - if (status != RP_OK) { - return status; - } - *frequency = (double) (stp + 1) / (double) siz * RP_GEN_SR; - *phase = (double) (off ) / (double) siz * 360 ; - return RP_OK; -} - -int rp_GenSetWaveform(rp_handle_uio_t *handle, uint16_t *waveform, uint32_t size) { - asg_regset_t *regset = (asg_regset_t *) handle->regset; - if(!inrangeUint32(size,1,RP_GEN_SIG_SAMPLES)){ - return RP_EOOR; - } - for (uint32_t i=0; itable[i]); - } - iowrite32((size << RP_GEN_CWF) - 1, ®set->cfg_siz); - return RP_OK; -} - -int rp_GenGetWaveform(rp_handle_uio_t *handle, uint16_t *waveform, uint32_t *size) { - asg_regset_t *regset = (asg_regset_t *) handle->regset; - *size = (ioread32(®set->cfg_siz) + 1) >> RP_GEN_CWF; - for (uint32_t i=0; i<*size; i++) { - waveform[i] = ioread32(®set->table[i]); - } - return RP_OK; -} - -int rp_GenSetWaveformUpCountSeq(rp_handle_uio_t *handle, uint32_t size) { - uint16_t ramp[RP_GEN_SIG_SAMPLES]; - for (uint32_t i=0; iregset; - uint32_t tmp; - tmp = ioread32(®set->cfg_bst); - tmp |= a_mask; - iowrite32(tmp, ®set->cfg_bst); - return RP_OK; -} - -static int rp_GenClearBst(rp_handle_uio_t *handle, uint32_t a_mask) { - asg_regset_t *regset = (asg_regset_t *) handle->regset; - uint32_t tmp; - tmp = ioread32(®set->cfg_bst); - tmp &= ~a_mask; - iowrite32(tmp, ®set->cfg_bst); - return RP_OK; -} - -int rp_GenSetMode(rp_handle_uio_t *handle, RP_GEN_MODE mode) -{ - switch(mode){ - case RP_GEN_MODE_CONTINUOUS: - return rp_GenClearBst(handle, RP_GEN_CFG_BURST_MASK); - break; - case RP_GEN_MODE_BURST: - return rp_GenSetBst(handle, RP_GEN_CFG_BURST_MASK); - break; - default: - return -1; - } - return RP_OK; -} -/* -int rp_GenGetMode(rp_handle_uio_t *handle, RP_GEN_MODE * mode) -{ - asg_regset_t *regset = (asg_regset_t *) handle->regset; - uint32_t tmp; - tmp=ioread32(®set->cfg_bst); - if(tmp&RP_GEN_MODE_BURST){ - *mode=RP_GEN_MODE_BURST; - } - else{ - *mode=RP_GEN_MODE_CONTINUOUS; - } - return RP_OK; -} -*/ - -int rp_GenSetBurstModeRepetitions(rp_handle_uio_t *handle, uint32_t val) -{ - asg_regset_t *regset = (asg_regset_t *) handle->regset; - if(val==RP_GEN_REP_INF){ - iowrite32(2, ®set->cfg_bnm); - return rp_GenSetBst(handle, RP_GEN_CFG_BURST_INF_MASK); - } - else if(inrangeUint32(val,BURST_REPETITIONS_MIN,BURST_REPETITIONS_MAX)){ - iowrite32((val-1), ®set->cfg_bnm); - return rp_GenClearBst(handle, RP_GEN_CFG_BURST_INF_MASK); - } - else{ - return RP_EOOR; - } - return RP_OK; -} - -int rp_GenSetBurstModeDataLen(rp_handle_uio_t *handle, uint32_t length) -{ - asg_regset_t *regset = (asg_regset_t *) handle->regset; - if(!inrangeUint32(length,1,RP_GEN_SIG_SAMPLES)){ - return RP_EOOR; - } - iowrite32((length-1), ®set->cfg_bdl); - return RP_OK; -} - -int rp_GenSetBurstModePeriodLen(rp_handle_uio_t *handle, uint32_t length) -{ - asg_regset_t *regset = (asg_regset_t *) handle->regset; - if(!inrangeUint32(length,BURST_PERIOD_LEN_MIN,BURST_PERIOD_LEN_MAX)){ - return RP_EOOR; - } - iowrite32((length-1), ®set->cfg_bln); - return RP_OK; -} - -int rp_GenOutputEnable(rp_handle_uio_t *handle, uint32_t a_mask) -{ - asg_regset_t *regset = (asg_regset_t *) handle->regset; - uint32_t tmp; - tmp = ioread32(®set->gen_spec.lg_spec.dig_out_en); - tmp |= a_mask; - iowrite32(tmp, ®set->gen_spec.lg_spec.dig_out_en); - iowrite32(0 , ®set->gen_spec.lg_spec.dig_openc ); - return RP_OK; -} - -int rp_GenOutputDisable(rp_handle_uio_t *handle, uint32_t a_mask) -{ - asg_regset_t *regset = (asg_regset_t *) handle->regset; - uint32_t tmp; - tmp = ioread32(®set->gen_spec.lg_spec.dig_out_en); - tmp &= ~a_mask; - iowrite32(tmp, ®set->gen_spec.lg_spec.dig_out_en); - iowrite32(0 , ®set->gen_spec.lg_spec.dig_openc ); - return RP_OK; -} - -int rp_GenSetWaveformSampleRate(rp_handle_uio_t *handle, double * sample_rate) -{ - if(!inrangeDouble(*sample_rate,c_min_waveform_sample_rate_freq,c_max_waveform_sample_rate_freq)){ - return RP_EOOR; - } - uint32_t reg_val=(*sample_rate/(double)RP_GEN_SR)*(double)(1<regset; - iowrite32(reg_val, ®set->cfg_stp); - return RP_OK; -} - -int rp_GenFpgaRegDump(rp_handle_uio_t *handle, uint32_t data_len) -{ - int r; - r=FpgaRegDump("Gen reg",0,(uint32_t*)handle->regset,16); - - { - lg_spec_regset_t *regset = (lg_spec_regset_t *) &(((asg_regset_t*)handle->regset)->gen_spec.lg_spec); - FpgaRegDump("Logic gen reg",0,(uint32_t*)regset,2); - } - - - if(!inrangeUint32(data_len,1,RP_GEN_SIG_SAMPLES)){ - return RP_EOOR; - } - else{ - asg_regset_t *regset = (asg_regset_t *) handle->regset; - r=FpgaRegDump("Pattern/waveform",0,(uint32_t*)regset->table,data_len); - } - return r; -} - diff --git a/api2/src/generate.h b/api2/src/generate.h deleted file mode 100644 index 3e9f035a2..000000000 --- a/api2/src/generate.h +++ /dev/null @@ -1,186 +0,0 @@ -/** - * $Id: $ - * - * @brief Red Pitaya library Generate module interface - * - * @Author Red Pitaya - * - * (c) Red Pitaya http://www.redpitaya.com - * - * This part of code is written in C programming language. - * Please visit http://en.wikipedia.org/wiki/C_(programming_language) - * for more details on the language used herein. - */ -#ifndef __GENERATE_H -#define __GENERATE_H - -#include "common.h" - -#define LEVEL_MAX 1.0 // V -#define AMPLITUDE_MAX 1.0 // V -#define OFFSET_MAX 2.0 // V -#define FREQUENCY_MIN 0 // Hz -#define FREQUENCY_MAX 62.5e6 // Hz -#define PHASE_MIN -360 // deg -#define PHASE_MAX 360 // deg -#define BURST_COUNT_MIN -1 -#define BURST_COUNT_MAX 50000 - -#define BURST_REPETITIONS_MAX 0x0000ffff -#define BURST_REPETITIONS_MIN 1 -#define RP_GEN_REP_INF 0 - -#define BURST_PERIOD_LEN_MAX 0xffffffff -#define BURST_PERIOD_LEN_MIN 1 - -// Base Generate address -#define GENERATE_BASE_SIZE 0x00040000 - -// sampling rate -#define RP_GEN_SR 125000000 -// number of trigger options -#define RP_GEN_TWS RP_MNG+2 -// ASG counter width (mantisa and fraction) -#define RP_GEN_CWM 14 -#define RP_GEN_CWF 16 -// linear -#define RP_GEN_DWO 14 -#define RP_GEN_DWM 16 -#define RP_GEN_DWS 14 - -#define RP_GEN_SIG_SAMPLES (1<<14) ///< 16384 - -/** Mode masks */ -#define RP_GEN_CFG_BURST_MASK (1<<0) ///< if set generator will operate in burst mode, otherwise periodic mode -#define RP_GEN_CFG_BURST_INF_MASK (1<<1) ///< if set cfg_bnm will be inf regardless of cfg_bnm setting - -typedef enum { - RP_GEN_MODE_CONTINUOUS, - RP_GEN_MODE_BURST, -} RP_GEN_MODE; - -// Logic generator specific -/** Output enable */ -#define RP_GEN_OUT_ALL_MASK 0xffff -#define RP_GEN_OUT_PORT0_MASK 0x00ff ///< lower 8 pins (RP hw 1.1 P_GPIO_PORT) -#define RP_GEN_OUT_PORT1_MASK 0xff00 ///< higher 8 pins (RP hw 1.1 N_GPIO_PORT) - -// Analog generator specific -// linear transformation -typedef struct { - int32_t mul; // multiplication (amplitude/gain) - int32_t sum; // summation (offset) -} ag_regset_t; - -typedef struct { - uint32_t dig_out_en; - uint32_t dig_openc; -} lg_spec_regset_t; - -typedef struct { - // control register - uint32_t ctl; ///< control register - uint32_t trig_mask; ///< global trigger registers - uint32_t reserved_08; - uint32_t reserved_0c; - // configuration that is (used only for periodic mode) - uint32_t cfg_siz; ///< len = reg + 1 - uint32_t cfg_off; ///< defines offset from which generation will started - uint32_t cfg_stp; ///< fixed point 16.16 value - uint32_t reserved_1c; - // burst mode - uint32_t cfg_bst; ///< enables & configures burst mode - uint32_t cfg_bdl; ///< burst data length - uint32_t cfg_bln; ///< burst period length (data length + idle length) - uint32_t cfg_bnm; ///< burst repetition number - // status - uint32_t sts_bln; ///< burst period length (data length + idle length) - uint32_t sts_bnm; ///< burst repetition number - // specific regs - union { - lg_spec_regset_t lg_spec; - ag_regset_t ag_spec; - } gen_spec; - // empty space - uint32_t reserved_40[(1<>2)]; - // table - uint32_t table [RP_GEN_SIG_SAMPLES]; -} asg_regset_t; - -/** -* Common functions / controls -*/ -int rp_GenOpen(const char *dev, rp_handle_uio_t *handle); -int rp_GenClose(rp_handle_uio_t *handle); - -int rp_GenReset(rp_handle_uio_t *handle); -int rp_GenRun(rp_handle_uio_t *handle); -int rp_GenStop(rp_handle_uio_t *handle); -int rp_GenTrigger(rp_handle_uio_t *handle); -int rp_GenIsStopped(rp_handle_uio_t *handle, bool * status); -int rp_GenDefaultSettings(); - -int rp_GenGlobalTrigSet(rp_handle_uio_t *handle, uint32_t mask); - -/** -* Sets channel signal peak to peak amplitude. -* @param amplitude Amplitude of the generated signal. From 0 to max value. Max amplitude is 1 -* @param offset DC offset of the generated signal. Max offset is 2. -* @return If the function is successful, the return value is RP_OK. -* If the function is unsuccessful, the return value is any of RP_E* values that indicate an error. -*/ -int rp_GenSetLinear(rp_handle_uio_t *handle, float amplitude, float offset); -int rp_GenGetLinear(rp_handle_uio_t *handle, float *amplitude, float *offset); - -/** -* Sets channel signal frequency. -* @param frequency Frequency of the generated signal in Hz. -* @param phase Phase in degrees of the generated signal. From 0 deg to 180 deg. -* @return If the function is successful, the return value is RP_OK. -* If the function is unsuccessful, the return value is any of RP_E* values that indicate an error. -*/ - -int rp_GenSetStepOffset(rp_handle_uio_t *handle, uint32_t stp, uint32_t off); -int rp_GenGetStepOffset(rp_handle_uio_t *handle, uint32_t *stp, uint32_t *off); - -int rp_GenSetFreqPhase(rp_handle_uio_t *handle, double frequency, double phase); -int rp_GenGetFreqPhase(rp_handle_uio_t *handle, double *frequency, double *phase); - -/** Sets mode */ -int rp_GenSetMode(rp_handle_uio_t *handle, RP_GEN_MODE mode); - -/** - * Sets waveform sample rate - * - * @param sample_rate Requested sample rate, on return actual sample rate - */ -int rp_GenSetWaveformSampleRate(rp_handle_uio_t *handle, double * sample_rate); - -/* - * Sets/Gets waveform - */ -int rp_GenSetWaveform(rp_handle_uio_t *handle, uint16_t *waveform, uint32_t size); -int rp_GenGetWaveform(rp_handle_uio_t *handle, uint16_t *waveform, uint32_t *size); -int rp_GenSetWaveformUpCountSeq(rp_handle_uio_t *handle, uint32_t size); - -/* - * Burst mode settings - */ -int rp_GenSetBurstModeRepetitions(rp_handle_uio_t *handle, uint32_t val); -int rp_GenSetBurstModeDataLen(rp_handle_uio_t *handle, uint32_t length); -int rp_GenSetBurstModePeriodLen(rp_handle_uio_t *handle, uint32_t length); ///< TODO: to be fixed - -/* - * Enables/disable physical logic outputs - * @param mask Defines which outputs to enable bits [31-16] (PORT1), bits [15-0] (PORT0) - */ -int rp_GenOutputEnable(rp_handle_uio_t *handle, uint32_t mask); -int rp_GenOutputDisable(rp_handle_uio_t *handle, uint32_t mask); - -/* - * Dumps fpga registers and waveform data - * @param data_len Waveform data length to dump. - */ -int rp_GenFpgaRegDump(rp_handle_uio_t *handle, uint32_t data_len); - -#endif //__GENERATE_H diff --git a/api2/src/id.c b/api2/src/id.c deleted file mode 100644 index 04996729c..000000000 --- a/api2/src/id.c +++ /dev/null @@ -1,65 +0,0 @@ -/** - * @brief Red Pitaya library API interface implementation - * @Author Red Pitaya - * (c) Red Pitaya http://www.redpitaya.com - */ - -#include -#include -#include -#include - -#include -#include - -#include "common.h" -#include "id.h" - -int rp_IdOpen(char *dev, rp_handle_uio_t *handle) { - handle->length = ID_BASE_SIZE; - int status = common_Open (dev, handle); - if (status != RP_OK) { - return status; - } - return RP_OK; -} - -int rp_IdClose(rp_handle_uio_t *handle) { - int status = common_Close (handle); - if (status != RP_OK) { - return status; - } - return RP_OK; -} - -/** - * Identification - */ - -int rp_IdGetID(rp_handle_uio_t *handle, uint32_t *id) { - id_regset_t *regset = (id_regset_t *) handle->regset; - *id = ioread32(®set->id); - return RP_OK; -} - -int rp_IdGetEFUSE(rp_handle_uio_t *handle, uint32_t *efuse) { - id_regset_t *regset = (id_regset_t *) handle->regset; - *efuse = ioread32(®set->efuse); - return RP_OK; -} - -int rp_IdGetDNA(rp_handle_uio_t *handle, uint64_t *dna) { - id_regset_t *regset = (id_regset_t *) handle->regset; - *dna = ((uint64_t) ioread32(®set->dna_hi) << 32) - | ((uint64_t) ioread32(®set->dna_lo) << 0); -// TODO: the current FPGA AXI4 bus implementation does not support 64bit transfers -// *dna = ioread64(®set->dna); - return RP_OK; -} - -int rp_IdGetGITH(rp_handle_uio_t *handle, uint32_t *gith) { - id_regset_t *regset = (id_regset_t *) handle->regset; - for (int unsigned i=0; i<5; i++) - gith[i] = ioread32(®set->gith[i]); - return RP_OK; -} diff --git a/api2/src/id.h b/api2/src/id.h deleted file mode 100644 index 90d3ca6fd..000000000 --- a/api2/src/id.h +++ /dev/null @@ -1,62 +0,0 @@ -/** - * $Id: $ - * - * @brief Red Pitaya library id module interface - * - * @Author Red Pitaya - * - * (c) Red Pitaya http://www.redpitaya.com - * - * This part of code is written in C programming language. - * Please visit http://en.wikipedia.org/wiki/C_(programming_language) - * for more details on the language used herein. - */ - - - -#ifndef __ID_H -#define __ID_H - -#include -#include - -// Base Id address -static const int ID_BASE_SIZE = 0x1000; - -// Id structure declaration -typedef struct { - uint32_t id; // 0x00 - uint32_t reserved_04; // 0x04 - uint32_t efuse; // 0x08 - uint32_t reserved_0c; // 0x0c -// TODO: the current FPGA AXI4 bus implementation does not support 64bit transfers -// uint64_t dna; // 0x10 - uint32_t dna_lo; // 0x10 - uint32_t dna_hi; // 0x14 - uint32_t reserved_18; // 0x18 - uint32_t reserved_1c; // 0x1c - uint32_t gith[5]; // 0x20 - 0x30 -} id_regset_t; - -int rp_IdOpen(char *dev, rp_handle_uio_t *handle); -int rp_IdClose(rp_handle_uio_t *handle); - -/** -* Gets FPGA Synthesized ID -*/ -int rp_IdGetID(rp_handle_uio_t *handle, uint32_t *id); - -/** -* Gets FPGA EFUSE -*/ -int rp_IdGetEFUSE(rp_handle_uio_t *handle, uint32_t *efuse); - -/** -* Gets FPGA Unique DNA -*/ -int rp_IdGetDNA(rp_handle_uio_t *handle, uint64_t *dna); - -// get 160 bit GIT HASH -int rp_IdGetGITH(rp_handle_uio_t *handle, uint32_t *gith); - -#endif //__ID_H diff --git a/api2/src/la_acq.c b/api2/src/la_acq.c index 0f9d76958..decc856d3 100644 --- a/api2/src/la_acq.c +++ b/api2/src/la_acq.c @@ -22,7 +22,6 @@ #include #include "common.h" -#include "generate.h" #include "la_acq.h" #include "rp_dma.h" @@ -49,7 +48,7 @@ int rp_LaAcqOpen(const char *dev, rp_handle_uio_t *handle) { return status; } - status = rp_DmaOpen("/dev/rprx", handle); + status = rp_DmaOpen("/dev/amba_pl:rprx@2", handle); if (status != RP_OK) { return status; } diff --git a/api2/src/muxctl.c b/api2/src/muxctl.c deleted file mode 100644 index 98069c08e..000000000 --- a/api2/src/muxctl.c +++ /dev/null @@ -1,79 +0,0 @@ -/** - * @brief Red Pitaya library API interface implementation - * @Author Red Pitaya - * (c) Red Pitaya http://www.redpitaya.com - */ - -#include -#include - -#include "common.h" -#include "muxctl.h" - -int rp_MuxctlOpen(char *dev, rp_handle_uio_t *handle) { - handle->length = MUXCTL_BASE_SIZE; - int status = common_Open (dev, handle); - if (status != RP_OK) { - return status; - } - return RP_OK; -} - -int rp_MuxctlClose(rp_handle_uio_t *handle) { - int status = common_Close (handle); - if (status != RP_OK) { - return status; - } - return RP_OK; -} - -int rp_MuxctlReset(rp_handle_uio_t *handle) { - muxctl_regset_t *regset = (muxctl_regset_t *) handle->regset; - iowrite32(0, ®set->loop); - iowrite32(0, ®set->gen ); - iowrite32(0, ®set->lg ); - return RP_OK; -} - -// Loop - -int rp_MuxctlSetLoop(rp_handle_uio_t *handle, uint32_t mux) { - muxctl_regset_t *regset = (muxctl_regset_t *) handle->regset; - iowrite32(mux, ®set->loop); - return RP_OK; -} - -int rp_MuxctlGetLoop(rp_handle_uio_t *handle, uint32_t *mux) { - muxctl_regset_t *regset = (muxctl_regset_t *) handle->regset; - *mux = ioread32(®set->loop); - return RP_OK; -} - -// Gen - -int rp_MuxctlSetGen(rp_handle_uio_t *handle, uint32_t mux) { - muxctl_regset_t *regset = (muxctl_regset_t *) handle->regset; - iowrite32(mux, ®set->gen); - return RP_OK; -} - -int rp_MuxctlGetGen(rp_handle_uio_t *handle, uint32_t *mux) { - muxctl_regset_t *regset = (muxctl_regset_t *) handle->regset; - *mux = ioread32(®set->gen); - return RP_OK; -} - -// LG - -int rp_MuxctlSetLg(rp_handle_uio_t *handle, uint32_t mux) { - muxctl_regset_t *regset = (muxctl_regset_t *) handle->regset; - iowrite32(mux, ®set->lg); - return RP_OK; -} - -int rp_MuxctlGetLg(rp_handle_uio_t *handle, uint32_t *mux) { - muxctl_regset_t *regset = (muxctl_regset_t *) handle->regset; - *mux = ioread32(®set->lg); - return RP_OK; -} - diff --git a/api2/src/muxctl.h b/api2/src/muxctl.h deleted file mode 100644 index 3a62cf811..000000000 --- a/api2/src/muxctl.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * $Id: $ - * - * @brief Red Pitaya library muxctl module interface - * - * @Author Red Pitaya - * - * (c) Red Pitaya http://www.redpitaya.com - * - * This part of code is written in C programming language. - * Please visit http://en.wikipedia.org/wiki/C_(programming_language) - * for more details on the language used herein. - */ - -#ifndef __MUXCTL_H -#define __MUXCTL_H - -#include -#include - -// Base Muxctl address -static const int MUXCTL_BASE_SIZE = 0x30; - -// Muxctl structure declaration -typedef struct { - uint32_t loop; - uint32_t gen ; - uint32_t lg ; -} muxctl_regset_t; - -int rp_MuxctlOpen(char *dev, rp_handle_uio_t *handle); -int rp_MuxctlClose(rp_handle_uio_t *handle); -int rp_MuxctlReset(rp_handle_uio_t *handle); - -int rp_MuxctlSetGpio(rp_handle_uio_t *handle, uint32_t mux); -int rp_MuxctlGetGpio(rp_handle_uio_t *handle, uint32_t *mux); - -int rp_MuxctlSetLoop(rp_handle_uio_t *handle, uint32_t mux); -int rp_MuxctlGetLoop(rp_handle_uio_t *handle, uint32_t *mux); - -int rp_MuxctlSetGen (rp_handle_uio_t *handle, uint32_t mux); -int rp_MuxctlGetGen (rp_handle_uio_t *handle, uint32_t *mux); - -int rp_MuxctlSetLg (rp_handle_uio_t *handle, uint32_t mux); -int rp_MuxctlGetLg (rp_handle_uio_t *handle, uint32_t *mux); - -#endif //__MUXCTL_H diff --git a/api2/src/pdm.c b/api2/src/pdm.c deleted file mode 100644 index b67900c4c..000000000 --- a/api2/src/pdm.c +++ /dev/null @@ -1,88 +0,0 @@ -/** - * $Id: $ - * - * @brief Red Pitaya library API interface implementation - * - * @Author Red Pitaya - * - * (c) Red Pitaya http://www.redpitaya.com - * - * This part of code is written in C programming language. - * Please visit http://en.wikipedia.org/wiki/C_(programming_language) - * for more details on the language used herein. - */ - -#include -#include -#include -#include -#include - -#include -#include "common.h" -#include "pdm.h" - -int rp_PdmOpen(char *dev, rp_handle_uio_t *handle) { - handle->length = PDM_BASE_SIZE; - int status = common_Open (dev, handle); - if (status != RP_OK) { - return status; - } - return RP_OK; -} - -int rp_PdmClose(rp_handle_uio_t *handle) { - int status = common_Close (handle); - if (status != RP_OK) { - return status; - } - return RP_OK; -} - -int rp_PdmReset(rp_handle_uio_t *handle) { - for (int unsigned pin=0; pin<4; pin++) { - rp_PdmSetValueRaw(handle, pin, 0); - } - return RP_OK; -} - -int rp_PdmSetValueRaw(rp_handle_uio_t *handle, int unsigned pin, uint32_t value) { - pdm_regset_t *regset = (pdm_regset_t *) handle->regset; - if (pin >= 4) { - return RP_EPN; - } - if (value > PDM_MAX_VAL_INTEGER) { - return RP_EOOR; - - } - iowrite32(value & PDM_MASK, ®set->pdm_cfg[pin]); - return RP_OK; -} - -int rp_PdmSetValue(rp_handle_uio_t *handle, int unsigned pin, float value) { - uint32_t value_raw = (uint32_t) (((value - PDM_MIN_VAL) / (PDM_MAX_VAL - PDM_MIN_VAL)) * PDM_MAX_VAL_INTEGER); - return rp_PdmSetValueRaw(handle, pin, value_raw); -} - -int rp_PdmGetValueRaw(rp_handle_uio_t *handle, int unsigned pin, uint32_t* value) { - pdm_regset_t *regset = (pdm_regset_t *) handle->regset; - if (pin >= 4) { - return RP_EPN; - } - *value = ioread32(®set->pdm_cfg[pin]) & PDM_MASK; - return RP_OK; -} - -int rp_PdmGetValue(rp_handle_uio_t *handle, int unsigned pin, float* value) { - uint32_t value_raw; - int result = rp_PdmGetValueRaw(handle, pin, &value_raw); - *value = (((float)value_raw / PDM_MAX_VAL_INTEGER) * (PDM_MAX_VAL - PDM_MIN_VAL)) + PDM_MIN_VAL; - return result; -} - -int rp_PdmGetRange(rp_handle_uio_t *handle, int unsigned pin, float* min_val, float* max_val) { - *min_val = PDM_MIN_VAL; - *max_val = PDM_MAX_VAL; - return RP_OK; -} - diff --git a/api2/src/pdm.h b/api2/src/pdm.h deleted file mode 100644 index 96c454abf..000000000 --- a/api2/src/pdm.h +++ /dev/null @@ -1,66 +0,0 @@ -/** - * $Id: $ - * - * @brief Red Pitaya library Analog Mixed Signals (AMS) module interface - * - * @Author Red Pitaya - * - * (c) Red Pitaya http://www.redpitaya.com - * - * This part of code is written in C programming language. - * Please visit http://en.wikipedia.org/wiki/C_(programming_language) - * for more details on the language used herein. - */ - -#ifndef __ANALOG_MIXED_SIGNALS_H -#define __ANALOG_MIXED_SIGNALS_H - -// Base Analog Mixed Signals address -static const int PDM_BASE_SIZE = 0x30; - -typedef struct { - uint32_t pdm_cfg [4]; -} pdm_regset_t; - -static const uint32_t PDM_MASK = 0xFF; - -static const float PDM_MAX_VAL = 1.8; -static const float PDM_MIN_VAL = 0.0; -static const uint32_t PDM_MAX_VAL_INTEGER = 255; - -int rp_PdmOpen(char *dev, rp_handle_uio_t *handle); -int rp_PdmClose(rp_handle_uio_t *handle); - -/** -* Sets analog outputs to default values (0V). -*/ -int rp_PdmReset(rp_handle_uio_t *handle); - -/** - * Gets value from analog pin in volts. - * @param pin Analog output pin index. - * @param value Value on analog pin in volts - * @return RP_OK - successful, RP_E* - failure - */ -int rp_PdmGetValue(rp_handle_uio_t *handle, int unsigned pin, float* value); -int rp_PdmSetValue(rp_handle_uio_t *handle, int unsigned pin, float value); - -/** - * Gets raw value from analog pin. - * @param pin Analog output pin index. - * @param value Raw value on analog pin - * @return RP_OK - successful, RP_E* - failure - */ -int rp_PdmGetValueRaw(rp_handle_uio_t *handle, int unsigned pin, uint32_t* value); -int rp_PdmSetValueRaw(rp_handle_uio_t *handle, int unsigned pin, uint32_t value); - -/** - * Gets range in volts on specific pin. - * @param pin Analog input output pin index. - * @param min_val Minimum value in volts on given pin. - * @param max_val Maximum value in volts on given pin. - * @return RP_OK - successful, RP_E* - failure - */ -int rp_PdmGetRange(rp_handle_uio_t *handle, int unsigned pin, float* min_val, float* max_val); - -#endif //__ANALOG_MIXED_SIGNALS_H diff --git a/api2/src/rp2.c b/api2/src/rp2.c deleted file mode 100644 index faf33bee2..000000000 --- a/api2/src/rp2.c +++ /dev/null @@ -1,54 +0,0 @@ -/** - * $Id: $ - * - * @brief Red Pitaya library API interface implementation - * - * @Author Red Pitaya - * - * (c) Red Pitaya http://www.redpitaya.com - * - * This part of code is written in C programming language. - * Please visit http://en.wikipedia.org/wiki/C_(programming_language) - * for more details on the language used herein. - */ - -#include -#include - -#include "common.h" -#include "pdm.h" -#include "id.h" -#include "acquire.h" -#include "calib.h" -#include "generate.h" -#include "rp_api.h" - -const char* rp_GetError(int errorCode) { - switch (errorCode) { - case RP_OK : return "OK"; - case RP_EOED: return "Failed to Open EEPROM Device."; - case RP_EOMD: return "Failed to open memory device."; - case RP_ECMD: return "Failed to close memory device."; - case RP_EMMD: return "Failed to map memory device."; - case RP_EUMD: return "Failed to unmap memory device."; - case RP_EOOR: return "Value out of range."; - case RP_ELID: return "LED input direction is not valid."; - case RP_EMRO: return "Modifying read only filed is not allowed."; - case RP_EWIP: return "Writing to input pin is not valid."; - case RP_EPN : return "Invalid Pin number."; - case RP_UIA : return "Uninitialized Input Argument."; - case RP_FCA : return "Failed to Find Calibration Parameters."; - case RP_RCA : return "Failed to Read Calibration Parameters."; - case RP_BTS : return "Buffer too small"; - case RP_EIPV: return "Invalid parameter value"; - case RP_EUF : return "Unsupported Feature"; - case RP_ENN : return "Data not normalized"; - case RP_EFOB: return "Failed to open bus"; - case RP_EFCB: return "Failed to close bus"; - case RP_EABA: return "Failed to acquire bus access"; - case RP_EFRB: return "Failed to read from the bus"; - case RP_EFWB: return "Failed to write to the bus"; - default: return "Unknown error"; - } -} - diff --git a/api2/src/rp_api.c b/api2/src/rp_api.c index a46f483a1..ba2eccb3d 100644 --- a/api2/src/rp_api.c +++ b/api2/src/rp_api.c @@ -10,7 +10,6 @@ #include #include "common.h" -#include "generate.h" #include "la_acq.h" @@ -32,84 +31,25 @@ bool g_acq_running=false; /** * Open device */ -RP_STATUS rp_OpenUnit(void) -{ +RP_STATUS rp_OpenUnit(void) { int r=RP_API_OK; - if(rp_LaAcqOpen("/dev/uio/la", &la_acq_handle)!=RP_API_OK){ r=-1; } - - //rp_LaAcqFpgaRegDump(&la_acq_handle); - - if(rp_GenOpen("/dev/uio/lg", &sig_gen_handle)!=RP_API_OK){ - r=-1; - } return r; } /** * Close device */ -RP_STATUS rp_CloseUnit(void) -{ +RP_STATUS rp_CloseUnit(void) { int r=RP_API_OK; - if(rp_LaAcqClose(&la_acq_handle)!=RP_API_OK){ r=-1; } - - if(rp_GenClose(&sig_gen_handle)!=RP_API_OK){ - r=-1; - } - return r; } -/** - * This function retrieves information about the specified device. - * If the device fails to open or no device is opened, only the driver version is available. - * - * @param string On exit, the information string selected specified by the info argument. - * If string is NULL, only requiredSize is returned. - * @param stringLength On entry, the maximum number of int8_t that may be written to string. - * @param requiredSize On exit, the required length of the string array. - * @param info A number specifying what information is required. The possible values are listed in the table below. - */ -RP_STATUS rp_GetUnitInfo(int8_t * string, - int16_t stringLength, - int16_t * requiredSize, - RP_INFO info) -{ - - - return RP_API_OK; -} - - -/** - * Enable digital port - * - * This function is used to enable the digital port and set the logic level (the voltage at - * which the state transitions from 0 to 1). - * - * @param port Identifies the port for digital data - * @param enabled Whether or not to enable the channel. - * @param logiclevel The voltage at which the state transitions between 0 - * and 1. Range: –32767 (–5 V) to 32767 (5 V). - * - */ -RP_STATUS rp_SetDigitalPort(RP_DIGITAL_PORT port, - int16_t enabled, - int16_t logiclevel) -{ - // TODO: - // RP_DIGITAL_PORT0 - // RP_DIGITAL_PORT1 - return RP_API_OK; -} - - /** * Enable digital port * @@ -281,30 +221,17 @@ RP_STATUS rp_GetTimebase(uint32_t timebase, * * This function tells the driver where to store the data. * - * @param channel The channel you want to use with the buffer. * @param buffer The location of the buffer * @param bufferLth The size of the buffer array (notice that one sample is 16 bits) * */ -RP_STATUS rp_SetDataBuffer(RP_CHANNEL channel, - int16_t * buffer, +RP_STATUS rp_SetDataBuffer( int16_t * buffer, int32_t bufferLth, // uint32_t segmentIndex, - RP_RATIO_MODE mode) -{ - switch(channel){ - case RP_CH_AIN1: - case RP_CH_AIN2: - case RP_CH_AIN3: - case RP_CH_AIN4: - break; - case RP_CH_DIN: + RP_RATIO_MODE mode) { acq_data.buf = buffer; acq_data.buf_size = bufferLth; return RP_API_OK; - break; - } - return RP_INVALID_PARAMETER; } @@ -396,8 +323,6 @@ RP_STATUS rp_RunBlock(uint32_t noOfPreTriggerSamples, return RP_BLOCK_MODE_FAILED; } - // rp_DmaMemDump(&la_acq_handle); - uint32_t trig_sample; uint32_t last_sample; @@ -754,166 +679,3 @@ RP_STATUS rp_Stop(void){ //return rp_LaAcqStopAcq(&la_acq_handle); } -/** SIGNAL GENERATION */ -/** - * This function causes a trigger event, or starts and stops gating. - * It is used when the signal generator is set to SIGGEN_SOFT_TRIG. - * - * @param state, sets the trigger gate high or low when the trigger type is - * set to either SIGGEN_GATE_HIGH or SIGGEN_GATE_LOW. Ignored for other trigger types. - */ - -RP_STATUS rp_SigGenSoftwareControl(int16_t state){ - rp_GenTrigger(&sig_gen_handle); - return RP_API_OK; -} - -/** - * This function sets up the signal generator to produce a signal from a list of built-in - * waveforms. If different start and stop frequencies are specified, the device will sweep - * either up, down or up and down. - * - * @param offsetVoltage The voltage offset, in microvolts, to be applied to the waveform - * @param pkToPk The peak-to-peak voltage, in microvolts, of the waveform signal. - * Note that if the signal voltages described by the combination of offsetVoltage and pkToPk - * extend outside the voltage range of the signal generator, the output waveform will be clipped. - * @param waveType The type of waveform to be generated. - * @param startFrequency The frequency that the signal generator will initially produce. - * For allowable values see RP_SINE_MAX_FREQUENCY and related values. - * @param stopFrequency The frequency at which the sweep reverses direction or returns to the initial frequency. - * @param increment The amount of frequency increase or decrease in sweep mode. - * @param dwellTime The time for which the sweep stays at each frequency in seconds. - * @param sweepType Whether the frequency will sweep from startFrequency to stopFrequency, or in the opposite direction, - * or repeatedly reverse direction. - * @param operation The type of extra waveform to be produced. - * @param shots 0: Sweep the frequency as specified by sweeps - * 1...RP_MAX_SWEEPS_SHOTS: the number of cycles of the waveform to be produced after a trigger event. - * Sweeps must be zero. - * RP_SHOT_SWEEP_TRIGGER_CONTINUOUS_RUN: start and run continuously after trigger occurs - * @param sweeps 0: produce number of cycles specified by shots - * 1..RP_MAX_SWEEPS_SHOTS: the number of times to sweep the frequency after a trigger event, according to sweepType. - * shots must be zero. - * RP_SHOT_SWEEP_TRIGGER_CONTINUOUS_RUN: start a sweep and continue after trigger occurs. - * @param triggerType The type of trigger that will be applied to the signal generator. - * @param triggerSource The source that will trigger the signal generator - * @param extInThreshold Used to set trigger level for external trigger. - */ - -RP_STATUS rp_SetSigGenBuiltIn(int32_t offsetVoltage, - uint32_t pkToPk, - RP_WAVE_TYPE waveType, - float startFrequency, - float stopFrequency, - float increment, - float dwellTime, - RP_SWEEP_TYPE sweepType, - RP_EXTRA_OPERATIONS operation, - uint32_t shots, - uint32_t sweeps, - RP_SIGGEN_TRIG_TYPE triggerType, - RP_SIGGEN_TRIG_SOURCE triggerSource, - int16_t extInThreshold){ - - //rp_GenSetAmp(&sig_gen_handle,1.0); - //rp_GenSetOffset(&sig_gen_handle, 1.0); - - - // triggerType - switch(triggerSource){ - case RP_SIGGEN_NONE: - break; - case RP_SIGGEN_SCOPE_TRIG: - break; - case RP_SIGGEN_EXT_IN: - break; - case RP_SIGGEN_SOFT_TRIG: - break; - case RP_SIGGEN_TRIGGER_RAW: - break; - } - - switch(waveType){ - case RP_SG_SINE: - break; - case RP_SG_SQUARE: - break; - case RP_SG_TRIANGLE: - break; - case RP_SG_DC_VOLTAGE: - break; - case RP_SG_RAMP_UP: - break; - case RP_SG_RAMP_DOWN: - break; - case RP_SG_SINC: - break; - case RP_SG_GAUSSIAN: - break; - case PR_SG_HALF_SINE: - break; - } - - return RP_API_OK; -} - -/** DIGITAL SIGNAL GENERATION */ - -RP_STATUS rp_DigSigGenOuput(bool enable) -{ - if(enable){ - rp_GenOutputEnable(&sig_gen_handle, RP_GEN_OUT_PORT0_MASK); - } - else{ - rp_GenOutputDisable(&sig_gen_handle, RP_GEN_OUT_PORT0_MASK); - } - return RP_API_OK; -} - -RP_STATUS rp_DigSigGenSoftwareControl(int16_t state) -{ - return rp_GenTrigger(&sig_gen_handle); - // rp_GenFpgaRegDump(&sig_gen_handle,0); -} - -RP_STATUS rp_SetDigSigGenBuiltIn(RP_DIG_SIGGEN_PAT_TYPE patternType, - double * sample_rate, - uint32_t shots, - uint32_t delay_between_shots, - uint32_t triggerSourceMask) -{ - rp_GenReset(&sig_gen_handle); // TODO: stop not working that's why reset is needed here - rp_GenStop(&sig_gen_handle); - - // set burst mode - dig. sig. gen will always operate in this mode! - rp_GenSetMode(&sig_gen_handle, RP_GEN_MODE_BURST); - - // set waveform - uint32_t len = 256; - switch(patternType){ - case RP_DIG_SIGGEN_PAT_UP_COUNT_8BIT_SEQ_256: - rp_GenSetWaveformUpCountSeq(&sig_gen_handle,len); - rp_GenSetBurstModeDataLen(&sig_gen_handle,len); - rp_GenSetBurstModePeriodLen(&sig_gen_handle,len); - break; - } - - // repetitions - rp_GenSetBurstModeRepetitions(&sig_gen_handle, shots); - - // no idle - // rp_GenSetBurstModeIdle(&sig_gen_handle, delay_between_shots); - - // sample rate - rp_GenSetWaveformSampleRate(&sig_gen_handle,sample_rate); - - // trigger - rp_GenGlobalTrigSet(&sig_gen_handle, triggerSourceMask); - - rp_GenRun(&sig_gen_handle); - - //rp_GenFpgaRegDump(&sig_gen_handle,len); - - return RP_API_OK; -} - -// TODO: add function that will generate protocol from file diff --git a/api2/src/rp_api.h b/api2/src/rp_api.h index cf8824c37..c33155bf4 100644 --- a/api2/src/rp_api.h +++ b/api2/src/rp_api.h @@ -5,18 +5,6 @@ #include #include -typedef enum { - RP_DRIVER_VERSION, ///< Version number of Red Pitaya APIs - RP_USB_VERSION, ///< Type of USB connection to device: 1.1, 2.0 or 3.0 - RP_HARDWARE_VERSION, ///< Hardware version of device - RP_VARIANT_INFO, ///< Variant number of device - RP_BATCH_AND_SERIAL, ///< Batch and serial number of device - RP_CAL_DATE, ///< Calibration date of device - RP_KERNEL_VERSION, ///< Version of kernel driver - RP_DIGITAL_HARDWARE_VERSION, ///< Hardware version of the digital section - RP_ANALOGUE_HARDWARE_VERSION, ///< Hardware version of the analog section -} RP_INFO; - typedef enum { RP_API_OK, ///< The Red Pitaya is functioning correctly RP_MAX_UNITS_OPENED, ///< An attempt has been made to open more than RP_MAX_UNITS. @@ -134,23 +122,7 @@ typedef enum { RP_USB3_0_DEVICE_NON_USB3_0_PORT, ///< A USB 3.0 device is connected to a non-USB 3.0 port. } RP_STATUS; - -typedef enum rpDigitalPort { - RP_DIGITAL_PORT0 = 0x80, // (digital channels 0–7) - RP_DIGITAL_PORT1 = 0x81 // (digital channels 8–15) -} RP_DIGITAL_PORT; - - -typedef enum rpChannel { - RP_CH_AIN1=0, - RP_CH_AIN2, - RP_CH_AIN3, - RP_CH_AIN4, - RP_CH_DIN -} RP_CHANNEL; - -typedef enum rpDigitalChannel -{ +typedef enum rpDigitalChannel { RP_DIGITAL_CHANNEL_0, RP_DIGITAL_CHANNEL_1, RP_DIGITAL_CHANNEL_2, @@ -170,8 +142,7 @@ RP_DIGITAL_CHANNEL_15, RP_MAX_DIGITAL_CHANNELS } RP_DIGITAL_CHANNEL; -typedef enum rpDigitalDirection -{ +typedef enum rpDigitalDirection { RP_DIGITAL_DONT_CARE, RP_DIGITAL_DIRECTION_LOW, RP_DIGITAL_DIRECTION_HIGH, @@ -182,23 +153,20 @@ typedef enum rpDigitalDirection } RP_DIGITAL_DIRECTION; -typedef struct tPS3000ADigitalChannelDirections -{ +typedef struct tPS3000ADigitalChannelDirections { RP_DIGITAL_CHANNEL channel; RP_DIGITAL_DIRECTION direction; } RP_DIGITAL_CHANNEL_DIRECTIONS; -typedef enum rpRatioMode -{ +typedef enum rpRatioMode { RP_RATIO_MODE_NONE, //(downSampleRatio is ignored) RP_RATIO_MODE_AGGREGATE, RP_RATIO_MODE_AVERAGE, RP_RATIO_MODE_DECIMATE } RP_RATIO_MODE; -typedef enum rpTimeUnits -{ +typedef enum rpTimeUnits { RP_FS, RP_PS, RP_NS, @@ -223,11 +191,6 @@ RP_STATUS rp_OpenUnit(void); RP_STATUS rp_CloseUnit(void); -RP_STATUS rp_GetUnitInfo(int8_t * string, - int16_t stringLength, - int16_t * requiredSize, - RP_INFO info); - RP_STATUS rp_SetTriggerDigitalPortProperties(RP_DIGITAL_CHANNEL_DIRECTIONS * directions, int16_t nDirections); @@ -244,8 +207,7 @@ RP_STATUS rp_GetTimebase(uint32_t timebase, //uint32_t segmentIndex ); -RP_STATUS rp_SetDataBuffer(RP_CHANNEL channel, - int16_t * buffer, +RP_STATUS rp_SetDataBuffer(int16_t * buffer, int32_t bufferLth, // uint32_t segmentIndex, RP_RATIO_MODE mode); @@ -291,84 +253,6 @@ RP_STATUS rp_GetValuesAsync(uint32_t startIndex, RP_STATUS rp_Stop(void); - -/** SIGNAL GENERATION */ - -typedef enum rpWaveType { - RP_SG_SINE, ///< sine wave - RP_SG_SQUARE, ///< square wave - RP_SG_TRIANGLE, ///< triangle wave - RP_SG_DC_VOLTAGE, ///< DC voltage - RP_SG_RAMP_UP, ///< rising sawtooth - RP_SG_RAMP_DOWN, ///< falling sawtooth - RP_SG_SINC, ///< sin (x)/x - RP_SG_GAUSSIAN, ///< Gaussian - PR_SG_HALF_SINE, ///< half (full-wave rectified) sine -} RP_WAVE_TYPE; - -typedef enum rpSweepType{ - RP_SWEEP_UP, ///< - RP_SWEEP_DOWN, ///< - RP_SWEEP_UPDOWN, ///< - RP_SWEEP_DOWNUP, ///< -} RP_SWEEP_TYPE; - - -typedef enum rpExtraOperationType{ - RP_ES_OFF, ///< normal signal generator operation specified by wavetype. - RP_WHITENOISE, ///< the signal generator produces white noise and ignores all settings except pkToPk and offsetVoltage. - RP_PRBS, ///< produces a pseudorandom binary sequence with bit rate specified by the start and stop frequencies. -} RP_EXTRA_OPERATIONS; - - -typedef enum rpTriggerType{ - RP_SIGGEN_RISING, ///< trigger on rising edge - RP_SIGGEN_FALLING, ///< trigger on falling edge - RP_SIGGEN_GATE_HIGH,///< run while trigger is high - RP_SIGGEN_GATE_LOW, ///< run while trigger is low -} RP_SIGGEN_TRIG_TYPE; - - -typedef enum rpTriggerSource { - RP_SIGGEN_NONE, ///< run without waiting for trigger - RP_SIGGEN_SCOPE_TRIG, ///< use scope trigger - RP_SIGGEN_EXT_IN, ///< use EXT input - RP_SIGGEN_SOFT_TRIG, ///< wait for software trigger provided by rpSigGenSoftwareControl() - RP_SIGGEN_TRIGGER_RAW // reserved -} RP_SIGGEN_TRIG_SOURCE; - RP_STATUS rp_SetPolarity(uint32_t reg); -RP_STATUS rp_DigSigGenOuput(bool enable); - -RP_STATUS rp_SigGenSoftwareControl(int16_t state); - -RP_STATUS rp_SetSigGenBuiltIn(int32_t offsetVoltage, - uint32_t pkToPk, - RP_WAVE_TYPE waveType, - float startFrequency, - float stopFrequency, - float increment, - float dwellTime, - RP_SWEEP_TYPE sweepType, - RP_EXTRA_OPERATIONS operation, - uint32_t shots, - uint32_t sweeps, - RP_SIGGEN_TRIG_TYPE triggerType, - RP_SIGGEN_TRIG_SOURCE triggerSource, - int16_t extInThreshold); - -/** DIGITAL SIGNAL GENERATION */ - -typedef enum patternType{ - RP_DIG_SIGGEN_PAT_UP_COUNT_8BIT_SEQ_256, ///< counts 8bit -} RP_DIG_SIGGEN_PAT_TYPE; - -RP_STATUS rp_DigSigGenSoftwareControl(int16_t state); - -RP_STATUS rp_SetDigSigGenBuiltIn(RP_DIG_SIGGEN_PAT_TYPE patternType, - double * sample_rate, - uint32_t shots, - uint32_t delay_between_shots, - uint32_t triggerSourceMask); #endif // _RP_API_H_ diff --git a/api2/src/rp_dma.c b/api2/src/rp_dma.c index b680e04cb..421c7910b 100644 --- a/api2/src/rp_dma.c +++ b/api2/src/rp_dma.c @@ -20,29 +20,24 @@ #define RP_SGMNT_CNT 8 // 240/RP_SGMNT_CNT must be int #define RP_SGMNT_SIZE (256*1024) -int rp_DmaOpen(const char *dev, rp_handle_uio_t *handle) -{ +int rp_DmaOpen(const char *dev, rp_handle_uio_t *handle) { // make a copy of the device path handle->dma_dev = (char*) malloc((strlen(dev)+1) * sizeof(char)); strncpy(handle->dma_dev, dev, strlen(dev)+1); - // open DMA driver device handle->dma_fd = open(handle->dma_dev, O_RDWR); if (handle->dma_fd < 1) { printf("Unable to open device file"); return -1; } - // TODO: check for max. memory size.. handle->dma_size=RP_SGMNT_CNT*RP_SGMNT_SIZE; rp_SetSgmntC(handle,RP_SGMNT_CNT); rp_SetSgmntS(handle,RP_SGMNT_SIZE); - return RP_OK; } -int rp_DmaCtrl(rp_handle_uio_t *handle, RP_DMA_CTRL ctrl) -{ +int rp_DmaCtrl(rp_handle_uio_t *handle, RP_DMA_CTRL ctrl) { switch(ctrl){ case RP_DMA_CYCLIC: ioctl(handle->dma_fd, CYCLIC_RX, 0); @@ -56,47 +51,17 @@ int rp_DmaCtrl(rp_handle_uio_t *handle, RP_DMA_CTRL ctrl) return RP_OK; } -int rp_SetSgmntC(rp_handle_uio_t *handle, unsigned long no) -{ +int rp_SetSgmntC(rp_handle_uio_t *handle, unsigned long no) { ioctl(handle->dma_fd, SET_RX_SGMNT_CNT, no); return RP_OK; } -int rp_SetSgmntS(rp_handle_uio_t *handle, unsigned long no) -{ +int rp_SetSgmntS(rp_handle_uio_t *handle, unsigned long no) { ioctl(handle->dma_fd, SET_RX_SGMNT_SIZE, no); return RP_OK; } -int rp_DmaMemDump(rp_handle_uio_t *handle) -{ - unsigned char* map=NULL; - // allocate data buffer memory - map = (unsigned char *) mmap(NULL, handle->dma_size, PROT_READ | PROT_WRITE, MAP_SHARED, handle->dma_fd, 0); - if (map==NULL) { - printf("Failed to mmap\n"); - if (handle->dma_fd) { - close(handle->dma_fd); - } - return -1; - } - - // printout data - for (int i=0; idma_size; i++) { - if ((i%64)==0 ) printf("@%08x: ", i); - printf("%02x",(char)map[i]); - if ((i%64)==63) printf("\n"); - } - - if(munmap (map, handle->dma_size)==-1){ - printf("Failed to munmap\n"); - return -1; - } - return RP_OK; -} - -int rp_DmaRead(rp_handle_uio_t *handle) -{ +int rp_DmaRead(rp_handle_uio_t *handle) { int s = read(handle->dma_fd, NULL, 1); if (s<0) { printf("read error\n"); @@ -105,15 +70,12 @@ int rp_DmaRead(rp_handle_uio_t *handle) return RP_OK; } -int rp_DmaClose(rp_handle_uio_t *handle) -{ +int rp_DmaClose(rp_handle_uio_t *handle) { if(handle->dma_fd){ if(close(handle->dma_fd)==-1){ return -1; } } - free(handle->dma_dev); - return RP_OK; } diff --git a/api2/src/rp_dma.h b/api2/src/rp_dma.h index 75e2f38eb..dcf4df5fa 100644 --- a/api2/src/rp_dma.h +++ b/api2/src/rp_dma.h @@ -15,25 +15,20 @@ #ifndef _RP_DMA_H_ #define _RP_DMA_H_ -#include "rp_dma.h" - #include #include -typedef enum -{ +typedef enum { RP_DMA_SINGLE, RP_DMA_CYCLIC, RP_DMA_STOP_RX } RP_DMA_CTRL; - int rp_DmaOpen(const char *dev, rp_handle_uio_t *handle); int rp_DmaCtrl(rp_handle_uio_t *handle, RP_DMA_CTRL ctrl); int rp_SetSgmntC(rp_handle_uio_t *handle, unsigned long no); int rp_SetSgmntS(rp_handle_uio_t *handle, unsigned long no); int rp_DmaRead(rp_handle_uio_t *handle); -int rp_DmaMemDump(rp_handle_uio_t *handle); int rp_DmaClose(rp_handle_uio_t *handle); #endif // _RP_DMA_H_ diff --git a/api2/test/test_dma.c b/api2/test/test_dma.c deleted file mode 100644 index 51373f0a1..000000000 --- a/api2/test/test_dma.c +++ /dev/null @@ -1,129 +0,0 @@ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "la_acq.h" -#include "rp_api.h" - -int suite_la_acq_init(void) -{ - if(rp_OpenUnit()!=RP_OK){ - return -1; - } - return 0; -} - -int suite_la_acq_cleanup(void) -{ - if(rp_CloseUnit()!=RP_OK){ - return -1; - } - return 0; -} - -void rpReadyCallback(RP_STATUS status, void * pParameter) -{ - printf("\r\nACQ_CALLBACK"); -} - -pthread_t tid; - -void* trigGen(void *arg) -{ - sleep(2); - rp_DigSigGenSoftwareControl(1); - return NULL; -} - -int main () { - pthread_t tid; - RP_STATUS s; - RP_DIGITAL_CHANNEL_DIRECTIONS dir[1]; - dir[0].channel=RP_DIGITAL_CHANNEL_7; - dir[0].direction=RP_DIGITAL_DIRECTION_RISING; - - if(rp_OpenUnit()!=RP_OK){ - return -1; - } - - for (int n=0; n<1; n++) { - rp_DigSigGenOuput(true); - double sample_rate=125e6; - rp_SetDigSigGenBuiltIn(RP_DIG_SIGGEN_PAT_UP_COUNT_8BIT_SEQ_256,&sample_rate,0,0,RP_TRG_DGEN_SWE_MASK); - //printf("sample rate %lf",sample_rate); - - // start trigger a bit later in a new thread - int err; - err = pthread_create(&tid, NULL, &trigGen, NULL); - if (err != 0) - printf("\ncan't create thread :[%s]", strerror(err)); - else - printf("\n Thread created successfully\n"); - - printf("\r\nTriggers"); - s=rp_SetTriggerDigitalPortProperties(dir,1); - if(s!=RP_API_OK){ - printf("Failed to set trigger properties."); - } - - // enable RLE - rp_EnableDigitalPortDataRLE(0); - - printf("\r\nRunBlock"); - double timeIndisposedMs; - uint32_t pre=100; - uint32_t post=8000; - s=rp_RunBlock(pre,post,0,&timeIndisposedMs,&rpReadyCallback,NULL); - if(s!=RP_API_OK){ - printf("Failed to acquire data."); - } - - uint32_t samples=pre+post; - - int16_t * buf = malloc(samples * sizeof(int16_t)); - if (NULL == buf) { - printf("malloc failed"); - } - - // set data buffer to which data will be read from memory space - rp_SetDataBuffer(RP_CH_DIN,buf,samples,RP_RATIO_MODE_NONE); - - // get data - rp_GetValues(0,&samples,1,RP_RATIO_MODE_NONE,NULL); - - // verify data - int first=buf[0]; - for(int i=0;i%04x",buf[pre]); - printf("\n\r %04x",buf[pre+1]); - - free(buf); - } - - if(rp_CloseUnit()!=RP_OK){ - return -1; - } - - return (0); -} - diff --git a/api2/test/test_gen.c b/api2/test/test_gen.c deleted file mode 100644 index b119a76a4..000000000 --- a/api2/test/test_gen.c +++ /dev/null @@ -1,44 +0,0 @@ -#include -#include -#include - -#include "redpitaya/rp2.h" -#include "generate.h" -#include "common.h" - -int main (int argc, char **argv) { - rp_handle_uio_t handle; - int status; - - // Initialization of API - if (rp_GenOpen("/dev/uio/asg0", &handle) != RP_OK) { - fprintf(stderr, "Red Pitaya API init failed!\n"); - return EXIT_FAILURE; - } - - int unsigned length = 1<<13; - double frequency = 1000; - double phase = 180; - - rp_GenSetWaveformUpCountSeq(&handle, length); - - status = rp_GenSetFreqPhase(&handle, frequency, phase); - if (status != RP_OK) { - fprintf(stderr, "Red Pitaya API access failed!\n"); - } - status = rp_GenGetFreqPhase(&handle, &frequency, &phase); - if (status != RP_OK) { - fprintf(stderr, "Red Pitaya API access failed!\n"); - } - - rp_GenGlobalTrigSet(&handle, RP_TRG_GEN1_SWE_MASK); - rp_GenTrigger(&handle); - - usleep(5*1000*1000); - fprintf(stderr, "frequency = %f, phase = %f\n", frequency, phase); - - // Releasing resources - rp_GenClose(&handle); - - return EXIT_SUCCESS; -} diff --git a/api2/test/test_id.c b/api2/test/test_id.c deleted file mode 100644 index 716bf07be..000000000 --- a/api2/test/test_id.c +++ /dev/null @@ -1,41 +0,0 @@ -#include -#include -#include - -#include "redpitaya/rp2.h" -#include "id.h" - -int main (int argc, char **argv) { - rp_handle_uio_t handle; - - // Initialization of API - if (rp_IdOpen("/dev/uio/id", &handle) != RP_OK) { - fprintf(stderr, "Red Pitaya API init failed!\n"); - return EXIT_FAILURE; - } - - uint32_t id; - rp_IdGetID (&handle, &id); - printf("ID = 0x%08x\n", id); - - uint32_t efuse; - rp_IdGetEFUSE (&handle, &efuse); - printf("EFUSE = 0x%08x\n", efuse); - - uint64_t dna; - rp_IdGetDNA (&handle, &dna); - printf("DNA = 0x%" PRIx64 "\n", dna); - - uint32_t gith[5]; - rp_IdGetGITH (&handle, gith); - printf("GITH = "); - for (int i=0; i<5; i++) { - printf("%08x", gith[i]); - } - printf("\n"); - - // Releasing resources - rp_IdClose(&handle); - - return EXIT_SUCCESS; -} diff --git a/api2/test/test_lg_burst.c b/api2/test/test_lg_burst.c deleted file mode 100644 index e03ab5c83..000000000 --- a/api2/test/test_lg_burst.c +++ /dev/null @@ -1,45 +0,0 @@ -#include -#include -#include - -#include "redpitaya/rp2.h" -#include "generate.h" - -int main (int argc, char **argv) { - rp_handle_uio_t handle; - int status; - - // Initialization of API - if (rp_GenOpen("/dev/uio/lg", &handle) != RP_OK) { - fprintf(stderr, "Red Pitaya API init failed!\n"); - return EXIT_FAILURE; - } - - int unsigned length = 256; - uint32_t stp = 0x00010000; - uint32_t off = 0x00000000; - - rp_GenSetWaveformUpCountSeq(&handle, length); - - status = rp_GenSetStepOffset(&handle, stp, off); - if (status != RP_OK) { - fprintf(stderr, "Error: failed to write step and offset!\n"); - return EXIT_FAILURE; - } - - rp_GenOutputEnable(&handle, 0xffff); - - rp_GenSetMode (&handle, RP_GEN_MODE_BURST); - rp_GenSetBurstModeDataLen (&handle, length); - rp_GenSetBurstModePeriodLen (&handle, length); - - rp_GenSetBurstModeRepetitions (&handle, RP_GEN_REP_INF); - - rp_GenGlobalTrigSet(&handle, RP_TRG_DGEN_SWE_MASK); - rp_GenTrigger(&handle); - - // Releasing resources - rp_GenClose(&handle); - - return EXIT_SUCCESS; -} diff --git a/api2/test/test_lg_periodic.c b/api2/test/test_lg_periodic.c deleted file mode 100644 index 842362174..000000000 --- a/api2/test/test_lg_periodic.c +++ /dev/null @@ -1,45 +0,0 @@ -#include -#include -#include - -#include "redpitaya/rp2.h" -#include "generate.h" - -int main (int argc, char **argv) { - rp_handle_uio_t handle; - int status; - - // Initialization of API - if (rp_GenOpen("/dev/uio/lg", &handle) != RP_OK) { - fprintf(stderr, "Red Pitaya API init failed!\n"); - return EXIT_FAILURE; - } - - int unsigned length = 256; - double frequency = 1000; - double phase = 180; - - rp_GenSetWaveformUpCountSeq(&handle, length); - - status = rp_GenSetFreqPhase(&handle, frequency, phase); - if (status != RP_OK) { - fprintf(stderr, "Red Pitaya API access failed!\n"); - } - status = rp_GenGetFreqPhase(&handle, &frequency, &phase); - if (status != RP_OK) { - fprintf(stderr, "Red Pitaya API access failed!\n"); - } - - rp_GenOutputEnable(&handle, 0xffff); - - rp_GenGlobalTrigSet(&handle, RP_TRG_DGEN_SWE_MASK); - rp_GenTrigger(&handle); - - usleep(5*1000*1000); - fprintf(stderr, "frequency = %f, phase = %f\n", frequency, phase); - - // Releasing resources - rp_GenClose(&handle); - - return EXIT_SUCCESS; -} diff --git a/api2/utests/ut_la_acq.c b/api2/utests/ut_la_acq.c deleted file mode 100644 index 90747cc64..000000000 --- a/api2/utests/ut_la_acq.c +++ /dev/null @@ -1,257 +0,0 @@ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "ut_main.h" -#include "la_acq.h" -#include "rp_api.h" - -int suite_la_acq_init(void) -{ - if(rp_OpenUnit()!=RP_OK){ - return -1; - } - return 0; -} - -int suite_la_acq_cleanup(void) -{ - if(rp_CloseUnit()!=RP_OK){ - return -1; - } - return 0; -} - -void rpReadyCallback(RP_STATUS status, void * pParameter) -{ - printf("\r\nACQ_CALLBACK"); -} - -pthread_t tid; -pthread_t tid2; -pthread_t tid3; - -void* trigGen(void *arg) -{ - sleep(1); - rp_DigSigGenSoftwareControl(1); - return NULL; -} - -void* trigAcq(void *arg) -{ - printf("\r\nTrigAcqThreadStarted"); - sleep(2); - printf("\r\nSW trigger"); - if(rp_SoftwareTrigger()!=RP_API_OK){ - printf("\r\nCannot trigger acq."); - rp_Stop(); - } - return NULL; -} - -void* stopAcq(void *arg) -{ - printf("\r\nStopAcqThreadStarted"); - sleep(2); - printf("\r\nStopAcq"); - rp_Stop(); - return NULL; -} - - - -void la_acq_trig_test(void) -{ - - // for(int i=0; i<1; i++){ - - //sleep(1); - - RP_STATUS s; - RP_DIGITAL_CHANNEL_DIRECTIONS dir[1]; - dir[0].channel=RP_DIGITAL_CHANNEL_7; - dir[0].direction=RP_DIGITAL_DIRECTION_RISING; - - rp_DigSigGenOuput(true); - double sample_rate=125e6; - rp_SetDigSigGenBuiltIn(RP_DIG_SIGGEN_PAT_UP_COUNT_8BIT_SEQ_256,&sample_rate,0,0,RP_TRG_DGEN_SWE_MASK); - //printf("sample rate %lf",sample_rate); - - printf("\r\nTriggers"); - s=rp_SetTriggerDigitalPortProperties(dir,1); - if(s!=RP_API_OK){ - CU_FAIL("Failed to set trigger properties."); - } - - // enable RLE - rp_EnableDigitalPortDataRLE(1); - - - // start gen a bit later in a new thread - /* - if(pthread_create(&tid, NULL, &trigGen, NULL)!=0){ - CU_FAIL("can't create thread."); - } - */ - - // software trig. acq. - /* - if(pthread_create(&tid2, NULL, &trigAcq, NULL)!=0){ - CU_FAIL("can't create thread."); - } - */ - - // stop acq. - if(pthread_create(&tid3, NULL, &stopAcq, NULL)!=0){ - CU_FAIL("can't create thread."); - } - - printf("\r\nRunBlock"); - double timeIndisposedMs; - uint32_t pre=100; - uint32_t post=100; - s=rp_RunBlock(pre,post,8,&timeIndisposedMs,&rpReadyCallback,NULL); - if(s!=RP_API_OK){ - CU_FAIL("Failed to acquire data."); - } - - uint32_t samples=pre+post; - - int16_t * buf = malloc(samples * sizeof(int16_t)); - if (NULL == buf) { - CU_FAIL("malloc failed"); - } - - // set data buffer to which data will be read from memory space - rp_SetDataBuffer(RP_CH_DIN,buf,samples,RP_RATIO_MODE_NONE); - - // get data - rp_GetValues(0,&samples,1,RP_RATIO_MODE_NONE,NULL); - - - // verify data - int first=buf[0]; - for(int i=0;i%04x",buf[trig_pos]); - printf("\n\r %04x",buf[trig_pos+1]); - - free(buf); - //} -} - -void reg_rw_test(void){ - -/* - rp_handle_uio_t handle; - - - - // once device is opened, acq. should be stopped - bool status; - rp_LaAcqAcqIsStopped(&handle, &status); - CU_ASSERT_TRUE(status); - - // test register access - - // rp_la_cfg_regset_t - rp_la_cfg_regset_t cfgw, cfgr; - cfgw.acq=RP_LA_ACQ_CFG_AUTO_MASK|RP_LA_ACQ_CFG_CONT_MASK; - cfgw.pre=UINT32_MAX; - cfgw.pst=UINT32_MAX; - rp_LaAcqSetCntConfig(&handle,cfgw); - rp_LaAcqGetCntConfig(&handle,&cfgr); - CU_ASSERT_FALSE(memcmp((char*)&cfgw, (char*)&cfgr, sizeof(rp_la_cfg_regset_t))); - cfgw.acq=RP_LA_ACQ_CFG_AUTO_MASK; - cfgw.pre=56456; - cfgw.pst=45677; - rp_LaAcqSetCntConfig(&handle,cfgw); - rp_LaAcqGetCntConfig(&handle,&cfgr); - CU_ASSERT_FALSE(memcmp((char*)&cfgw, (char*)&cfgr, sizeof(rp_la_cfg_regset_t))); - memset(&cfgw, 0, sizeof(rp_la_cfg_regset_t)); - rp_LaAcqSetCntConfig(&handle,cfgw); - rp_LaAcqGetCntConfig(&handle,&cfgr); - CU_ASSERT_FALSE(memcmp((char*)&cfgw, (char*)&cfgr, sizeof(rp_la_cfg_regset_t))); - - // rp_la_trg_regset_t trg - rp_la_trg_regset_t trgw, trgr; - trgw.cmp_msk=UINT32_MAX; - trgw.cmp_val=UINT32_MAX; - trgw.edg_pos=UINT32_MAX; - trgw.edg_neg=UINT32_MAX; - rp_LaAcqSetTrigSettings(&handle,trgw); - rp_LaAcqGetTrigSettings(&handle,&trgr); - CU_ASSERT_FALSE(memcmp((char*)&trgw, (char*)&trgr, sizeof(rp_la_trg_regset_t))); - trgw.cmp_msk=2355; - trgw.cmp_val=6345; - trgw.edg_pos=7567; - trgw.edg_neg=8567; - rp_LaAcqSetTrigSettings(&handle,trgw); - rp_LaAcqGetTrigSettings(&handle,&trgr); - CU_ASSERT_FALSE(memcmp((char*)&trgw, (char*)&trgr, sizeof(rp_la_trg_regset_t))); - - rp_LaAcqSetTrigSettings(&handle,trgw); - rp_LaAcqGetTrigSettings(&handle,&trgr); - CU_ASSERT_FALSE(memcmp((char*)&trgw, (char*)&trgr, sizeof(rp_la_trg_regset_t))); - - // rp_la_decimation_regset_t dec - rp_la_decimation_regset_t decw, decr; - decw.avg=UINT32_MAX; - decw.dec=UINT32_MAX; - decw.shr=UINT32_MAX; - rp_LaAcqSetDecimation(&handle,decw); - rp_LaAcqGetDecimation(&handle,&decr); - CU_ASSERT_FALSE(memcmp((char*)&decw, (char*)&decr, sizeof(rp_la_decimation_regset_t))); - decw.avg=23423; - decw.dec=34534; - decw.shr=63456; - rp_LaAcqSetDecimation(&handle,decw); - rp_LaAcqGetDecimation(&handle,&decr); - CU_ASSERT_FALSE(memcmp((char*)&decw, (char*)&decr, sizeof(rp_la_decimation_regset_t))); - memset(&decw, 0, sizeof(rp_la_decimation_regset_t)); - rp_LaAcqSetDecimation(&handle,decw); - rp_LaAcqGetDecimation(&handle,&decr); - CU_ASSERT_FALSE(memcmp((char*)&decw, (char*)&decr, sizeof(rp_la_decimation_regset_t))); - - // test control bits - // TODO: - rp_LaAcqReset(&handle); - rp_LaAcqRunAcq(&handle); - rp_LaAcqStopAcq(&handle); - rp_LaAcqTriggerAcq(&handle); - - rp_LaAcqFpgaRegDump(&handle); - - // rp_data_ptrs_regset_t dpt - // TODO: - - // Close log. anal. device - if(rp_LaAcqClose(&handle) != RP_OK){ - CU_FAIL_FATAL("Could not properly close the device."); - } - */ -} - diff --git a/api2/utests/ut_sig_gen.c b/api2/utests/ut_sig_gen.c deleted file mode 100644 index 53da79d0e..000000000 --- a/api2/utests/ut_sig_gen.c +++ /dev/null @@ -1,41 +0,0 @@ - -#include -#include -#include - -#include "CUnit/Basic.h" -#include "CUnit/Console.h" -#include "CUnit/Automated.h" -#include "CUnit/CUCurses.h" - -#include "ut_main.h" -#include "generate.h" -#include "rp_api.h" - - - -int suite_sig_gen_init(void) -{ - if(rp_OpenUnit()!=RP_OK){ - return -1; - } - return 0; -} - -int suite_sig_gen_cleanup(void) -{ - if(rp_CloseUnit()!=RP_OK){ - return -1; - } - return 0; -} - -void sig_gen_test(void) -{ - rp_DigSigGenOuput(true); - double sample_rate=125e6; - rp_SetDigSigGenBuiltIn(RP_DIG_SIGGEN_PAT_UP_COUNT_8BIT_SEQ_256,&sample_rate,10,0,RP_TRG_DGEN_SWE_MASK); - //printf("sample rate %lf",sample_rate); - rp_DigSigGenSoftwareControl(1); - sleep(5); -} diff --git a/doc/appsFeatures/apps-featured/oscSigGen/osc.rst b/doc/appsFeatures/apps-featured/oscSigGen/osc.rst index 56c3033f8..e5071ef43 100644 --- a/doc/appsFeatures/apps-featured/oscSigGen/osc.rst +++ b/doc/appsFeatures/apps-featured/oscSigGen/osc.rst @@ -30,7 +30,7 @@ Apart from the graph there are five areas in which the surface is divided: Features -******* +******** Oscilloscope & signal generator main features are listed below: - Run/stop and auto set functionality diff --git a/doc/appsFeatures/examples/genRF-exm1.rst b/doc/appsFeatures/examples/genRF-exm1.rst index 37f732eb0..38ac02c8a 100644 --- a/doc/appsFeatures/examples/genRF-exm1.rst +++ b/doc/appsFeatures/examples/genRF-exm1.rst @@ -51,6 +51,8 @@ MATLAB editor, save project and press run. Code - C ******** +.. code-block:: c + /* Red Pitaya C API example Generating continuous signal * This application generates a specific signal */ diff --git a/doc/appsFeatures/marketplace/marketplace.rst b/doc/appsFeatures/marketplace/marketplace.rst index 04c62a883..b6f9b2412 100644 --- a/doc/appsFeatures/marketplace/marketplace.rst +++ b/doc/appsFeatures/marketplace/marketplace.rst @@ -66,7 +66,7 @@ one of the following types of SDR software such as HDSDR, SDR#, PowerSDR mRX PS, You can find more about the SDR on the Red Pitaya STEM at the links below: - http://redpitaya.com/red-pitaya-as-sdr-transceiver/ + http://blog.redpitaya.com/red-pitaya-and-software-defined-radio/ http://pavel-demin.github.io/red-pitaya-notes/ diff --git a/doc/appsFeatures/remoteControl/remoteControl.rst b/doc/appsFeatures/remoteControl/remoteControl.rst index b951e7e84..39045fc5d 100644 --- a/doc/appsFeatures/remoteControl/remoteControl.rst +++ b/doc/appsFeatures/remoteControl/remoteControl.rst @@ -86,7 +86,7 @@ To install them do: .. code-block:: shell-session - $ sudo pip3 install pyvisa pyvisa-py + $ sudo pip3 install pyvisa pyvisa-py #. Open the :ref:`blink ` tutorial and copy the code to your favorite text editor #. Save the file as ``blink.py`` to your working folder → for example ``examples_py`` diff --git a/doc/conf.py b/doc/conf.py index 39a40d85a..c5e62847c 100644 --- a/doc/conf.py +++ b/doc/conf.py @@ -56,7 +56,7 @@ # General information about the project. project = u'Red Pitaya STEMlab' title = u'Red Pitaya STEMlab Documentation' -copyright = u'2016, Red Pitaya d.d.' +copyright = u'2017, Red Pitaya d.d.' author = u'Red Pitaya' # The version info for the project you're documenting, acts as replacement for diff --git a/doc/developerGuide/125-10/vs.rst b/doc/developerGuide/125-10/vs.rst index 87c4f79d1..264143ac6 100644 --- a/doc/developerGuide/125-10/vs.rst +++ b/doc/developerGuide/125-10/vs.rst @@ -52,49 +52,50 @@ input / output channels and is perfect for universities,students and makers. | Synchronisation | / | Daisy chain connector (up to 500 Mbps)| +-----------------+----------------------+---------------------------------------+ -+-----------------------------------+-------------------+--------------------+ -| RF inputs | -+-----------------------------------+-------------------+--------------------+ -| | STEMLAB 125-10 | STEMLAB 125-14 | -+-----------------------------------+-------------------+--------------------+ -| RF input channels | 2 | 2 | -+-----------------------------------+-------------------+--------------------+ -| Sample rate | 125 MS/s | 125 MS/s | -+-----------------------------------+-------------------+--------------------+ -| ADC resolution | 10 bit | 14 bit | -+-----------------------------------+-------------------+--------------------+ -| Input impedance | 1MOhm/10pF | 1MOhm/10pF | -+-----------------------------------+-------------------+--------------------+ -| Full scale voltage range | ±20 V | ±20 V | -+-----------------------------------+-------------------+--------------------+ -| Absolute max. Input voltage range | 30V | 30V | -+-----------------------------------+-------------------+--------------------+ -| Input ESD protection | Yes | Yes | -+-----------------------------------+-------------------+--------------------+ -| Overload protection | Protection diodes | Protection diodes | -+-----------------------------------+-------------------+--------------------+ ++-----------------------------------+------------------------+------------------------+ +| RF inputs | ++-----------------------------------+------------------------+------------------------+ +| | STEMLAB 125-10 | STEMLAB 125-14 | ++-----------------------------------+------------------------+------------------------+ +| RF input channels | 2 | 2 | ++-----------------------------------+------------------------+------------------------+ +| Sample rate | 125 MS/s | 125 MS/s | ++-----------------------------------+------------------------+------------------------+ +| ADC resolution | 10 bit | 14 bit | ++-----------------------------------+------------------------+------------------------+ +| Input impedance | 1MOhm/10pF | 1MOhm/10pF | ++-----------------------------------+------------------------+------------------------+ +| Full scale voltage range | ±1V (LV) and ±20V (HV) | ±1V (LV) and ±20V (HV) | ++-----------------------------------+------------------------+------------------------+ +| Absolute max. Input voltage range | 30V | 30V | ++-----------------------------------+------------------------+------------------------+ +| Input ESD protection | Yes | Yes | ++-----------------------------------+------------------------+------------------------+ +| Overload protection | Protection diodes | Protection diodes | ++-----------------------------------+------------------------+------------------------+ - +-------------------------+----------------+----------------+ - | RF outputs | - +-------------------------+----------------+----------------+ - | | STEMLAB 125-10 | STEMLAB 125-14 | - +-------------------------+----------------+----------------+ - | RF output channels | 2 | 2 | - +-------------------------+----------------+----------------+ - | Sample rate | 125 MS/s | 125 MS/s | - +-------------------------+----------------+----------------+ - | DAC resolution | 10 bit | 14 bit | - +-------------------------+----------------+----------------+ - | Load impedance | 50 Ohm | 50 Ohm | - +-------------------------+----------------+----------------+ - | Voltage range | ±1V | ±1V | - +-------------------------+----------------+----------------+ - | Ouput slew rate | 200V/us | 200V/us | - +-------------------------+----------------+----------------+ - | Short circut protection | Yes | Yes | - +-------------------------+----------------+----------------+ - | Connector type | SMA | SMA | - +-------------------------+----------------+----------------+ + ++-------------------------+----------------+----------------+ +| RF outputs | ++-------------------------+----------------+----------------+ +| | STEMLAB 125-10 | STEMLAB 125-14 | ++-------------------------+----------------+----------------+ +| RF output channels | 2 | 2 | ++-------------------------+----------------+----------------+ +| Sample rate | 125 MS/s | 125 MS/s | ++-------------------------+----------------+----------------+ +| DAC resolution | 10 bit | 14 bit | ++-------------------------+----------------+----------------+ +| Load impedance | 50 Ohm | 50 Ohm | ++-------------------------+----------------+----------------+ +| Voltage range | ±1V | ±1V | ++-------------------------+----------------+----------------+ +| Ouput slew rate | 200V/us | 200V/us | ++-------------------------+----------------+----------------+ +| Short circut protection | Yes | Yes | ++-------------------------+----------------+----------------+ +| Connector type | SMA | SMA | ++-------------------------+----------------+----------------+ +------------------------------+-------------------+----------------+ | Extension connector | diff --git a/doc/developerGuide/ecosystem/ecosystem.rst b/doc/developerGuide/ecosystem/ecosystem.rst index 490102b92..647fb3cdd 100644 --- a/doc/developerGuide/ecosystem/ecosystem.rst +++ b/doc/developerGuide/ecosystem/ecosystem.rst @@ -1,9 +1,35 @@ -.. ecosystem +.. _ecosystem: ############### Ecosystem Guide ############### +Go to redpitaya-public (git) directory. + +.. note:: + + | It is recommended that you set ``$LC_ALL`` variable. + | To check whether it is set, type the following command into a terminal: + + .. code-block:: shell-session + + echo $LC_ALL + + If it returns an empty line, set it up by typing the following command into the terminal: + + .. code-block:: shell-session + + export LC_ALL=C + + This line can also be added to the end of .bashrc and will automatically set the ``$LC_ALL`` variable each time the + terminal is started. + +.. note:: + + It is not possible to build an ecosystem on an encrypted home directory, since schroot can not access that + directory. We recommend that you make a separate directory in home directory that is not encrypted e.g. + ``/home/ecosystem_build`` + ===================================== Red Pitaya ecosystem and applications ===================================== @@ -67,7 +93,7 @@ You will need the following to build the Red Pitaya components: # QEMU sudo apt-get install qemu qemu-user qemu-user-static # 32 bit libraries - sudo apt-get install lib32z1 lib32ncurses5 lib32bz2-1.0 lib32stdc++6 + sudo apt-get install lib32z1 lib32ncurses5 libbz2-1.0:i386 lib32stdc++6 2. Meson Build system (depends on Python 3) is used for some new code. It is not required but can be used during development on x86 PC. @@ -79,7 +105,7 @@ You will need the following to build the Red Pitaya components: sudo pip3 install meson sudo apt-get install ninja-build -3. Xilinx `Vivado 2017.1 `_ FPGA development tools. +3. Xilinx `Vivado 2017.2 `_ FPGA development tools. The SDK (bare metal toolchain) must also be installed, be careful during the install process to select it. Preferably use the default install location. @@ -125,9 +151,9 @@ Correct file permissions are required for ``schroot`` to work properly. .. code-block:: shell-session - wget http://downloads.redpitaya.com/downloads/redpitaya_ubuntu_15-13-08_13-jul-2017.tar.gz - sudo chown root:root redpitaya_ubuntu_15-13-08_13-jul-2017.tar.gz - sudo chmod 664 redpitaya_ubuntu_15-13-08_13-jul-2017.tar.gz + wget http://downloads.redpitaya.com/downloads/redpitaya_ubuntu_13-14-23_25-sep-2017.tar.gz + sudo chown root:root redpitaya_ubuntu_13-14-23_25-sep-2017.tar.gz + sudo chmod 664 redpitaya_ubuntu_13-14-23_25-sep-2017.tar.gz Create schroot configuration file ``/etc/schroot/chroot.d/red-pitaya-ubuntu.conf``. Replace the tarball path stub with the absolute path of the previously downloaded image. @@ -304,7 +330,7 @@ You can install it on Red Pitaya by copying it there: SCPI server ~~~~~~~~~~~ -Scpi server README can be found `here `_. +Scpi server README can be found :download:`here <../../../scpi-server/README.md>`. To compile the server run: @@ -323,4 +349,4 @@ You can install it on Red Pitaya by copying it there: Free applications ~~~~~~~~~~~~~~~~~ -To build free applications, follow the instructions given at ``_ file. +To build free applications, follow the instructions given :download:`here <../../../apps-free/README.md>`. diff --git a/doc/developerGuide/gpio/gpio.rst b/doc/developerGuide/gpio/gpio.rst new file mode 100644 index 000000000..08e0fa69d --- /dev/null +++ b/doc/developerGuide/gpio/gpio.rst @@ -0,0 +1,124 @@ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +General purpose input output +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +===== +GPIOs +===== + +This document introduses handling of GPIO signals that are conected to Zynq-7000 PS EMIO block +and is accesible as general purpose input / output pins on Extension conector E1 with Linux gpio subsystem userspace interfaces. + +There are two interfaces legacy sysfs interface and new character device based one. + +==== +PINS +==== + +Pins connected to the PL block require FPGA code to function. If the pin signals are wired directly (in the FPGA sources) from PS based EMIO signals to the FPGA pads, +then they can be managed using Linux drivers intended for the PS block. This is currently done with two fpga projects: classic and mercury. + +Apropriate fpga bitstream can be applied using bash command. + +.. code-block:: shell-session + + cat /opt/redpitaya/fpga/classic/fpga.bit > /dev/xdevcfg + + +There are 54+64=118 GPIO provided by ZYNQ PS, MIO provides 54 GPIO, +and EMIO provide additional 64 GPIO and only 16 out of those are accesible on board. +On Extension connector E1; pins from DIO0_N to DIO7_N and DIO0_P to DIO7_P. + +The next formula is used to calculate the ``gpio_base`` index. + +.. code-block:: none + + base_gpio = ARCH_NR_GPIOS - ZYNQ_GPIO_NR_GPIOS = 1024 - 118 = 906 + +Values for the used macros can be found in the kernel sources. + +.. code-block:: shell-session + + $ grep ZYNQ_GPIO_NR_GPIOS drivers/gpio/gpio-zynq.c + #define ZYNQ_GPIO_NR_GPIOS 118 + $ grep -r CONFIG_ARCH_NR_GPIO tmp/linux-xlnx-xilinx-v2017.2 + tmp/linux-xlnx-xilinx-v2017.2/.config:CONFIG_ARCH_NR_GPIO=1024 + +Another way to find the `gpio_base` index is to check the given name inside `sysfs`. + +.. code-block:: shell-session + + # find /sys/class/gpio/ -name gpiochip* + /sys/class/gpio/gpiochip906 + +GPIOs are accessible at the ``sysfs`` index. + +The default pin assignment for GPIO is described in the next table. + ++--------+------------+--------------------+------------------+------------------------------+-------------------------------------------+ +| FPGA | connector | GPIO | MIO/EMIO index | ``sysfs`` index | comments, LED color, dedicated meaning | ++========+============+====================+==================+==============================+===========================================+ +| | | ``exp_p_io [7:0]`` | ``EMIO[15: 8]`` | ``906+54+[15: 8]=[975:968]`` | DIO7_P : DIO0_P | ++--------+------------+--------------------+------------------+------------------------------+-------------------------------------------+ +| | | ``exp_n_io [7:0]`` | ``EMIO[23:16]`` | ``906+54+[23:16]=[983:976]`` | DIO7_N : DIO0_N | ++--------+------------+--------------------+------------------+------------------------------+-------------------------------------------+ + + + +==================== +Linux access to GPIO +==================== + +************ +SYSFS access +************ + +This document is used as reference: +`Linux+GPIO+Driver `_ + + + +Bash example for writing to and reading from gpio value for pins from 968(DIO0_P) to 983(DIO7_N). + + +.. code-block:: shell-session + + #export pin 968 + $ echo "968" > /sys/class/gpio/export + #set direction to output + $ echo "out" > /sys/class/gpio/gpio968/direction + #set pin to LOW + $ echo "0" > /sys/class/gpio/gpio968/value + #set pin to HIGH + $ echo "1" > /sys/class/gpio/gpio968/value + #set pin direction to input + $ echo "in" > /sys/class/gpio/gpio968/direction + #output pin value + $ cat /sys/class/gpio/gpio968/value + #when done with pin you should unexport it with + $ echo 968 > /sys/class/gpio/unexport + + + +SYSFS GPIO C example is available at github: https://github.com/RedPitaya/RedPitaya/tree/master/Examples/gpio_sysfs + + +*********************** +Character device access +*********************** + +Character device usersace access to gpio kernel subsystem is confirmed working on kernels newer and including 4.8. + +References: + +http://elinux.org/images/9/9b/GPIO_for_Engineers_and_Makers.pdf +https://www.youtube.com/watch?v=lQRCDl0tFiQ + +The Linux kernel contains GPIO utilities in its ``tools`` directory. + +https://github.com/torvalds/linux/tree/master/tools/gpio + +We isolated the sources and created a library from ``gpio-utils.c`` and +executables from other source files. + +https://github.com/RedPitaya/gpio-utils diff --git a/doc/developerGuide/os/debian.rst b/doc/developerGuide/os/debian.rst index a4c348f20..8106131d5 100644 --- a/doc/developerGuide/os/debian.rst +++ b/doc/developerGuide/os/debian.rst @@ -1,10 +1,102 @@ -.. os +.. _os: ############# Red Pitaya OS ############# -For instructions on how to build the ecosystem, go to :ref:`ecosystem `. +******** +Overview +******** + +Executable scripts from ``SW/debian`` directory: + ++---------------------+------------------------------------------------------------------------------+ +| script | description | ++=====================+==============================================================================+ +| ``image.sh`` | full SD card image build procedure (creates and formats partitions) | ++---------------------+------------------------------------------------------------------------------+ +| ``image-update.sh`` | update existing SD card image with new ``ecosystem_*.zip`` | ++---------------------+------------------------------------------------------------------------------+ +| ``image-fsck.sh`` | run FSCK on SD card image partitions (for images created from used DS cards) | ++---------------------+------------------------------------------------------------------------------+ +| ``image-clean.sh`` | deprecated | ++---------------------+------------------------------------------------------------------------------+ + +Scripts to be used in a ``chroot`` environment only: + +.. note:: + + If this scripts are executed on the host OS directly, they can cause serious damage. + ++---------------------+-----------------------------------------------------------------------------------------------------+ +| script | description | ++=====================+=====================================================================================================+ +| ``ubuntu.sh`` | Ubuntu bootstrap, locale, apt configuration, timezone, fake HW clock) | ++---------------------+-----------------------------------------------------------------------------------------------------+ +| ``debian.sh`` | Debian bootstrap (**experimental**, WEB applications are not working) | ++---------------------+-----------------------------------------------------------------------------------------------------+ +| ``tools.sh`` | tools for compiling software | ++---------------------+-----------------------------------------------------------------------------------------------------+ +| ``zynq.sh`` | HW support for ZYNQ chip (U-Boot, I2C, EEPROM, dtc, IIO, NE10?, GPIO, groups with HW access rights) | ++---------------------+-----------------------------------------------------------------------------------------------------+ +| ``network.sh`` | systemd-networkd based wired/wireless network configuration and required tools (hostAP, supplicant) | ++---------------------+-----------------------------------------------------------------------------------------------------+ +| ``redpitaya.sh`` | libraries required by ecosystem applications (boost, jpeg, json), install and enable services | ++---------------------+-----------------------------------------------------------------------------------------------------+ +| ``jupyter.sh`` | Jupyter with NumPy and SciPy | ++---------------------+-----------------------------------------------------------------------------------------------------+ +| ``tft.sh`` | X-server and XFCE | ++---------------------+-----------------------------------------------------------------------------------------------------+ + +The ``overlay`` directory contains configuration files which are individually installed onto the OS by scripts. + +************* +Bootstrapping +************* + +A short list of SD card image contents: + +1. Debian/Ubuntu OS (Ext4 partition): + - base operating system files + - additional operating system applications and libraries + - systemd services + - most network configuration files + - Jupyter work space +2. Ecosystem (Fat32 partition): + + 1. Bare metal: + - ``boot.bin`` file containing FSBL, FPGA bitstream, U-Boot + - Linux kernel image, device tree files + - alternative FPGA bitstreams and corresponding device tree overlays + 2. User space + - Bazaar server (Nginx) and WEB applications + - Red Pitaya API library + - SCPI server + +To build a functional *OS image* the *ecosystem* is required, +since without the ``boot.bin`` and the Linux kernel, the system will not start. +And to build the *ecosystem* the *OS image* is required, +since the user space applications are built inside a ``chroot`` environment +with an emulated ARM CPU. + +Therefore the procedure for the first build is as follows: + +1. Build the OS image without the ecosystem. + This will create a ``redpitaya_OS_*.img`` SD card image, but without the ecosystem and therefore non functional. + It will also create a ``redpitaya_OS_*.tar.gz`` file, to be used in the ``chroot`` environment. +2. Build the ``ecosystem_*.zip`` inside the ``chroot`` environment. +3. Combine ``redpitaya_OS_*.img`` with ``ecosystem_*.zip`` using: + + .. code-block:: shell-session + + OS/debian/image-update.sh redpitaya_OS_*.img ecosystem_*.zip + +After finishing the bootstrapping procedure, either the ecosystem or the OS image can be built as needed. +The more common procedure would be to build a new ecosystem using an existing ``chroot`` environment, +and then replace the ecosystem in an existing SD card image with the new one. +The build procedure for a new SD card OS image can now be done in one step. +If an existing ``ecosystem_*.zip`` file is present in the project root while building the OS image, +it will be integrated and the result will be a fully functional SD card image. ************ Dependencies @@ -18,44 +110,20 @@ The next two packages need to be installed on the host PC: $ sudo apt-get install debootstrap qemu-user-static -***************************** -SD card image build Procedure -***************************** - -Multiple steps are needed to prepare a proper SD card image. - -1. Bootstrap Debian system with network configuration and Red Pitaya specifics. -2. Add Red Pitaya ecosystem ZIP. - ================ Ubuntu bootstrap ================ -.. |image.sh| replace:: ``image.sh`` -.. _image.sh: /OS/debian/image.sh - -.. |image-update.sh| replace:: ``image-update.sh`` -.. _image-update.sh: /OS/debian/image-update.sh - -.. |image-fsck.sh| replace:: ``image-fsck.sh`` -.. _image-fsck.sh: /OS/debian/image-fsck.sh - -.. |ubuntu.sh| replace:: ``ubuntu.sh`` -.. _ubuntu.sh: /OS/debian/ubuntu.sh - -.. |network.sh| replace:: ``network.sh`` -.. _network.sh: /OS/debian/network.sh +The next steps should be executed in the root directory of the Red Pitaya Git repository. -.. |redpitaya.sh| replace:: ``redpitaya.sh`` -.. _redpitaya.sh: /OS/debian/redpitaya.sh - -.. |jupyter.sh| replace:: ``jupyter.sh`` -.. _jupyter.sh: /OS/debian/jupyter.sh +.. code-block:: shell-session -.. |tft.sh| replace:: ``tft.sh`` -.. _tft.sh: /OS/debian/tft.sh + $ git clone https://github.com/RedPitaya/RedPitaya.git + $ cd RedPitaya -Run the next command inside the project root directory. Root or ``sudo`` privileges are needed. +Run the next command to build the OS image. Root or ``sudo`` privileges are needed. +The code should be executed as the ``root`` user, +otherwise some configuration files will be placed into the wrong users home directory. .. code-block:: shell-session @@ -63,48 +131,35 @@ Run the next command inside the project root directory. Root or ``sudo`` privile # OS/debian/image.sh # exit -:source:`OS/debian/image.sh` will create an SD card image with a name containing the current date and time. -Two partitions are created a 128MB FAT32 partition and a alightly less then 4GB Ext4 partition. - -|image.sh|_ will call |ubuntu.sh|_ which installs the base system and some additional packages. -It also configures APT (Debian packaging system), locales, hostname, timezone, -file system table, U-boot and users (access to UART console). - -|ubuntu.sh|_ also executes |network.sh|_ which creates a -``systemd-networkd`` based wired and wireless network setup. -And it executes |redpitaya.sh|_ which installs additional -Debian packages (mostly libraries) needed by Red Pitaya applications. -|redpitaya.sh|_ also extracts ``ecosystem*.zip`` -(if one exists in the current directory) into the FAT partition. - -Optionally (code can be commented out) |ubuntu.sh|_ also executes -|jupyter.sh|_ and |tft.sh|_ which provide additional functionality. - -The generated image can be written to a SD card -using the ``dd`` command or the ``Disks`` tool (Restore Disk Image). +:download:`image.sh <../../../OS/debian/image.sh>` will create an SD card image with a name containing the current +date and time. Two partitions are created a 128MB FAT32 partition for the ecosystem and a slightly less then 4GB Ext4 partition. -.. code-block:: shell-session - - $ dd bs=4M if=debian_armhf_*.img of=/dev/sd? +:download:`image.sh <../../../OS/debian/image.sh>` will call :download:`ubuntu.sh <../../../OS/debian/ubuntu.sh>` +which installs the base system and some additional packages. It also configures APT (Debian packaging system), +locales, hostname, timezone, file system table, U-boot and users (access to UART console). -.. note:: +:download:`ubuntu.sh <../../../OS/debian/ubuntu.sh>` also executes +:download:`network.sh <../../../OS/debian/network.sh>` which creates a +``systemd-networkd`` based wired and wireless network setup. And it executes +:download:`redpitaya.sh <../../../OS/debian/redpitaya.sh>` which installs additional Debian packages (mostly libraries) +needed by Red Pitaya applications. :download:`redpitaya.sh <../../../OS/debian/redpitaya.sh>` also extracts +``ecosystem*.zip`` (if one exists in the current directory) into the FAT partition. - To get the correct destination storage device, - read the output of ``dmesg`` after you insert the SD card. - If the wrong device is specified, the content of another - drive may be overwritten, causing permanent loose of user data. +Optionally (code can be commented out) :download:`ubuntu.sh <../../../OS/debian/ubuntu.sh>` also executes +:download:`jupyter.sh <../../../OS/debian/jupyter.sh>` and :download:`tft.sh <../../../OS/debian/tft.sh>` which provide +additional functionality. -=============================== -Red Pitaya ecosystem extraction -=============================== +=========================== +Red Pitaya ecosystem update +=========================== In case an ``ecosystem*.zip`` file was not available for the previous step, it can be extracted later to the FAT partition (128MB) of the SD card. -In addition to Red Pitaya tools, this ecosystem ZIP file contains a boot image (containing FPGA code), +In addition to Red Pitaya tools, this ``ecosystem_*.zip`` file contains a boot image (containing FPGA code), a boot script (``u-boot.scr``) and the Linux kernel. -A script |image-update.sh|_ is provided for updating an existing image -to a newer ecosystem zippfile without making modifications to the ``ext4`` partition. +A script :download:`image-update.sh <../../../OS/debian/image-update.sh>` is provided for updating an existing image +to a newer ``ecosystem_*.zip`` file without making modifications to the ``ext4`` partition. The script should be run with the image and ecosystem files as arguments: @@ -119,7 +174,8 @@ File system check If the image creation involved multiple steps performed by the user, for example some installation/setup procedure performed on a live Red Pitaya, there is a possibility a file system might be corrupted. -The |image-fsck.sh|_ script performs a file system check without changing anything. +The :download:`image-fsck.sh <../../../OS/debian/image-fsck.sh>` script performs a file system check without changing +anything. Use this script on an image before releasing it. @@ -131,6 +187,11 @@ Use this script on an image before releasing it. Reducing image size =================== +.. note:: + + This steps should only be performed on a live Red Pitaya board. + If executed on the host OS, they can and will cause problems. + A cleanup can be performed to reduce the image size. Various things can be done to reduce the image size: * remove unused software (this could be software which was needed to compile applications) @@ -138,7 +199,7 @@ A cleanup can be performed to reduce the image size. Various things can be done * remove temporary files * zero out empty space on the partition -The next code only removes APT temporary files and zeros out the filesystem empty space. +The next code only removes APT temporary files and zeros out the file system empty space. .. code-block:: shell-session diff --git a/doc/developerGuide/os/network.rst b/doc/developerGuide/os/network.rst index a766b7e42..ecb519103 100644 --- a/doc/developerGuide/os/network.rst +++ b/doc/developerGuide/os/network.rst @@ -19,8 +19,7 @@ Quick setup WiFi client =========== -`Recommended USB Wi-Fi device for Raspberry PI -`_ can be used. +A list of `Supported USB Wi-Fi adapters`_ is provided at the bottom of the page. List wireless access pints: @@ -409,38 +408,379 @@ Services handling the described configuration are enabled with. # enable service for creating SSH keys on first boot systemctl enable ssh-reconfigure -*************** -Wireless driver -*************** +**************************** +Supported USB Wi-Fi adapters +**************************** -============= -Current setup -============= +Support for a specific Wi-Fi adapter usually depends only on the availability +of the driver for the chipset used in the adapter. +Therefore this section focuses on Linux kernel drivers for Wi-Fi adapters. -Currently an `out of tree driver `_ is used to support devices based on the ``RTL8188CUS`` chip. -For example. +Before the switch to kernel 4.9 an out of tree driver was used for the **rtl8192cu** chipset. +Support for this patch was removed, due to reliability and maintenance issues. +In practice this means *rtl8192cu* based adapters will only work in client mode. +At the same time support for the deprecated user space tools ``wireless extensions`` +was removed, instead the ``nl80211`` framework should be used. +In practice this means ``iw`` should be used instead of ``iwconfig``. + +After plugging an USB Wi-Fi adapter use ``dmesg`` and ``lsusb`` to check +if the adapter was properly recognized by the Linux kernel. + +To check what modes (managed, AP, ...) are supported by an adapter use ``iw``. + +================ +BCM43143 chipset +================ + +Client (``managed``) and access point (``AP``) modes are supported. + +--------------------------------------------- +Recommended USB Wi-Fi device for Raspberry PI +--------------------------------------------- + +https://www.raspberrypi.org/products/usb-wifi-dongle/ + +https://web.archive.org/web/20161014035710/https://www.raspberrypi.org/products/usb-wifi-dongle/ .. code-block:: shell-session # lsusb - Bus 001 Device 003: ID 0bda:8176 Realtek Semiconductor Corp. RTL8188CUS 802.11n WLAN Adapter - Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub + Bus 001 Device 004: ID 0a5c:bd1e Broadcom Corp. + +.. code-block:: shell-session + + # dmesg + ... + usb 1-1: new high-speed USB device number 4 using ci_hdrc + brcmfmac: brcmf_c_preinit_dcmds: Firmware version = wl0: Apr 3 2014 04:43:32 version 6.10.198.66 (r467479) FWID 01-32bd010e + brcmfmac: brcmf_cfg80211_reg_notifier: not a ISO3166 code (0x30 0x30) + ... + usb 1-1: USB disconnect, device number 4 + brcmfmac: brcmf_usb_send_ctl: usb_submit_urb failed -19 + brcmfmac: brcmf_usb_tx_ctlpkt: fail -19 bytes: 45 + brcmfmac: brcmf_fil_cmd_data: bus is down. we have nothing to do. + brcmfmac: brcmf_fil_cmd_data: bus is down. we have nothing to do. + brcmfmac: brcmf_fil_cmd_data: bus is down. we have nothing to do. + brcmfmac: brcmf_cfg80211_get_channel: chanspec failed (-5) + +.. code-block:: shell-session + + # iw list + Wiphy phy3 + max # scan SSIDs: 10 + max scan IEs length: 2048 bytes + Retry short limit: 7 + Retry long limit: 4 + Coverage class: 0 (up to 0m) + Device supports roaming. + Supported Ciphers: + * WEP40 (00-0f-ac:1) + * WEP104 (00-0f-ac:5) + * TKIP (00-0f-ac:2) + * CCMP (00-0f-ac:4) + Available Antennas: TX 0 RX 0 + Supported interface modes: + * IBSS + * managed + * AP + * P2P-client + * P2P-GO + * P2P-device + Band 1: + Capabilities: 0x1022 + HT20/HT40 + Static SM Power Save + RX HT20 SGI + No RX STBC + Max AMSDU length: 3839 bytes + DSSS/CCK HT40 + Maximum RX AMPDU length 65535 bytes (exponent: 0x003) + Minimum RX AMPDU time spacing: 16 usec (0x07) + HT TX/RX MCS rate indexes supported: 0-7 + Bitrates (non-HT): + * 1.0 Mbps + * 2.0 Mbps (short preamble supported) + * 5.5 Mbps (short preamble supported) + * 11.0 Mbps (short preamble supported) + * 6.0 Mbps + * 9.0 Mbps + * 12.0 Mbps + * 18.0 Mbps + * 24.0 Mbps + * 36.0 Mbps + * 48.0 Mbps + * 54.0 Mbps + Frequencies: + * 2412 MHz [1] (20.0 dBm) + * 2417 MHz [2] (20.0 dBm) + * 2422 MHz [3] (20.0 dBm) + * 2427 MHz [4] (20.0 dBm) + * 2432 MHz [5] (20.0 dBm) + * 2437 MHz [6] (20.0 dBm) + * 2442 MHz [7] (20.0 dBm) + * 2447 MHz [8] (20.0 dBm) + * 2452 MHz [9] (20.0 dBm) + * 2457 MHz [10] (20.0 dBm) + * 2462 MHz [11] (20.0 dBm) + * 2467 MHz [12] (disabled) + * 2472 MHz [13] (disabled) + * 2484 MHz [14] (disabled) + Supported commands: + * new_interface + * set_interface + * new_key + * start_ap + * join_ibss + * set_pmksa + * del_pmksa + * flush_pmksa + * remain_on_channel + * frame + * set_channel + * start_p2p_device + * crit_protocol_start + * crit_protocol_stop + * connect + * disconnect + Supported TX frame types: + * managed: 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xa0 0xb0 0xc0 0xd0 0xe0 0xf0 + * P2P-client: 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xa0 0xb0 0xc0 0xd0 0xe0 0xf0 + * P2P-GO: 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xa0 0xb0 0xc0 0xd0 0xe0 0xf0 + * P2P-device: 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xa0 0xb0 0xc0 0xd0 0xe0 0xf0 + Supported RX frame types: + * managed: 0x40 0xd0 + * P2P-client: 0x40 0xd0 + * P2P-GO: 0x00 0x20 0x40 0xa0 0xb0 0xc0 0xd0 + * P2P-device: 0x40 0xd0 + software interface modes (can always be added): + valid interface combinations: + * #{ managed } <= 1, #{ P2P-device } <= 1, #{ P2P-client, P2P-GO } <= 1, + total <= 3, #channels <= 1 + * #{ managed } <= 1, #{ AP } <= 1, #{ P2P-client } <= 1, #{ P2P-device } <= 1, + total <= 4, #channels <= 1 + Device supports scan flush. + +================= +rtl8192cu chipset +================= + +The rtl8192cu chipset is supported by the ``rtl8xxxu`` driver. +For now this driver only supports client (``managed``) mode. + +---------------- +Edimax EW-7811Un +---------------- + +http://us.edimax.com/edimax/merchandise/merchandise_detail/data/edimax/us/wireless_adapters_n150/ew-7811un/ + +.. code-block:: shell-session + + # lsusb + Bus 001 Device 002: ID 7392:7811 Edimax Technology Co., Ltd EW-7811Un 802.11n Wireless Adapter [Realtek RTL8188CUS] -This driver supports client and access point modes, and is the most documented driver/device combination -for seeing up an access point using an USB adapter. Most of the documentation is intended for Raspberry Pi. +.. code-block:: shell-session + + # dmesg + ... + usb 1-1: new high-speed USB device number 2 using ci_hdrc + usb 1-1: Vendor: Realtek + usb 1-1: Product: 802.11n WLAN Adapter + usb 1-1: rtl8192cu_parse_efuse: dumping efuse (0x80 bytes): + usb 1-1: 00: 29 81 00 74 cd 00 00 00 + usb 1-1: 08: ff 00 92 73 11 78 03 41 + usb 1-1: 10: 32 00 85 62 9e ad 74 da + usb 1-1: 18: 38 7d d0 48 0a 03 52 65 + usb 1-1: 20: 61 6c 74 65 6b 00 16 03 + usb 1-1: 28: 38 30 32 2e 31 31 6e 20 + usb 1-1: 30: 57 4c 41 4e 20 41 64 61 + usb 1-1: 38: 70 74 65 72 00 00 00 00 + usb 1-1: 40: 00 00 00 00 00 00 00 00 + usb 1-1: 48: 00 00 00 00 00 00 00 00 + usb 1-1: 50: 00 00 00 00 00 00 00 00 + usb 1-1: 58: 06 00 29 29 29 00 00 00 + usb 1-1: 60: 2b 2b 2a 00 00 00 00 00 + usb 1-1: 68: 00 00 00 00 11 11 33 00 + usb 1-1: 70: 00 00 00 00 00 02 00 00 + usb 1-1: 78: 10 00 00 00 36 00 00 00 + usb 1-1: RTL8188CU rev A (TSMC) 1T1R, TX queues 2, WiFi=1, BT=0, GPS=0, HI PA=0 + usb 1-1: RTL8188CU MAC: 74:da:38:7d:d0:48 + usb 1-1: rtl8xxxu: Loading firmware rtlwifi/rtl8192cufw_TMSC.bin + usb 1-1: Firmware revision 80.0 (signature 0x88c1) + usb 1-1: rtl8xxxu_iqk_path_a: Path A RX IQK failed! + usb 1-1: rtl8xxxu_iqk_path_a: Path A RX IQK failed! + usb 1-1: rtl8xxxu_iqk_path_a: Path A RX IQK failed! + usb 1-1: rtl8xxxu_iqk_path_a: Path A RX IQK failed! + ... + usb 1-1: USB disconnect, device number 2 + usb 1-1: rtl8xxxu_active_to_lps: RX poll timed out (0x05f8) + usb 1-1: rtl8xxxu_active_to_emu: Disabling MAC timed out + usb 1-1: disconnecting + +.. code-block:: shell-session -We would like to get rid of this driver, since it requires maintaining a patch, -and it requires deprecated user space tools ``wireless extensions`` and a -`patched hostapd `_. + # iw list + Wiphy phy0 + max # scan SSIDs: 4 + max scan IEs length: 2257 bytes + RTS threshold: 2347 + Retry short limit: 7 + Retry long limit: 4 + Coverage class: 0 (up to 0m) + Supported Ciphers: + * WEP40 (00-0f-ac:1) + * WEP104 (00-0f-ac:5) + * TKIP (00-0f-ac:2) + * CCMP (00-0f-ac:4) + * 00-0f-ac:10 + * GCMP (00-0f-ac:8) + * 00-0f-ac:9 + Available Antennas: TX 0 RX 0 + Supported interface modes: + * managed + * monitor + Band 1: + Capabilities: 0x60 + HT20 + Static SM Power Save + RX HT20 SGI + RX HT40 SGI + No RX STBC + Max AMSDU length: 3839 bytes + No DSSS/CCK HT40 + Maximum RX AMPDU length 65535 bytes (exponent: 0x003) + Minimum RX AMPDU time spacing: 16 usec (0x07) + HT TX/RX MCS rate indexes supported: 0-7, 32 + Bitrates (non-HT): + * 1.0 Mbps + * 2.0 Mbps + * 5.5 Mbps + * 11.0 Mbps + * 6.0 Mbps + * 9.0 Mbps + * 12.0 Mbps + * 18.0 Mbps + * 24.0 Mbps + * 36.0 Mbps + * 48.0 Mbps + * 54.0 Mbps + Frequencies: + * 2412 MHz [1] (20.0 dBm) + * 2417 MHz [2] (20.0 dBm) + * 2422 MHz [3] (20.0 dBm) + * 2427 MHz [4] (20.0 dBm) + * 2432 MHz [5] (20.0 dBm) + * 2437 MHz [6] (20.0 dBm) + * 2442 MHz [7] (20.0 dBm) + * 2447 MHz [8] (20.0 dBm) + * 2452 MHz [9] (20.0 dBm) + * 2457 MHz [10] (20.0 dBm) + * 2462 MHz [11] (20.0 dBm) + * 2467 MHz [12] (20.0 dBm) (no IR) + * 2472 MHz [13] (20.0 dBm) (no IR) + * 2484 MHz [14] (20.0 dBm) (no IR) + Supported commands: + * new_interface + * set_interface + * new_key + * start_ap + * new_station + * set_bss + * authenticate + * associate + * deauthenticate + * disassociate + * join_ibss + * set_tx_bitrate_mask + * frame + * frame_wait_cancel + * set_wiphy_netns + * set_channel + * set_wds_peer + * probe_client + * set_noack_map + * register_beacons + * start_p2p_device + * set_mcast_rate + * Unknown command (104) + * connect + * disconnect + Supported TX frame types: + * IBSS: 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xa0 0xb0 0xc0 0xd0 0xe0 0xf0 + * managed: 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xa0 0xb0 0xc0 0xd0 0xe0 0xf0 + * AP: 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xa0 0xb0 0xc0 0xd0 0xe0 0xf0 + * AP/VLAN: 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xa0 0xb0 0xc0 0xd0 0xe0 0xf0 + * mesh point: 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xa0 0xb0 0xc0 0xd0 0xe0 0xf0 + * P2P-client: 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xa0 0xb0 0xc0 0xd0 0xe0 0xf0 + * P2P-GO: 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xa0 0xb0 0xc0 0xd0 0xe0 0xf0 + * P2P-device: 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xa0 0xb0 0xc0 0xd0 0xe0 0xf0 + Supported RX frame types: + * IBSS: 0x40 0xb0 0xc0 0xd0 + * managed: 0x40 0xd0 + * AP: 0x00 0x20 0x40 0xa0 0xb0 0xc0 0xd0 + * AP/VLAN: 0x00 0x20 0x40 0xa0 0xb0 0xc0 0xd0 + * mesh point: 0xb0 0xc0 0xd0 + * P2P-client: 0x40 0xd0 + * P2P-GO: 0x00 0x20 0x40 0xa0 0xb0 0xc0 0xd0 + * P2P-device: 0x40 0xd0 + software interface modes (can always be added): + * monitor + interface combinations are not supported + HT Capability overrides: + * MCS: ff ff ff ff ff ff ff ff ff ff + * maximum A-MSDU length + * supported channel width + * short GI for 40 MHz + * max A-MPDU length exponent + * min MPDU start spacing + Device supports TX status socket option. + Device supports HT-IBSS. + Device supports SAE with AUTHENTICATE command + Device supports low priority scan. + Device supports scan flush. + Device supports AP scan. + Device supports per-vif TX power setting + Driver supports full state transitions for AP/GO clients + Driver supports a userspace MPM + +------------------------------------------------------ +Generic Realtek Semiconductor Corp. RTL8188CUS 802.11n +------------------------------------------------------ -===================== -Proposed future setup -===================== +.. code-block:: shell-session -There is another much newer driver available in the kernel tree, but it currently only supports client mode. + # dmesg + ... + usb 1-1: new high-speed USB device number 3 using ci_hdrc + usb 1-1: Vendor: Realtek + usb 1-1: Product: 802.11n WLAN Adapter + usb 1-1: rtl8192cu_parse_efuse: dumping efuse (0x80 bytes): + usb 1-1: 00: 29 81 00 74 cd 00 00 00 + usb 1-1: 08: ff 00 da 0b 76 81 01 41 + usb 1-1: 10: 32 00 85 62 9e ad 00 13 + usb 1-1: 18: ef 60 22 15 0a 03 52 65 + usb 1-1: 20: 61 6c 74 65 6b 00 16 03 + usb 1-1: 28: 38 30 32 2e 31 31 6e 20 + usb 1-1: 30: 57 4c 41 4e 20 41 64 61 + usb 1-1: 38: 70 74 65 72 00 00 00 00 + usb 1-1: 40: 00 00 00 00 00 00 00 00 + usb 1-1: 48: 00 00 00 00 00 00 00 00 + usb 1-1: 50: 00 00 00 00 00 00 00 00 + usb 1-1: 58: 06 00 28 28 28 00 00 00 + usb 1-1: 60: 28 28 28 00 00 00 00 00 + usb 1-1: 68: 00 00 00 00 02 02 02 00 + usb 1-1: 70: 00 00 00 00 00 02 00 00 + usb 1-1: 78: 10 00 00 00 36 00 00 00 + usb 1-1: RTL8188CU rev A (TSMC) 1T1R, TX queues 2, WiFi=1, BT=0, GPS=0, HI PA=0 + usb 1-1: RTL8188CU MAC: 00:13:ef:60:22:15 + usb 1-1: rtl8xxxu: Loading firmware rtlwifi/rtl8192cufw_TMSC.bin + usb 1-1: Firmware revision 80.0 (signature 0x88c1) + ... + usb 1-1: USB disconnect, device number 3 + usb 1-1: rtl8xxxu_active_to_lps: RX poll timed out (0x05f8) + usb 1-1: rtl8xxxu_active_to_emu: Disabling MAC timed out + usb 1-1: disconnecting -We are following progress on the ``rtl8xxxu`` driver in the -`authors (Jes Sorensen) `_ repository -on `kernel.org `_. +.. code-block:: shell-session -We already tested this new driver in the past, and it worked well in client mode. + # lsusb + Bus 001 Device 003: ID 0bda:8176 Realtek Semiconductor Corp. RTL8188CUS 802.11n WLAN Adapter diff --git a/doc/developerGuide/pinConfig.rst b/doc/developerGuide/pinConfig.rst new file mode 100644 index 000000000..10a2150bf --- /dev/null +++ b/doc/developerGuide/pinConfig.rst @@ -0,0 +1,474 @@ +#################################################################################### +1. State of the I/Os after all the power rails are powered and before configuration? +#################################################################################### + +SOURCE: https://www.xilinx.com/support/answers/50802.html + +The recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO, and VCCO to achieve minimum current draw and +ensure that the I/Os are 3-stated at power-on. + +The 7 series FPGAs contain a pin called PUDC_B. When PUDC_B is Low, internal pull-up resistors are enabled on each +SelectIO pin. When PUDC_B is High, internal pull-up resistors are disabled on each SelectIO pin. The state of this pin +effects the state of the I/O from power-on until configuration completes. Therefore, the I/Os will be 3-stated after +power-on when PUDC is High. + +The state of the I/O prior to the rails being powered is not guaranteed. + +.. note:: + + Due to the presence of the clamp diode, if the I/Os are driven before Vcco powered this will reverse bias the + Vcco rail. For further information, see (Xilinx Answer 45985). + +SOURCE: https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf ++----------+----------------+-----------+----------------------------------------------------------+ +| Pin Name | Type | Direction | Description | +| | | | Pull-Up During Configuration (bar) | +| | | | Active-Low PUDC_B input enables internal pull-up | +| | | | resistors on the SelectIO pins after power-up and during | +| | | | configuration. | +| PUDC_B | Multi-function | Input | ° When PUDC_B is Low, internal pull-up resistors | +| | | | are enabled on each SelectIO pin. | +| | | | ° When PUDC_B is High, internal pull-up resistors are | +| | | | disabled on each SelectIO pin. | +| | | | PUDC_B must be tied either directly (or through a 1KΩ or | +| | | | less resistor) to VCCO_34 or GND. | +| | | | CAUTION! Do not allow this pin to float before and | +| | | | during configuration. | ++----------+----------------+-----------+----------------------------------------------------------+ + +.. note:: + + On the Red Pitaya board PUDC_B pin is grounded through a capacitor C100. If needed it can be changed, more + information can be found at http://redpitaya.readthedocs.io/en/latest/developerGuide/125-14/shem.html. + +################################ +2. IO Assignments by Package Pin +################################ + +A report on current PIN configuration can be generated during synthesis by adding +'report_io -file $path_out/post_imp_io.rpt' +to the +'fpga/red_pitaya_vivado.tcl' +file. This will generate a report in the +'fpga/prj/classic/out/post_imp_io.rpt' + + +Table bellow shows the current setting of PINs. ++------------+-------------------+------------+-------------------------+---------------+-------------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | ++------------+-------------------+------------+-------------------------+---------------+-------------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+ +| A1 | DDR_dm[0] | | PS_DDR_DM0_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| A2 | DDR_dq[2] | | PS_DDR_DQ2_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| A3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| A4 | DDR_dq[3] | | PS_DDR_DQ3_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| A5 | FIXED_IO_mio[6] | | PS_MIO6_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| A6 | FIXED_IO_mio[5] | | PS_MIO5_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| A7 | FIXED_IO_mio[1] | | PS_MIO1_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| A8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| A9 | FIXED_IO_mio[43] | | PS_MIO43_501 | BIDIR | LVCMOS25 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| A10 | FIXED_IO_mio[37] | | PS_MIO37_501 | BIDIR | LVCMOS25 | | 8 | FAST | | NONE | | FIXED | | | | NONE | +| A11 | FIXED_IO_mio[36] | | PS_MIO36_501 | BIDIR | LVCMOS25 | | 8 | FAST | | NONE | | FIXED | | | | NONE | +| A12 | FIXED_IO_mio[34] | | PS_MIO34_501 | BIDIR | LVCMOS25 | | 8 | FAST | | NONE | | FIXED | | | | NONE | +| A13 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| A14 | FIXED_IO_mio[32] | | PS_MIO32_501 | BIDIR | LVCMOS25 | | 8 | FAST | | NONE | | FIXED | | | | NONE | +| A15 | FIXED_IO_mio[26] | | PS_MIO26_501 | BIDIR | LVCMOS25 | | 8 | FAST | | NONE | | FIXED | | | | NONE | +| A16 | FIXED_IO_mio[24] | | PS_MIO24_501 | BIDIR | LVCMOS25 | | 8 | FAST | | NONE | | FIXED | | | | NONE | +| A17 | FIXED_IO_mio[20] | | PS_MIO20_501 | BIDIR | LVCMOS25 | | 8 | FAST | | NONE | | FIXED | | | | NONE | +| A18 | | | GND | GND | | | | | | | 0.0 | | | | | | +| A19 | FIXED_IO_mio[16] | | PS_MIO16_501 | BIDIR | LVCMOS25 | | 8 | FAST | | NONE | | FIXED | | | | NONE | +| A20 | vinn_i[0] | High Range | IO_L2N_T0_AD8N_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | +| B1 | | | GND | GND | | | | | | | 0.0 | | | | | | +| B2 | DDR_dqs_n[0] | | PS_DDR_DQS_N0_502 | BIDIR | DIFF_SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| B3 | DDR_dq[1] | | PS_DDR_DQ1_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| B4 | DDR_reset_n | | PS_DDR_DRST_B_502 | BIDIR | SSTL15 | | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | +| B5 | FIXED_IO_mio[9] | | PS_MIO9_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| B6 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | +| B7 | FIXED_IO_mio[4] | | PS_MIO4_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| B8 | FIXED_IO_mio[2] | | PS_MIO2_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| B9 | FIXED_IO_mio[51] | | PS_MIO51_501 | BIDIR | LVCMOS25 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| B10 | FIXED_IO_ps_srstb | | PS_SRST_B_501 | BIDIR | LVCMOS25 | | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | +| B11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| B12 | FIXED_IO_mio[48] | | PS_MIO48_501 | BIDIR | LVCMOS25 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| B13 | FIXED_IO_mio[50] | | PS_MIO50_501 | BIDIR | LVCMOS25 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| B14 | FIXED_IO_mio[47] | | PS_MIO47_501 | BIDIR | LVCMOS25 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| B15 | FIXED_IO_mio[45] | | PS_MIO45_501 | BIDIR | LVCMOS25 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| B16 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| B17 | FIXED_IO_mio[22] | | PS_MIO22_501 | BIDIR | LVCMOS25 | | 8 | FAST | | NONE | | FIXED | | | | NONE | +| B18 | FIXED_IO_mio[18] | | PS_MIO18_501 | BIDIR | LVCMOS25 | | 8 | FAST | | NONE | | FIXED | | | | NONE | +| B19 | vinp_i[0] | High Range | IO_L2P_T0_AD8P_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | +| B20 | vinn_i[1] | High Range | IO_L1N_T0_AD0N_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | +| C1 | DDR_dq[6] | | PS_DDR_DQ6_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| C2 | DDR_dqs_p[0] | | PS_DDR_DQS_P0_502 | BIDIR | DIFF_SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| C3 | DDR_dq[0] | | PS_DDR_DQ0_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| C4 | | | GND | GND | | | | | | | 0.0 | | | | | | +| C5 | FIXED_IO_mio[14] | | PS_MIO14_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| C6 | FIXED_IO_mio[11] | | PS_MIO11_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| C7 | FIXED_IO_ps_porb | | PS_POR_B_500 | BIDIR | LVCMOS33 | | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | +| C8 | FIXED_IO_mio[15] | | PS_MIO15_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| C9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| C10 | FIXED_IO_mio[52] | | PS_MIO52_501 | BIDIR | LVCMOS25 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| C11 | FIXED_IO_mio[53] | | PS_MIO53_501 | BIDIR | LVCMOS25 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| C12 | FIXED_IO_mio[49] | | PS_MIO49_501 | BIDIR | LVCMOS25 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| C13 | FIXED_IO_mio[29] | | PS_MIO29_501 | BIDIR | LVCMOS25 | | 8 | FAST | | NONE | | FIXED | | | | NONE | +| C14 | | | GND | GND | | | | | | | 0.0 | | | | | | +| C15 | FIXED_IO_mio[30] | | PS_MIO30_501 | BIDIR | LVCMOS25 | | 8 | FAST | | NONE | | FIXED | | | | NONE | +| C16 | FIXED_IO_mio[28] | | PS_MIO28_501 | BIDIR | LVCMOS25 | | 8 | FAST | | NONE | | FIXED | | | | NONE | +| C17 | FIXED_IO_mio[41] | | PS_MIO41_501 | BIDIR | LVCMOS25 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| C18 | FIXED_IO_mio[39] | | PS_MIO39_501 | BIDIR | LVCMOS25 | | 8 | FAST | | NONE | | FIXED | | | | NONE | +| C19 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | +| C20 | vinp_i[1] | High Range | IO_L1P_T0_AD0P_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | +| D1 | DDR_dq[5] | | PS_DDR_DQ5_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| D2 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| D3 | DDR_dq[4] | | PS_DDR_DQ4_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| D4 | DDR_addr[13] | | PS_DDR_A13_502 | BIDIR | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| D5 | FIXED_IO_mio[8] | | PS_MIO8_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| D6 | FIXED_IO_mio[3] | | PS_MIO3_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| D7 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | +| D8 | FIXED_IO_mio[7] | | PS_MIO7_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| D9 | FIXED_IO_mio[12] | | PS_MIO12_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| D10 | FIXED_IO_mio[19] | | PS_MIO19_501 | BIDIR | LVCMOS25 | | 8 | FAST | | NONE | | FIXED | | | | NONE | +| D11 | FIXED_IO_mio[23] | | PS_MIO23_501 | BIDIR | LVCMOS25 | | 8 | FAST | | NONE | | FIXED | | | | NONE | +| D12 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| D13 | FIXED_IO_mio[27] | | PS_MIO27_501 | BIDIR | LVCMOS25 | | 8 | FAST | | NONE | | FIXED | | | | NONE | +| D14 | FIXED_IO_mio[40] | | PS_MIO40_501 | BIDIR | LVCMOS25 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| D15 | FIXED_IO_mio[33] | | PS_MIO33_501 | BIDIR | LVCMOS25 | | 8 | FAST | | NONE | | FIXED | | | | NONE | +| D16 | FIXED_IO_mio[46] | | PS_MIO46_501 | BIDIR | LVCMOS25 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| D17 | | | GND | GND | | | | | | | 0.0 | | | | | | +| D18 | vinn_i[2] | High Range | IO_L3N_T0_DQS_AD1N_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | +| D19 | dac_dat_o[13] | High Range | IO_L4P_T0_35 | OUTPUT | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| D20 | dac_dat_o[12] | High Range | IO_L4N_T0_35 | OUTPUT | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| E1 | DDR_dq[7] | | PS_DDR_DQ7_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| E2 | DDR_dq[8] | | PS_DDR_DQ8_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| E3 | DDR_dq[9] | | PS_DDR_DQ9_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| E4 | DDR_addr[12] | | PS_DDR_A12_502 | BIDIR | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| E5 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| E6 | FIXED_IO_mio[0] | | PS_MIO0_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| E7 | FIXED_IO_ps_clk | | PS_CLK_500 | BIDIR | LVCMOS33 | | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | +| E8 | FIXED_IO_mio[13] | | PS_MIO13_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| E9 | FIXED_IO_mio[10] | | PS_MIO10_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| E10 | | | GND | GND | | | | | | | 0.0 | | | | | | +| E11 | | | PS_MIO_VREF_501 | PSS IO | | | | | | | | | | | | | +| E12 | FIXED_IO_mio[42] | | PS_MIO42_501 | BIDIR | LVCMOS25 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| E13 | FIXED_IO_mio[38] | | PS_MIO38_501 | BIDIR | LVCMOS25 | | 8 | FAST | | NONE | | FIXED | | | | NONE | +| E14 | FIXED_IO_mio[17] | | PS_MIO17_501 | BIDIR | LVCMOS25 | | 8 | FAST | | NONE | | FIXED | | | | NONE | +| E15 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| E16 | FIXED_IO_mio[31] | | PS_MIO31_501 | BIDIR | LVCMOS25 | | 8 | FAST | | NONE | | FIXED | | | | NONE | +| E17 | vinp_i[2] | High Range | IO_L3P_T0_DQS_AD1P_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | +| E18 | vinp_i[3] | High Range | IO_L5P_T0_AD9P_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | +| E19 | vinn_i[3] | High Range | IO_L5N_T0_AD9N_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | +| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | +| F1 | DDR_dm[1] | | PS_DDR_DM1_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| F2 | DDR_dqs_n[1] | | PS_DDR_DQS_N1_502 | BIDIR | DIFF_SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| F3 | | | GND | GND | | | | | | | 0.0 | | | | | | +| F4 | DDR_addr[14] | | PS_DDR_A14_502 | BIDIR | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| F5 | DDR_addr[10] | | PS_DDR_A10_502 | BIDIR | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| F6 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| F8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| F9 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | +| F10 | | | RSVDGND | GND | | | | | | | | | | | | | +| F11 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | +| F12 | FIXED_IO_mio[35] | | PS_MIO35_501 | BIDIR | LVCMOS25 | | 8 | FAST | | NONE | | FIXED | | | | NONE | +| F13 | FIXED_IO_mio[44] | | PS_MIO44_501 | BIDIR | LVCMOS25 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| F14 | FIXED_IO_mio[21] | | PS_MIO21_501 | BIDIR | LVCMOS25 | | 8 | FAST | | NONE | | FIXED | | | | NONE | +| F15 | FIXED_IO_mio[25] | | PS_MIO25_501 | BIDIR | LVCMOS25 | | 8 | FAST | | NONE | | FIXED | | | | NONE | +| F16 | led_o[0] | High Range | IO_L6P_T0_35 | BIDIR | LVCMOS33 | 35 | 4 | SLOW | | NONE | | FIXED | | | | NONE | +| F17 | led_o[1] | High Range | IO_L6N_T0_VREF_35 | BIDIR | LVCMOS33 | 35 | 4 | SLOW | | NONE | | FIXED | | | | NONE | +| F18 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | +| F19 | dac_dat_o[10] | High Range | IO_L15P_T2_DQS_AD12P_35 | OUTPUT | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| F20 | dac_dat_o[11] | High Range | IO_L15N_T2_DQS_AD12N_35 | OUTPUT | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| G1 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| G2 | DDR_dqs_p[1] | | PS_DDR_DQS_P1_502 | BIDIR | DIFF_SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| G3 | DDR_dq[10] | | PS_DDR_DQ10_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| G4 | DDR_addr[11] | | PS_DDR_A11_502 | BIDIR | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| G5 | FIXED_IO_ddr_vrn | | PS_DDR_VRN_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| G6 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | +| G7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| G8 | | | VCCPLL | PSS VCCPLL | | | | | | | | | | | | | +| G9 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | +| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| G13 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| G14 | led_o[5] | High Range | IO_0_35 | BIDIR | LVCMOS33 | 35 | 4 | SLOW | | NONE | | FIXED | | | | NONE | +| G15 | led_o[2] | High Range | IO_L19N_T3_VREF_35 | BIDIR | LVCMOS33 | 35 | 4 | SLOW | | NONE | | FIXED | | | | NONE | +| G16 | | | GND | GND | | | | | | | 0.0 | | | | | | +| G17 | exp_p_io[0] | High Range | IO_L16P_T2_35 | BIDIR | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| G18 | exp_n_io[0] | High Range | IO_L16N_T2_35 | BIDIR | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| G19 | dac_dat_o[8] | High Range | IO_L18P_T2_AD13P_35 | OUTPUT | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| G20 | dac_dat_o[9] | High Range | IO_L18N_T2_AD13N_35 | OUTPUT | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| H1 | DDR_dq[14] | | PS_DDR_DQ14_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| H2 | DDR_dq[13] | | PS_DDR_DQ13_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| H3 | DDR_dq[11] | | PS_DDR_DQ11_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| H4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| H5 | FIXED_IO_ddr_vrp | | PS_DDR_VRP_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| H6 | | | PS_DDR_VREF0_502 | PSS IO | | | | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| H9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H12 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H14 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | +| H15 | led_o[3] | High Range | IO_L19P_T3_35 | BIDIR | LVCMOS33 | 35 | 4 | SLOW | | NONE | | FIXED | | | | NONE | +| H16 | exp_p_io[1] | High Range | IO_L13P_T2_MRCC_35 | BIDIR | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| H17 | exp_n_io[1] | High Range | IO_L13N_T2_MRCC_35 | BIDIR | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| H18 | exp_n_io[2] | High Range | IO_L14N_T2_AD4N_SRCC_35 | BIDIR | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| H19 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H20 | dac_dat_o[7] | High Range | IO_L17N_T2_AD5N_35 | OUTPUT | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| J1 | DDR_dq[15] | | PS_DDR_DQ15_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| J2 | | | GND | GND | | | | | | | 0.0 | | | | | | +| J3 | DDR_dq[12] | | PS_DDR_DQ12_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| J4 | DDR_addr[9] | | PS_DDR_A9_502 | BIDIR | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| J5 | DDR_ba[2] | | PS_DDR_BA2_502 | BIDIR | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| J6 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | +| J7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| J9 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | +| J10 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | +| J11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| J13 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| J14 | led_o[7] | High Range | IO_L20N_T3_AD6N_35 | BIDIR | LVCMOS33 | 35 | 4 | SLOW | | NONE | | FIXED | | | | NONE | +| J15 | led_o[6] | High Range | IO_25_35 | BIDIR | LVCMOS33 | 35 | 4 | SLOW | | NONE | | FIXED | | | | NONE | +| J16 | exp_n_io[6] | High Range | IO_L24N_T3_AD15N_35 | BIDIR | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| J17 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | +| J18 | exp_p_io[2] | High Range | IO_L14P_T2_AD4P_SRCC_35 | BIDIR | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| J19 | dac_dat_o[5] | High Range | IO_L10N_T1_AD11N_35 | OUTPUT | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| J20 | dac_dat_o[6] | High Range | IO_L17P_T2_AD5P_35 | OUTPUT | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| K1 | DDR_addr[8] | | PS_DDR_A8_502 | BIDIR | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| K2 | DDR_addr[1] | | PS_DDR_A1_502 | BIDIR | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| K3 | DDR_addr[3] | | PS_DDR_A3_502 | BIDIR | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| K4 | DDR_addr[7] | | PS_DDR_A7_502 | BIDIR | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K6 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| K9 | vinp_i[4] | Dedicated | VP_0 | INPUT | LVCMOS33 | 0 | | | | NONE | | FIXED | | | | NONE | +| K10 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K12 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| K13 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K14 | led_o[4] | High Range | IO_L20P_T3_AD6P_35 | BIDIR | LVCMOS33 | 35 | 4 | SLOW | | NONE | | FIXED | | | | NONE | +| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K16 | exp_p_io[6] | High Range | IO_L24P_T3_AD15P_35 | BIDIR | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| K17 | exp_p_io[3] | High Range | IO_L12P_T1_MRCC_35 | BIDIR | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| K18 | exp_n_io[3] | High Range | IO_L12N_T1_MRCC_35 | BIDIR | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| K19 | dac_dat_o[4] | High Range | IO_L10P_T1_AD11P_35 | OUTPUT | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| K20 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | +| L1 | DDR_addr[5] | | PS_DDR_A5_502 | BIDIR | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| L2 | DDR_ck_p | | PS_DDR_CKP_502 | BIDIR | DIFF_SSTL15 | | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | +| L3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| L4 | DDR_addr[6] | | PS_DDR_A6_502 | BIDIR | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| L5 | DDR_ba[0] | | PS_DDR_BA0_502 | BIDIR | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| L6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | +| L7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| L9 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | +| L10 | vinn_i[4] | Dedicated | VN_0 | INPUT | LVCMOS33 | 0 | | | | NONE | | FIXED | | | | NONE | +| L11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| L13 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| L14 | exp_p_io[4] | High Range | IO_L22P_T3_AD7P_35 | BIDIR | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| L15 | exp_n_io[4] | High Range | IO_L22N_T3_AD7N_35 | BIDIR | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| L16 | exp_p_io[5] | High Range | IO_L11P_T1_SRCC_35 | BIDIR | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| L17 | exp_n_io[5] | High Range | IO_L11N_T1_SRCC_35 | BIDIR | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| L18 | | | GND | GND | | | | | | | 0.0 | | | | | | +| L19 | dac_dat_o[2] | High Range | IO_L9P_T1_DQS_AD3P_35 | OUTPUT | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| L20 | dac_dat_o[3] | High Range | IO_L9N_T1_DQS_AD3N_35 | OUTPUT | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| M1 | | | GND | GND | | | | | | | 0.0 | | | | | | +| M2 | DDR_ck_n | | PS_DDR_CKN_502 | BIDIR | DIFF_SSTL15 | | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | +| M3 | DDR_addr[2] | | PS_DDR_A2_502 | BIDIR | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| M4 | DDR_addr[4] | | PS_DDR_A4_502 | BIDIR | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| M5 | DDR_we_n | | PS_DDR_WE_B_502 | BIDIR | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| M6 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| M8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| M9 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | +| M10 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| M12 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | +| M14 | exp_p_io[7] | High Range | IO_L23P_T3_35 | BIDIR | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| M15 | exp_n_io[7] | High Range | IO_L23N_T3_35 | BIDIR | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| M16 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | +| M17 | dac_wrt_o | High Range | IO_L8P_T1_AD10P_35 | OUTPUT | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| M18 | dac_clk_o | High Range | IO_L8N_T1_AD10N_35 | OUTPUT | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| M19 | dac_dat_o[0] | High Range | IO_L7P_T1_AD2P_35 | OUTPUT | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| M20 | dac_dat_o[1] | High Range | IO_L7N_T1_AD2N_35 | OUTPUT | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| N1 | DDR_cs_n | | PS_DDR_CS_B_502 | BIDIR | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| N2 | DDR_addr[0] | | PS_DDR_A0_502 | BIDIR | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| N3 | DDR_cke | | PS_DDR_CKE_502 | BIDIR | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| N4 | | | GND | GND | | | | | | | 0.0 | | | | | | +| N5 | DDR_odt | | PS_DDR_ODT_502 | BIDIR | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| N6 | | | RSVDVCC3 | Reserved | | | | | | | | | | | | | +| N7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| N9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | +| N11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| N13 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| N14 | | | GND | GND | | | | | | | 0.0 | | | | | | +| N15 | dac_rst_o | High Range | IO_L21P_T3_DQS_AD14P_35 | OUTPUT | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| N16 | dac_sel_o | High Range | IO_L21N_T3_DQS_AD14N_35 | OUTPUT | LVCMOS33 | 35 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| N17 | adc_dat_i[1][5] | High Range | IO_L23P_T3_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| N18 | daisy_p_i[1] | High Range | IO_L13P_T2_MRCC_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| N19 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | +| N20 | adc_clk_o[0] | High Range | IO_L14P_T2_SRCC_34 | OUTPUT | LVCMOS18 | 34 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| P1 | DDR_dq[16] | | PS_DDR_DQ16_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | PULLUP | | | SPLIT | +| P2 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| P3 | DDR_dq[17] | | PS_DDR_DQ17_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | PULLUP | | | SPLIT | +| P4 | DDR_ras_n | | PS_DDR_RAS_B_502 | BIDIR | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| P5 | DDR_cas_n | | PS_DDR_CAS_B_502 | BIDIR | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| P6 | | | PS_DDR_VREF1_502 | PSS IO | | | | | | | | | | | | | +| P7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P8 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P12 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P14 | daisy_p_i[0] | High Range | IO_L6P_T0_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| P15 | dac_pwm_o[2] | High Range | IO_L24P_T3_34 | OUTPUT | LVCMOS18 | 34 | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | +| P16 | adc_dat_i[1][3] | High Range | IO_L24N_T3_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| P17 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P18 | adc_dat_i[1][4] | High Range | IO_L23N_T3_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| P19 | daisy_n_i[1] | High Range | IO_L13N_T2_MRCC_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| P20 | adc_clk_o[1] | High Range | IO_L14N_T2_SRCC_34 | OUTPUT | LVCMOS18 | 34 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| R1 | DDR_dq[19] | | PS_DDR_DQ19_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | PULLUP | | | SPLIT | +| R2 | DDR_dqs_p[2] | | PS_DDR_DQS_P2_502 | BIDIR | DIFF_SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | PULLUP | | | SPLIT | +| R3 | DDR_dq[18] | | PS_DDR_DQ18_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | PULLUP | | | SPLIT | +| R4 | DDR_ba[1] | | PS_DDR_BA1_502 | BIDIR | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| R5 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| R6 | | | RSVDVCC2 | Reserved | | | | | | | | | | | | | +| R7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| R9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| R10 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | +| R11 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | +| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| R13 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| R14 | daisy_n_i[0] | High Range | IO_L6N_T0_VREF_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| R15 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | +| R16 | adc_dat_i[1][1] | High Range | IO_L19P_T3_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| R17 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | +| R18 | adc_dat_i[1][2] | High Range | IO_L20N_T3_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| R19 | adc_dat_i[1][6] | High Range | IO_0_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | +| T1 | DDR_dm[2] | | PS_DDR_DM2_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | PULLUP | | | SPLIT | +| T2 | DDR_dqs_n[2] | | PS_DDR_DQS_N2_502 | BIDIR | DIFF_SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | PULLUP | | | SPLIT | +| T3 | | | GND | GND | | | | | | | 0.0 | | | | | | +| T4 | DDR_dq[20] | | PS_DDR_DQ20_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | PULLUP | | | SPLIT | +| T5 | | | NC | Not Connected | | | | | | | | | | | | | +| T6 | | | RSVDVCC1 | Reserved | | | | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| T8 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | +| T9 | | | NC | Not Connected | | | | | | | | | | | | | +| T10 | dac_pwm_o[0] | High Range | IO_L1N_T0_34 | OUTPUT | LVCMOS18 | 34 | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | +| T11 | dac_pwm_o[1] | High Range | IO_L1P_T0_34 | OUTPUT | LVCMOS18 | 34 | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | +| T12 | daisy_p_o[0] | High Range | IO_L2P_T0_34 | TRISTATE | LVCMOS18 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| T13 | | | GND | GND | | | | | | | 0.0 | | | | | | +| T14 | adc_dat_i[0][11] | High Range | IO_L5P_T0_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| T15 | adc_dat_i[0][12] | High Range | IO_L5N_T0_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| T16 | adc_dat_i[0][14] | High Range | IO_L9P_T1_DQS_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| T17 | adc_dat_i[1][0] | High Range | IO_L20P_T3_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| T18 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | +| T19 | adc_dat_i[1][8] | High Range | IO_25_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| T20 | adc_dat_i[1][7] | High Range | IO_L15P_T2_DQS_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| U1 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| U2 | DDR_dq[22] | | PS_DDR_DQ22_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | PULLUP | | | SPLIT | +| U3 | DDR_dq[23] | | PS_DDR_DQ23_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | PULLUP | | | SPLIT | +| U4 | DDR_dq[21] | | PS_DDR_DQ21_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | PULLUP | | | SPLIT | +| U5 | | | NC | Not Connected | | | | | | | | | | | | | +| U6 | | | GND | GND | | | | | | | 0.0 | | | | | | +| U7 | | | NC | Not Connected | | | | | | | | | | | | | +| U8 | | | NC | Not Connected | | | | | | | | | | | | | +| U9 | | | NC | Not Connected | | | | | | | | | | | | | +| U10 | | | NC | Not Connected | | | | | | | | | | | | | +| U11 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | +| U12 | daisy_n_o[0] | High Range | IO_L2N_T0_34 | TRISTATE | LVCMOS18 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| U13 | dac_pwm_o[3] | High Range | IO_L3P_T0_DQS_PUDC_B_34 | OUTPUT | LVCMOS18 | 34 | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | +| U14 | daisy_p_o[1] | High Range | IO_L11P_T1_SRCC_34 | OUTPUT | LVCMOS18 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| U15 | daisy_n_o[1] | High Range | IO_L11N_T1_SRCC_34 | OUTPUT | LVCMOS18 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| U16 | | | GND | GND | | | | | | | 0.0 | | | | | | +| U17 | adc_dat_i[0][1] | High Range | IO_L9N_T1_DQS_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| U18 | adc_clk_i[1] | High Range | IO_L12P_T1_MRCC_34 | INPUT | DIFF_HSTL_I_18 | 34 | | | | NONE | | FIXED | | | | NONE | +| U19 | adc_clk_i[0] | High Range | IO_L12N_T1_MRCC_34 | INPUT | DIFF_HSTL_I_18 | 34 | | | | NONE | | FIXED | | | | NONE | +| U20 | adc_dat_i[1][9] | High Range | IO_L15N_T2_DQS_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| V1 | DDR_dq[24] | | PS_DDR_DQ24_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | PULLUP | | | SPLIT | +| V2 | DDR_dq[30] | | PS_DDR_DQ30_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | PULLUP | | | SPLIT | +| V3 | DDR_dq[31] | | PS_DDR_DQ31_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | PULLUP | | | SPLIT | +| V4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| V5 | | | NC | Not Connected | | | | | | | | | | | | | +| V6 | | | NC | Not Connected | | | | | | | | | | | | | +| V7 | | | NC | Not Connected | | | | | | | | | | | | | +| V8 | | | NC | Not Connected | | | | | | | | | | | | | +| V9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| V10 | | | NC | Not Connected | | | | | | | | | | | | | +| V11 | | | NC | Not Connected | | | | | | | | | | | | | +| V12 | adc_dat_i[0][9] | High Range | IO_L4P_T0_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| V13 | adc_dat_i[0][10] | High Range | IO_L3N_T0_DQS_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| V14 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | +| V15 | adc_dat_i[0][13] | High Range | IO_L10P_T1_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| V16 | adc_dat_i[0][15] | High Range | IO_L18P_T2_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| V17 | adc_dat_i[0][0] | High Range | IO_L21P_T3_DQS_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| V18 | adc_cdcs_o | High Range | IO_L21N_T3_DQS_34 | OUTPUT | LVCMOS18 | 34 | 8 | FAST | | NONE | | FIXED | | | | NONE | +| V19 | | | GND | GND | | | | | | | 0.0 | | | | | | +| V20 | adc_dat_i[1][10] | High Range | IO_L16P_T2_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| W1 | DDR_dq[26] | | PS_DDR_DQ26_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | PULLUP | | | SPLIT | +| W2 | | | GND | GND | | | | | | | 0.0 | | | | | | +| W3 | DDR_dq[29] | | PS_DDR_DQ29_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | PULLUP | | | SPLIT | +| W4 | DDR_dqs_n[3] | | PS_DDR_DQS_N3_502 | BIDIR | DIFF_SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | PULLUP | | | SPLIT | +| W5 | DDR_dqs_p[3] | | PS_DDR_DQS_P3_502 | BIDIR | DIFF_SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | PULLUP | | | SPLIT | +| W6 | | | NC | Not Connected | | | | | | | | | | | | | +| W7 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | +| W8 | | | NC | Not Connected | | | | | | | | | | | | | +| W9 | | | NC | Not Connected | | | | | | | | | | | | | +| W10 | | | NC | Not Connected | | | | | | | | | | | | | +| W11 | | | NC | Not Connected | | | | | | | | | | | | | +| W12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| W13 | adc_dat_i[0][8] | High Range | IO_L4N_T0_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| W14 | adc_dat_i[0][6] | High Range | IO_L8P_T1_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| W15 | adc_dat_i[0][5] | High Range | IO_L10N_T1_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| W16 | adc_dat_i[0][3] | High Range | IO_L18N_T2_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| W17 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | +| W18 | adc_dat_i[1][14] | High Range | IO_L22P_T3_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| W19 | adc_dat_i[1][12] | High Range | IO_L22N_T3_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| W20 | adc_dat_i[1][11] | High Range | IO_L16N_T2_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| Y1 | DDR_dm[3] | | PS_DDR_DM3_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | PULLUP | | | SPLIT | +| Y2 | DDR_dq[28] | | PS_DDR_DQ28_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | PULLUP | | | SPLIT | +| Y3 | DDR_dq[25] | | PS_DDR_DQ25_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | PULLUP | | | SPLIT | +| Y4 | DDR_dq[27] | | PS_DDR_DQ27_502 | BIDIR | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | PULLUP | | | SPLIT | +| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| Y6 | | | NC | Not Connected | | | | | | | | | | | | | +| Y7 | | | NC | Not Connected | | | | | | | | | | | | | +| Y8 | | | NC | Not Connected | | | | | | | | | | | | | +| Y9 | | | NC | Not Connected | | | | | | | | | | | | | +| Y10 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | +| Y11 | | | NC | Not Connected | | | | | | | | | | | | | +| Y12 | | | NC | Not Connected | | | | | | | | | | | | | +| Y13 | | | NC | Not Connected | | | | | | | | | | | | | +| Y14 | adc_dat_i[0][7] | High Range | IO_L8N_T1_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | +| Y16 | adc_dat_i[0][4] | High Range | IO_L7P_T1_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| Y17 | adc_dat_i[0][2] | High Range | IO_L7N_T1_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| Y18 | adc_dat_i[1][15] | High Range | IO_L17P_T2_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| Y19 | adc_dat_i[1][13] | High Range | IO_L17N_T2_34 | INPUT | LVCMOS18 | 34 | | | | NONE | | FIXED | | | | NONE | +| Y20 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | ++------------+-------------------+------------+-------------------------+---------------+-------------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + +######################### +modifying PIN constraints +######################### + +To modify PIN constraints eddit the +'./fpga/sdc/red_pitaya.xdc' +file. + +For more details please see the following link: +https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0004-vivado-applying-design-constraints-hub.html diff --git a/doc/developerGuide/scpi/scpi.rst b/doc/developerGuide/scpi/scpi.rst index 419573245..f29034094 100644 --- a/doc/developerGuide/scpi/scpi.rst +++ b/doc/developerGuide/scpi/scpi.rst @@ -16,7 +16,7 @@ the next dependencies have to be installed: .. code-block:: shell-session - sudo apt install pyton3-pip + sudo apt install python3-pip pip3 install --upgrade pip sudo pip3 install pyvisa sudo pip3 install pyvisa-py @@ -71,7 +71,7 @@ After cloning the Git repository and changing into the directory do: .. code-block:: shell-session - meson builddir --prefix /opt/redpitaya + meson builddir --prefix /opt/redpitaya --buildtype release cd builddir ninja @@ -82,6 +82,13 @@ The server can be installed using the nect commands: rw ninja install +Prerequisite for running mercury based scpi server is to apply mercury dtbo. + +.. code-block:: shell-session + + sh /opt/redpitaya/sbin/overlay.sh mercury + + And run as a systemd service: .. code-block:: shell-session diff --git a/doc/developerGuide/software.rst b/doc/developerGuide/software.rst index 09f2ca922..8e5e2728f 100644 --- a/doc/developerGuide/software.rst +++ b/doc/developerGuide/software.rst @@ -16,5 +16,6 @@ Software ../../fpga/fpga comC scpi/scpi + gpio/gpio software/manualApps.rst - + diff --git a/doc/developerGuide/software/clt.rst b/doc/developerGuide/software/clt.rst index d6fcb24fd..6c9c77ce9 100644 --- a/doc/developerGuide/software/clt.rst +++ b/doc/developerGuide/software/clt.rst @@ -76,6 +76,9 @@ Example (2 Vpp square wave signal with 1 MHz on channel 1): For correct operation of the generate tool, it is mandatory that the correct FPGA image is loaded. Please note, the some application can change the FPGA image loaded. To load the FPGA image open a terminal on the RedPitaya and execute the following command: + + .. code-block:: shell-session + cat /opt/redpitaya/fpga/fpga_0.94.bit > /dev/xdevcfg @@ -129,6 +132,9 @@ Example (acquire 1024 samples with decimation 8): For correct operation of the acquire tool, it is mandatory that the correct FPGA image is loaded. Please note, the some application can change the FPGA image loaded. To load the FPGA image open a terminal on the RedPitaya and execute the following command: + + .. code-block:: shell-session + cat /opt/redpitaya/fpga/fpga_0.94.bit > /dev/xdevcfg =================== diff --git a/doc/developerGuide/software/webexamples/addLEDbut.rst b/doc/developerGuide/software/webexamples/addLEDbut.rst index 2bc8eaf24..e0e157f9e 100644 --- a/doc/developerGuide/software/webexamples/addLEDbut.rst +++ b/doc/developerGuide/software/webexamples/addLEDbut.rst @@ -7,6 +7,13 @@ Add a button to control LED You can control Red Pitaya's peripherals via Web UI. In this tutorial will be shown how to turn on and off LED on Red Pitaya using parameters. +.. note:: + + Requierment for manipulating leds using api is to first load fpga_0.94.bit fpga bitstream image. + That can be done using next command line instruction: + "cat /opt/redpitaya/fpga/fpga_0.94.bit > /dev/xdevcfg" + + ****** Web UI ****** diff --git a/doc/developerGuide/tft/TFT.rst b/doc/developerGuide/tft/TFT.rst index d138672ea..cc278d6c4 100644 --- a/doc/developerGuide/tft/TFT.rst +++ b/doc/developerGuide/tft/TFT.rst @@ -34,10 +34,12 @@ It is possible to reconfigure **Zynq** MIO signals using the ``pinctrl`` kernel This TFT display setup takes advantage of this by repurposing SPI, I2C and UART signals on the :ref:`E2 ` connector as SPI and GPIO signals which are required by the TFT display interface. -.. |tft-E2| replace:: ``tft-E2.dtsi`` -.. _tft-E2: /fpga/dts/tft/tft-E2.dtsi +.. .. |tft-E2| replace:: ``tft-E2.dtsi`` +.. .. _tft-E2: /fpga/dts/tft/tft-E2.dtsi -The reconfiguration is performed by including the |tft-E2|_ device tree. +.. The reconfiguration is performed by including the |tft-E2|_ device tree. + +The reconfiguration is performed by including the :download:`tft-E2 <../../../fpga/dts/tft/tft-E2.dtsi>` device tree. +-----------------+-----+----------+--------+--------+----------+-----+-------------------+ | SPI TFT+touch | MIO | function | pin | pin | function | MIO | SPI TFT+touch | @@ -112,12 +114,10 @@ The maximum clock speed for this SPI controller is 50MHz. Software setup ************** -.. |tft.sh| replace:: ``tft.sh`` -.. _tft.sh: /OS/debian/tft.sh Instructions for starting XFCE on the TFT display. A script which can be used to generate an image with full support -is available on GitHub |tft.sh|_. +is available on GitHub :download:`tft.sh <../../../OS/debian/tft.sh>`. A set of Ubuntu/Debian packages should be installed: @@ -129,12 +129,8 @@ A set of Ubuntu/Debian packages should be installed: xfce4-terminal thunar gnome-icon-theme \ xserver-xorg xinit xserver-xorg-video-fbdev -.. |99-fbdev.conf| replace:: ``/usr/share/X11/xorg.conf.d/99-fbdev.conf`` -.. _99-fbdev.conf: /OS/debian/overlay/usr/share/X11/xorg.conf.d/99-fbdev.conf - -An X11 configuration file should be added to the system |99-fbdev.conf|_: -.. literalinclude:: /OS/debian/overlay/etc/udev/rules.d/95-ads7846.rules +An X11 configuration file should be added to the system :download:`99-fbdev.conf <../../../OS/debian/overlay/usr/share/X11/xorg.conf.d/99-fbdev.conf>`. Over SSH start the X server: @@ -209,12 +205,9 @@ to +5V VCC, this can be done with a simple jumper between the two display connector pins. Otherwise it would be possible to repurpose a LED on Red Pitaya. -.. |95-ads7846.rules| replace:: ``/etc/udev/rules.d/95-ads7846.rules`` -.. _95-ads7846.rules: /OS/debian/overlay/etc/udev/rules.d/95-ads7846.rules -The |95-ads7846.rules|_ UDEV rule will create a symbolik link ``/dev/input/touchscreen``. - -.. literalinclude:: /OS/debian/overlay/etc/udev/rules.d/95-ads7846.rules +The :download:`95-ads7846.rules <../../../OS/debian/overlay/etc/udev/rules.d/95-ads7846.rules>`> UDEV rule will create a +symbolik link ``/dev/input/touchscreen``. =================== Adafruit PiTFT 3.5" @@ -288,19 +281,11 @@ Male connector pinout based on the |PiTFT-35|_ | +5V | ``2`` | ``1`` | +3.3V | +-------------------+--------+--------+-------------------+ -.. |95-stmpe.rules| replace:: ``/etc/udev/rules.d/95-stmpe.rules`` -.. _95-stmpe.rules: /OS/debian/overlay/etc/udev/rules.d/95-stmpe.rules - -The |95-stmpe.rules|_ UDEV rule will create a symbolic link ``/dev/input/touchscreen``. - -.. literalinclude:: /OS/debian/overlay/etc/udev/rules.d/95-stmpe.rules - -.. |99-calibration.conf| replace:: ``/etc/X11/xorg.conf.d/99-calibration.conf`` -.. _99-calibration.conf: /OS/debian/overlay/etc/X11/xorg.conf.d/99-calibration.conf - -A calibration file should be added to the system |99-calibration.conf|_: +The :download:`95-stmpe.rules <../../../OS/debian/overlay/etc/udev/rules.d/95-stmpe.rules>` UDEV rule will create a +symbolic link ``/dev/input/touchscreen``. -.. literalinclude:: ../OS/debian/overlay/usr/share/X11/xorg.conf.d/99-fbdev.conf +A calibration file should be added to the system +:download:`99-calibration.conf <../../../OS/debian/overlay/etc/X11/xorg.conf.d/99-calibration.conf>` ------------- Block diagram diff --git a/doc/developerGuide/uio/uio.rst b/doc/developerGuide/uio/uio.rst new file mode 100644 index 000000000..050c7175b --- /dev/null +++ b/doc/developerGuide/uio/uio.rst @@ -0,0 +1,200 @@ +.. _UIO: + +### +UIO +### + +Userspace input output or `UIO `_ +Enables writing hardware drivers in user space with a small kernel module providing +memory space mapping and interrupt support. + +Although dedicated UIO kernel drivers can be written, +we are using a generic driver named ``uio_pdrv_genirq``. +Since this driver is actually intended as an example on how to write UIO drivers, +it is missing the ``compatible`` identifiers used by device tree nodes. +This issues can be solved by providing a compatible string as +a kernel boot argument ``uio_pdrv_genirq.of_id="generic-uio"``. +We do this in :download:`u-boot.script <../../../patches/u-boot/u-boot.script>`. + +**************** +Device tree node +**************** + +A new UIO device is added by providing a device tree node describing it. + +The next example describes an arbitrary signal generator: + +.. code-block:: c + + gen0: gen0@40040000 { + compatible = "generic-uio"; + reg = <0x40040000 0x01000>, + <0x40050000 0x10000>; // 2**14 * sizeof(int32_t), TODO: int16_t + reg-names = "regset", "buffer"; + interrupt-parent = <&axi_intc_0>; + interrupts = <0 1>; + }; + +The ``compatible`` attribute must use the same driver name as provided as kernel argument. + +The ``reg`` attribute must contain one or more address space windows. +Each window is defined by the base address and size. In our case +the window is inside the address space used by the AXI-GP0 port on the ZYNQ device. +In the given examples two windows are given, the first for the register set, +the second for the buffer. The ``reg-names`` attribute provides window names. + +Optionally an interrupt can be provided. ``interrupt-parent`` links +to the interrupt controller the signals is connected to. +In argument ``interrupts`` the first value specifis the index of the interrupt signal +on the connected interrupt controller, the cecond value is interrupt type. + +**** +UDEV +**** + +The Linux kernel will index each UIO device in the order it processed it. +So devices like ``/dev/uio0``, ``/dev/uio1``, ... will be present on the system. +Since this names depend on the loading order, and can change if new devices are added, +an `UDEV configuration file `_ +can be used to give each device a symbolink link, containing the name specified in the device tree. + +.. code-block:: c + + SUBSYSTEM=="uio", SYMLINK+="uio/%s{name}", GROUP="uio" + +.. code-block:: shell-session + + # ll /dev/uio + total 0 + drwxr-xr-x 2 root root 280 Sep 18 10:28 ./ + drwxr-xr-x 11 root root 3240 Sep 18 10:28 ../ + lrwxrwxrwx 1 root root 7 Sep 14 08:52 api -> ../uio1 + lrwxrwxrwx 1 root root 7 Sep 18 10:28 gen0 -> ../uio6 + lrwxrwxrwx 1 root root 7 Sep 18 10:28 gen1 -> ../uio7 + +Additional ``sysfs`` nodes provide details on the given device: + +.. code-block:: shell-session + + # find /sys/devices/soc0/amba_pl/40040000.gen0 + /sys/devices/soc0/amba_pl/40040000.gen0 + /sys/devices/soc0/amba_pl/40040000.gen0/subsystem + /sys/devices/soc0/amba_pl/40040000.gen0/driver + /sys/devices/soc0/amba_pl/40040000.gen0/uio + /sys/devices/soc0/amba_pl/40040000.gen0/uio/uio6 + /sys/devices/soc0/amba_pl/40040000.gen0/uio/uio6/version + /sys/devices/soc0/amba_pl/40040000.gen0/uio/uio6/device + /sys/devices/soc0/amba_pl/40040000.gen0/uio/uio6/event + /sys/devices/soc0/amba_pl/40040000.gen0/uio/uio6/subsystem + /sys/devices/soc0/amba_pl/40040000.gen0/uio/uio6/power + /sys/devices/soc0/amba_pl/40040000.gen0/uio/uio6/power/runtime_suspended_time + /sys/devices/soc0/amba_pl/40040000.gen0/uio/uio6/power/autosuspend_delay_ms + /sys/devices/soc0/amba_pl/40040000.gen0/uio/uio6/power/runtime_active_time + /sys/devices/soc0/amba_pl/40040000.gen0/uio/uio6/power/control + /sys/devices/soc0/amba_pl/40040000.gen0/uio/uio6/power/runtime_status + /sys/devices/soc0/amba_pl/40040000.gen0/uio/uio6/maps + /sys/devices/soc0/amba_pl/40040000.gen0/uio/uio6/maps/map0 + /sys/devices/soc0/amba_pl/40040000.gen0/uio/uio6/maps/map0/offset + /sys/devices/soc0/amba_pl/40040000.gen0/uio/uio6/maps/map0/size + /sys/devices/soc0/amba_pl/40040000.gen0/uio/uio6/maps/map0/name + /sys/devices/soc0/amba_pl/40040000.gen0/uio/uio6/maps/map0/addr + /sys/devices/soc0/amba_pl/40040000.gen0/uio/uio6/maps/map1 + /sys/devices/soc0/amba_pl/40040000.gen0/uio/uio6/maps/map1/offset + /sys/devices/soc0/amba_pl/40040000.gen0/uio/uio6/maps/map1/size + /sys/devices/soc0/amba_pl/40040000.gen0/uio/uio6/maps/map1/name + /sys/devices/soc0/amba_pl/40040000.gen0/uio/uio6/maps/map1/addr + /sys/devices/soc0/amba_pl/40040000.gen0/uio/uio6/dev + /sys/devices/soc0/amba_pl/40040000.gen0/uio/uio6/uevent + /sys/devices/soc0/amba_pl/40040000.gen0/uio/uio6/name + /sys/devices/soc0/amba_pl/40040000.gen0/power + /sys/devices/soc0/amba_pl/40040000.gen0/power/runtime_suspended_time + /sys/devices/soc0/amba_pl/40040000.gen0/power/autosuspend_delay_ms + /sys/devices/soc0/amba_pl/40040000.gen0/power/runtime_active_time + /sys/devices/soc0/amba_pl/40040000.gen0/power/control + /sys/devices/soc0/amba_pl/40040000.gen0/power/runtime_status + /sys/devices/soc0/amba_pl/40040000.gen0/driver_override + /sys/devices/soc0/amba_pl/40040000.gen0/modalias + /sys/devices/soc0/amba_pl/40040000.gen0/uevent + /sys/devices/soc0/amba_pl/40040000.gen0/of_node + +Memory window settings provided in the device tree can be read from +``maps/map0`` and ``maps/map1`` nodes. + +***************** +User space driver +***************** + +Access to UIO memory windows is similar to mapping ``/dev/mem``. +The device ``/dev/uio/gen0`` is opened and ``mmap`` is used to +map the physical memory window into virtual address space. + +.. code-block:: C + + #include + #include + #include + #include + + static int fd = 0; + uint32_t *regset; + int16_t *buffer; + + int uio_open(int *fd, uint32_t **regset, int16_t **buffer) { + size_t offset; + size_t size; + + # open UIO device file + if ((*fd = open("/dev/uio/gen0", O_RDWR | O_SYNC)) == -1) { + return -1; + } + // map regset memory window + offset = 0x0; + size = 0x1000; + *regset = mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED, *fd, 0); + if (regset == (void *) -1) { + return -1; + } + // map buffer memory window + // each consecutive memory window reqiures an offset of (index * PAGESIZE) + offset = sysconf(_SC_PAGESIZE); + size = 0x10000; + *buffer = mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED, *fd, offset); + if (buffer == (void *) -1) { + return -1; + } + return 0; + } + + int uio_close(int * fd, uint32_t **regset, uint16_t **buffer) { + size_t size; + + size = 0x1000; + if (munmap(*regset, size) < 0) { + return -1; + } + size = 0x10000; + if (munmap(*buffer, size) < 0) { + return -1; + } + if (close(*fd) < 0) { + return -1; + } + return 0; + } + +If regset is cast onto a structure containing 32bit registers, +registers can be read or written to using elements of this structure. + +******** +Examples +******** + +The **mercury** FPGA image and related user space code is using UIO extensively. + +Each HW module inside the FPGA is listed as an UIO device in the device tree. + +/fpga/prj/mercury/dts/fpga.dtso + +A Python API is provided: + +https://github.com/RedPitaya/jupyter/blob/master/redpitaya/drv/uio.py diff --git a/doc/quickStart/SDcard/SDcard.rst b/doc/quickStart/SDcard/SDcard.rst index 6ef423173..79743c7c1 100644 --- a/doc/quickStart/SDcard/SDcard.rst +++ b/doc/quickStart/SDcard/SDcard.rst @@ -13,7 +13,8 @@ The next procedure will create a clean SD card. #. Download the Red Pitaya SD card image: - `Latest Stable `_ - `CHANGELOG `_ - - `Beta (including STEMlab SDR transceiver app) `_. + +.. - `Beta (including STEMlab SDR transceiver app) `_. .. image:: microSDcard-RP.png :width: 10% diff --git a/doc/quickStart/connect/connect.rst b/doc/quickStart/connect/connect.rst index 2f5256080..311d3ed57 100644 --- a/doc/quickStart/connect/connect.rst +++ b/doc/quickStart/connect/connect.rst @@ -216,6 +216,11 @@ still available over the WiFi network i.e WiFi IP address. .. note:: WiFi networks are generally not robust and the full performances of the Red Pitaya application can be affected. + +.. note:: + + When using Raspberry Pi WiFi dongle, an issue of the dongle not being detected can arise. To mitigate, detatch + the power cable from Red Pitaya and wait for about a minute before powering up the Red Pitaya again. ================= Access Point mode diff --git a/doc/quickStart/troubleshooting/troubleshooting.rst b/doc/quickStart/troubleshooting/troubleshooting.rst index 12fadc640..debfc9c2b 100644 --- a/doc/quickStart/troubleshooting/troubleshooting.rst +++ b/doc/quickStart/troubleshooting/troubleshooting.rst @@ -92,6 +92,14 @@ please check the following: For full preformence the wired connection is preffered. +********************************* +Rassbary Pi Wi-Fi is not detected +********************************* + + In some circumstances a Rassbary Pi Wi-Fi is not detected by Red Pitaya. To mitigate, detatch + the power cable from Red Pitaya and wait for about a minute before powering up the Red Pitaya again. + On the next boot the Rassbary Pi Wi-Fi should be detected normally. + ### FAQ ### diff --git a/doc/security.rst b/doc/security.rst new file mode 100644 index 000000000..2cbb82184 --- /dev/null +++ b/doc/security.rst @@ -0,0 +1,66 @@ +###################### +General considerations +###################### + +#. follow best practices +#. no default passwords +#. no hardcoded passwords +#. user settings similar to Ubuntu (use ``sudo``, disabled ``root`` user) +#. avoid running applications as root +#. HW access requires group membership + +Main issues: +#. backward compatibility +#. Fat32 does not provide necessary file attributes + +### +UIO +### + +http://elinux.org/images/b/b0/Uio080417celfelc08.pdf +https://lwn.net/Articles/232575/ + + +########################### +Hardware access permissions +########################### + +Debugging UDEV rules + +.. code-block:: shell-session + + udevadm info -a /dev/xdevcfg + udevadm info -a /dev/uio0 + udevadm info -a /sys/devices/soc0/led-user/leds/led0 + udevadm info -a /sys/devices/soc0/amba/e000a000.gpio/gpio + udevadm info -a /dev/spidev1.0 + udevadm info -a /dev/i2c-0 + udevadm info -a /sys/bus/i2c/devices/0-0050 + udevadm info -a /dev/ttyPS1 + udevadm info -a /dev/iio\:device0 + udevadm info -a /dev/iio\:device1 + udevadm info -a /dev/rprx + +##### +Users +##### + +===================================== +System users for running applications +===================================== + +========================== +``redpitaya`` default user +========================== + +============= +``root`` user +============= + +Aftert the first boot the ``root`` user does not have a password +and is therefore disabled. +Setting ``root`` user password enables access to the account: + +.. code-block:: shell-session + + $ sudo passwd root diff --git a/fpga/Makefile b/fpga/Makefile index 6f5511c76..82d275cf4 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -31,6 +31,7 @@ all: $(FPGA_BIT) $(FSBL_ELF) $(DEVICE_TREE) # TODO: clean should go into each project clean: rm -rf out .Xil .srcs sdk project + rm -rf prj/$(PRJ)/out prj/$(PRJ)/.Xil prj/$(PRJ)/.srcs prj/$(PRJ)/sdk prj/$(PRJ)/project project: vivado -source red_pitaya_vivado_project.tcl -tclargs $(PRJ) diff --git a/fpga/dts/clkc.dtsi b/fpga/dts/clkc.dtsi index e0473c180..a8b32cf66 100644 --- a/fpga/dts/clkc.dtsi +++ b/fpga/dts/clkc.dtsi @@ -1,6 +1,6 @@ /* * PL clock configuration -*/ + */ &clkc { fclk-enable = <0xf>; diff --git a/fpga/dts/ethernet.dtsi b/fpga/dts/ethernet.dtsi index 61752d6d3..af9ec2b2c 100644 --- a/fpga/dts/ethernet.dtsi +++ b/fpga/dts/ethernet.dtsi @@ -1,12 +1,10 @@ /* * Lantiq ethernet PHY -*/ + */ &gem0 { phy-handle = <ðernet_0_mdio>; - ethernet_0_mdio: mdio@1 { - compatible = "lantiq,phy11g"; - device_type = "ethernet-phy"; + ethernet_0_mdio: ethernet_0_mdio@1 { reg = <1>; }; }; diff --git a/fpga/dts/gpio.dtsi b/fpga/dts/gpio.dtsi new file mode 100644 index 000000000..66ead9c15 --- /dev/null +++ b/fpga/dts/gpio.dtsi @@ -0,0 +1,86 @@ +/* + * GPIO names + */ + +&gpio0 { + gpio-line-names = + "MIO0 (LED 8)", + "MIO1 (QSPI_CS#)", + "MIO2 (QSPI_IO0)", + "MIO3 (QSPI_IO1)", + "MIO4 (QSPI_IO2)", + "MIO5 (QSPI_IO3)", + "MIO6 (QSPI_CLK)", + "MIO7 (LED 9)", + "MIO8 (UART1_TX)", + "MIO9 (UART1_RX)", + "MIO10 (SPI1_MOSI)", + "MIO11 (SPI1_MISO)", + "MIO12 (SPI1_CLK)", + "MIO13 (SPI1_CS#)", + "MIO14 (UART0_RX)", + "MIO15 (UART0_TX)", + "MIO16 (ETH_TXCLK)", + "MIO17 (ETH_TXD0)", + "MIO18 (ETH_TXD1)", + "MIO19 (ETH_TXD2)", + "MIO20 (ETH_TXD3)", + "MIO21 (ETH_TXCTL)", + "MIO22 (ETH_RXCLK)", + "MIO23 (ETH_RXD0)", + "MIO24 (ETH_RXD1)", + "MIO25 (ETH_RXD2)", + "MIO26 (ETH_RXD3)", + "MIO27 (ETH_RXCTL)", + "MIO28 (USB_D4)", + "MIO29 (USB_DIR)", + "MIO30 (USB_STP)", + "MIO31 (USB_NXT)", + "MIO32 (USB_D0)", + "MIO33 (USB_D1)", + "MIO34 (USB_D2)", + "MIO35 (USB_D3)", + "MIO36 (USB_CLK)", + "MIO37 (USB_D5)", + "MIO38 (USB_D6)", + "MIO39 (USB_D7)", + "MIO40 (SDIO_CLK)", + "MIO41 (SDIO_CMD)", + "MIO42 (SDIO_DAT0)", + "MIO43 (SDIO_DAT1)", + "MIO44 (SDIO_DAT2)", + "MIO45 (SDIO_DAT3)", + "MIO46 (SDIO_SDDET)", + "MIO47 (SDIO_WP)", + "MIO48 (USB_RESB)", + "MIO49 (USB_FLG)", + "MIO50 (I2C0_SDA)", + "MIO51 (I2C0_SCL)", + "MIO52 (ETH_MDC)", + "MIO53 (ETH_MDIO)", + "EMIO0 (LED 0)", + "EMIO1 (LED 1)", + "EMIO2 (LED 2)", + "EMIO3 (LED 3)", + "EMIO4 (LED 4)", + "EMIO5 (LED 5)", + "EMIO6 (LED 6)", + "EMIO7 (LED 7)", + "EMIO8 (GPIO 0)", + "EMIO9 (GPIO 1)", + "EMIO10 (GPIO 2)", + "EMIO11 (GPIO 3)", + "EMIO12 (GPIO 4)", + "EMIO13 (GPIO 5)", + "EMIO14 (GPIO 6)", + "EMIO15 (GPIO 7)", + "EMIO16 (GPIO 8)", + "EMIO17 (GPIO 9)", + "EMIO18 (GPIO 10)", + "EMIO19 (GPIO 11)", + "EMIO20 (GPIO 12)", + "EMIO21 (GPIO 13)", + "EMIO22 (GPIO 14)", + "EMIO23 (GPIO 15)", + "EMIO24 (GPIO 16)"; +}; \ No newline at end of file diff --git a/fpga/dts/i2c0.dtsi b/fpga/dts/i2c0.dtsi index 10a7c6a47..058966f53 100644 --- a/fpga/dts/i2c0.dtsi +++ b/fpga/dts/i2c0.dtsi @@ -1,6 +1,6 @@ /* * list devices on I2C bus -*/ + */ &i2c0 { eeprom@50 { @@ -8,4 +8,4 @@ reg = <0x50>; pagesize = <32>; }; -}; +}; \ No newline at end of file diff --git a/fpga/dts/led-system.dtsi b/fpga/dts/led-system.dtsi index e5ba0a846..40ba18283 100644 --- a/fpga/dts/led-system.dtsi +++ b/fpga/dts/led-system.dtsi @@ -2,7 +2,7 @@ * stystem LED are given a fixed function * yellow LED - SD card access * red LED - CPU heartbeat -*/ + */ / { led-system { diff --git a/fpga/dts/led-user.dtsi b/fpga/dts/led-user.dtsi index c0721cb0e..643b11182 100644 --- a/fpga/dts/led-user.dtsi +++ b/fpga/dts/led-user.dtsi @@ -1,6 +1,6 @@ /* * user LED -*/ + */ / { led-user { diff --git a/fpga/dts/memory.dtsi b/fpga/dts/memory.dtsi index c8b127a25..24a476ef4 100644 --- a/fpga/dts/memory.dtsi +++ b/fpga/dts/memory.dtsi @@ -1,6 +1,6 @@ /* * define memory for DMA pool -*/ + */ / { reserved-memory { diff --git a/fpga/dts/system.dtsi b/fpga/dts/redpitaya.dtsi similarity index 91% rename from fpga/dts/system.dtsi rename to fpga/dts/redpitaya.dtsi index 094d2ebbd..e53ea7910 100644 --- a/fpga/dts/system.dtsi +++ b/fpga/dts/redpitaya.dtsi @@ -10,5 +10,4 @@ /include/ "clkc.dtsi" /include/ "xadc.dtsi" /include/ "led-system.dtsi" -/include/ "uio-ps2pl.dtsi" /include/ "uio-api.dtsi" diff --git a/fpga/dts/uio-ps2pl.dtsi b/fpga/dts/uio-ps2pl.dtsi deleted file mode 100644 index 970f6f619..000000000 --- a/fpga/dts/uio-ps2pl.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Add UIO peripherals - * NOTE: although multiple IRQ are listed here only one will work - */ - -&amba_pl { - ps2pl: ps2pl@40000000 { - compatible = "generic-uio"; - reg = <0x40000000 0x40000000>, - <0x80000000 0x40000000>; - reg-names = "m_axi_gp0", "m_axi_gp1"; - interrupts = <0 68 4>, <0 67 4>, <0 66 4>, <0 65 4>, <0 64 4>, <0 63 4>, <0 62 4>, <0 61 4>, - <0 91 4>, <0 90 4>, <0 89 4>, <0 88 4>, <0 87 4>, <0 86 4>, <0 85 4>, <0 84 4>; - interrupt-names = "irqf2p7", "irqf2p6", "irqf2p5", "irqf2p4", "irqf2p3", "irqf2p2", "irqf2p1", "irqf2p0", - "irqf2p15", "irqf2p14", "irqf2p13", "irqf2p12", "irqf2p11", "irqf2p10", "irqf2p9", "irqf2p8"; - interrupt-parent = <&intc>; - }; -}; diff --git a/fpga/dts/uio.dtsi b/fpga/dts/uio.dtsi deleted file mode 100644 index 622176594..000000000 --- a/fpga/dts/uio.dtsi +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Add UIO peripherals - */ - -&amba_pl { - id: id@40000000 { - compatible = "generic-uio"; - reg = <0x40000000 0x10000>; - status = "disabled"; - }; - muxctl: muxctl@40040000 { - compatible = "generic-uio"; - reg = <0x40040000 0x10000>; - status = "disabled"; - }; - calib: calib@40100000 { - compatible = "generic-uio"; - reg = <0x40100000 0x10000>; - status = "disabled"; - }; - pdm: pdm@40140000 { - compatible = "generic-uio"; - reg = <0x40140000 0x10000>; - status = "disabled"; - }; - pwm: pwm@40180000 { - compatible = "generic-uio"; - reg = <0x40180000 0x10000>; - status = "disabled"; - }; - asg0: asg0@401c0000 { - compatible = "generic-uio"; - reg = <0x401c0000 0x40000>; - status = "disabled"; - }; - asg1: asg1@40200000 { - compatible = "generic-uio"; - reg = <0x40200000 0x40000>; - status = "disabled"; - }; - scope0: scope0@40240000 { - compatible = "generic-uio"; - reg = <0x40240000 0x10000>; - status = "disabled"; - }; - scope1: scope1@40280000 { - compatible = "generic-uio"; - reg = <0x40280000 0x10000>; - status = "disabled"; - }; - lg: lg@402c0000 { - compatible = "generic-uio"; - reg = <0x402c0000 0x40000>; - status = "disabled"; - }; - la: la@40300000 { - compatible = "generic-uio"; - reg = <0x40300000 0x10000>; - status = "disabled"; - }; -}; diff --git a/fpga/fpga.rst b/fpga/fpga.rst index 668782526..69f1c5a09 100644 --- a/fpga/fpga.rst +++ b/fpga/fpga.rst @@ -14,7 +14,7 @@ Install libraries: # apt-get install libxft2 libxft2:i386 lib32ncurses5 -2. *Xilinx Vivado 2017.1 (including SDK)* +2. *Xilinx Vivado 2017.2 (including SDK)* ******************* Directory structure @@ -25,7 +25,7 @@ Common code for all projects is placed directly into the ``fpga`` directory. Com Project specific code is placed inside the ``fpga/prj/name/`` directories and is similarly organized as common code. .. |ug895| replace:: Vivado System-Level Design Entry -.. _ug895: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug895-vivado-system-level-design-entry.pdf +.. _ug895: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug895-vivado-system-level-design-entry.pdf .. tabularcolumns:: |p{30mm}|p{120mm}| @@ -107,7 +107,7 @@ If Xilinx Vivado is installed at the default location, then the next command wil .. code-block:: shell-session - $ . /opt/Xilinx/Vivado/2017.1/settings64.sh + $ . /opt/Xilinx/Vivado/2017.2/settings64.sh The default mode for building the FPGA is to run a TCL script inside Vivado. Non project mode is used, to avoid the generation of project files, @@ -330,56 +330,6 @@ The default pin assignment for GPIO is described in the next table. | ``B9`` | ``E2[10]`` | I2C0_SDA | ``MIO[51]`` | ``906+ [51] = 957`` | requires ``pinctrl`` changes to be active | +--------+------------+--------------------+------------------+------------------------------+-------------------------------------------+ - -======================== -Linux access to GPIO/LED -======================== - -This document is used as reference: -`Linux+GPIO+Driver `_ - -There are 54+64=118 GPIO provided by ZYNQ PS, MIO provides 54 GPIO, -and EMIO provide additional 64 GPIO. - -The next formula is used to calculate the ``gpio_base`` index. - -.. code-block:: none - - base_gpio = ZYNQ_GPIO_NR_GPIOS - ARCH_NR_GPIOS = 1024 - 118 = -906 - -Values for the used macros can be found in the kernel sources. - -.. code-block:: shell-session - - $ grep ZYNQ_GPIO_NR_GPIOS drivers/gpio/gpio-zynq.c - #define ZYNQ_GPIO_NR_GPIOS 118 - $ grep -r CONFIG_ARCH_NR_GPIO tmp/linux-xlnx-xilinx-v2017.1 - tmp/linux-xlnx-xilinx-v2017.1/.config:CONFIG_ARCH_NR_GPIO=1024 - -Another way to find the `gpio_base` index is to check the given name inside `sysfs`. - -.. code-block:: shell-session - - # find /sys/class/gpio/ -name gpiochip* - /sys/class/gpio/gpiochip906 - -GPIOs are accessible at the ``sysfs`` index. -The next example will light up ``LED[0]``, and read back its value. - -.. code-block:: shell-session - - $ export INDEX=960 - $ echo $INDEX > /sys/class/gpio/export - $ echo out > /sys/class/gpio/gpio$INDEX/direction - $ echo 1 > /sys/class/gpio/gpio$INDEX/value - $ cat /sys/class/gpio/gpio$INDEX/value - -.. note:: - - `A new user space ABI for GPIO `_ - is coming in kernel v4.8, ioctl will be used instead of ``sysfs``. - The new driver will allow for seting multiple GPIO signals simultaneously. - =================== Linux access to LED =================== diff --git a/fpga/prj/axi4lite/dts/fpga.dts b/fpga/prj/axi4lite/dts/fpga.dts index 320811de4..d879ad535 100644 --- a/fpga/prj/axi4lite/dts/fpga.dts +++ b/fpga/prj/axi4lite/dts/fpga.dts @@ -1,33 +1,2 @@ -/include/ "system.dtsi" +/include/ "redpitaya.dtsi" /include/ "led-user.dtsi" -/include/ "uio.dtsi" - -/* - * Disable DMA after boot, must be anabled by a DT overlay - * TODO: it is probably not necessary to also disable each channel - */ - -&axi_dma_0 { - status = "disabled"; -}; -&axi_dma_1 { - status = "disabled"; -}; -&axi_dma_2 { - status = "disabled"; -}; - -/* - * Add Red Pitaya custom DMA consumer - */ - -&amba_pl { - rprx_2: rprx@2 { - compatible ="redpitaya,rprx"; - dmas = <&axi_dma_2 0 - &axi_dma_2 1>; - dma-names = "axidma0", "axidma1"; - memory-region = <&rprx_reserverd>; - status = "disabled"; - }; -}; diff --git a/fpga/prj/axi4lite/dts/fpga.dtso b/fpga/prj/axi4lite/dts/fpga.dtso index 68a8e350a..f83cd6055 100644 --- a/fpga/prj/axi4lite/dts/fpga.dtso +++ b/fpga/prj/axi4lite/dts/fpga.dtso @@ -1,2 +1,19 @@ /dts-v1/; /plugin/; +/ { + fragment@uio { + target = <&amba_pl>; + #address-cells = <1>; + #size-cells = <1>; + __overlay__ { + slave: slave@40000000 { + compatible = "generic-uio"; + reg = <0x40000000 0x01000>, + <0x40010000 0x10000>; + reg-names = "regset", "buffer"; + interrupt-parent = <&intc>; + interrupts = <0x3d 4>; + }; + }; + }; +}; diff --git a/fpga/prj/axi4lite/ip/system.tcl b/fpga/prj/axi4lite/ip/system.tcl index 68f1b16ac..82b047bc5 100644 --- a/fpga/prj/axi4lite/ip/system.tcl +++ b/fpga/prj/axi4lite/ip/system.tcl @@ -20,7 +20,7 @@ set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ -set scripts_vivado_version 2017.1 +set scripts_vivado_version 2017.2 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { @@ -178,6 +178,7 @@ CONFIG.PROTOCOL {AXI4LITE} \ set FCLK_RESET1_N [ create_bd_port -dir O -type rst FCLK_RESET1_N ] set FCLK_RESET2_N [ create_bd_port -dir O -type rst FCLK_RESET2_N ] set FCLK_RESET3_N [ create_bd_port -dir O -type rst FCLK_RESET3_N ] + set IRQ [ create_bd_port -dir I -type intr IRQ ] set PL_ACLK [ create_bd_port -dir I -type clk PL_ACLK ] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {M_AXI_GP0} \ @@ -470,6 +471,7 @@ CONFIG.PCW_USE_S_AXI_HP3 {0} \ connect_bd_intf_net -intf_net processing_system7_M_AXI_GP0 [get_bd_intf_pins axi_protocol_converter_0/S_AXI] [get_bd_intf_pins processing_system7/M_AXI_GP0] # Create port connections + connect_bd_net -net IRQ_1 [get_bd_ports IRQ] [get_bd_pins processing_system7/IRQ_F2P] connect_bd_net -net PL_ACLK_1 [get_bd_ports PL_ACLK] [get_bd_pins axi_protocol_converter_0/aclk] [get_bd_pins processing_system7/M_AXI_GP0_ACLK] connect_bd_net -net PL_ARESETn_1 [get_bd_ports PL_ARESETn] [get_bd_pins axi_protocol_converter_0/aresetn] connect_bd_net -net processing_system7_0_fclk_clk2 [get_bd_ports FCLK_CLK2] [get_bd_pins processing_system7/FCLK_CLK2] diff --git a/fpga/prj/axi4lite/rtl/axi4lite_gpio.sv b/fpga/prj/axi4lite/rtl/axi4lite_gpio.sv index 1edef7696..ab756bd15 100644 --- a/fpga/prj/axi4lite/rtl/axi4lite_gpio.sv +++ b/fpga/prj/axi4lite/rtl/axi4lite_gpio.sv @@ -8,6 +8,8 @@ module axi4lite_gpio #( output logic [DW-1:0] gpio_o, output logic [DW-1:0] gpio_t, input logic [DW-1:0] gpio_i, + // interrupt + output logic irq, // User ports ends axi4_lite_if.s bus ); @@ -77,6 +79,7 @@ always_ff @(posedge bus.ACLK) if (bus.ARESETn == 1'b0) begin gpio_o <= '0; gpio_t <= '0; + irq <= '0; end else if (slv_reg_wren) begin if (axi_awaddr == 2'h0) begin for (int unsigned i=0; i<(DW/8); i++) begin @@ -88,6 +91,9 @@ end else if (slv_reg_wren) begin if (bus.WSTRB[i]) gpio_t[(i*8)+:8] <= bus.WDATA[(i*8)+:8]; end end + if (axi_awaddr == 2'h3) begin + irq <= bus.WDATA[0]; + end end // Implement write response logic generation @@ -174,6 +180,7 @@ if (slv_reg_rden) begin 2'h0: bus.RDATA <= gpio_o; 2'h1: bus.RDATA <= gpio_t; 2'h2: bus.RDATA <= gpio_i; + 2'h3: bus.RDATA <= irq; // NOTE: a default is not really needed, values at address 2'h3 are undefined // default: bus.RDATA <= '0; endcase diff --git a/fpga/prj/axi4lite/rtl/red_pitaya_ps.sv b/fpga/prj/axi4lite/rtl/red_pitaya_ps.sv index 0fb369a2b..ec506a1a9 100644 --- a/fpga/prj/axi4lite/rtl/red_pitaya_ps.sv +++ b/fpga/prj/axi4lite/rtl/red_pitaya_ps.sv @@ -36,6 +36,8 @@ module red_pitaya_ps ( input logic [5-1:0] vinn_i, // slow analog voltages n // GPIO gpio_if.m gpio, + // interrupt + input logic irq, // system read/write channel axi4_lite_if.m bus ); @@ -120,7 +122,9 @@ system system ( // GPIO .GPIO_tri_i (gpio.i), .GPIO_tri_o (gpio.o), - .GPIO_tri_t (gpio.t) + .GPIO_tri_t (gpio.t), + // IRQ + .IRQ (irq) ); -endmodule +endmodule: red_pitaya_ps diff --git a/fpga/prj/axi4lite/rtl/red_pitaya_top.sv b/fpga/prj/axi4lite/rtl/red_pitaya_top.sv index ec19c3f62..db05d2f43 100644 --- a/fpga/prj/axi4lite/rtl/red_pitaya_top.sv +++ b/fpga/prj/axi4lite/rtl/red_pitaya_top.sv @@ -9,8 +9,8 @@ module red_pitaya_top #( // identification bit [0:5*32-1] GITH = '0, // module numbers - int unsigned MNA = 2, // number of acquisition modules - int unsigned MNG = 2 // number of generator modules + int unsigned MNO = 2, // number of oscilloscope modules + int unsigned MNG = 2 // number of generator modules )( // PS connections inout logic [54-1:0] FIXED_IO_mio , @@ -39,7 +39,7 @@ module red_pitaya_top #( // Red Pitaya periphery // ADC - input logic [MNA-1:0] [16-1:0] adc_dat_i, // ADC data + input logic [MNO-1:0] [16-1:0] adc_dat_i, // ADC data input logic [ 2-1:0] adc_clk_i, // ADC clock {p,n} output logic [ 2-1:0] adc_clk_o, // optional ADC clock source (unused) output logic adc_cdcs_o, // ADC clock duty cycle stabilizer @@ -70,66 +70,33 @@ module red_pitaya_top #( // local signals //////////////////////////////////////////////////////////////////////////////// + +// stream bus type +localparam type DTG = logic signed [14-1:0]; // generate +localparam type DTO = logic signed [16-1:0]; // acquire +localparam type DTL = logic unsigned [16-1:0]; // logic (generator/analyzer) +localparam type DTLG = struct packed {DTL e, o;}; + // GPIO parameter localparam int unsigned GDW = 8+8; -logic [4-1:0] fclk ; // {200MHz, 166MHz, 142MHz, 125MHz} +logic [4-1:0] fclk ; //[0]-125MHz, [1]-250MHz, [2]-50MHz, [3]-200MHz logic [4-1:0] frstn; // PLL signals -logic adc_clk_in; -logic pll_adc_clk; -logic pll_dac_clk_1x; -logic pll_dac_clk_2x; -logic pll_dac_clk_2p; -logic pll_ser_clk; -logic pll_pdm_clk; -logic pll_locked; -// fast serial signals -logic ser_clk ; -// PDM clock and reset -logic pdm_clk ; -logic pdm_rstn; +logic adc_clk_in; +logic pll_adc_clk; +logic pll_locked; // ADC clock/reset -logic adc_clk; -logic adc_rstn; - -// stream bus type -localparam type SBA_T = logic signed [ 14-1:0]; // acquire -localparam type SBG_T = logic signed [ 14-1:0]; // generate -localparam type SBL_T = logic [GDW-1:0]; // logic ananlyzer/generator +logic adc_clk; +logic adc_rstn; // DAC signals -logic dac_clk_1x; -logic dac_clk_2x; -logic dac_clk_2p; -logic dac_rst; -logic [MNG-1:0] [14-1:0] dac_dat; - -// calibration mul/sum type -localparam type CLM_T = logic signed [16-1:0]; -localparam type CLS_T = logic signed [14-1:0]; - -// multiplexer configuration -logic [MNG-1:0] mux_loop; -logic [MNG-1:0] mux_gen ; -logic mux_lg ; -// ADC calibration -CLM_T [MNA-1:0] adc_cfg_mul; // gain -CLS_T [MNA-1:0] adc_cfg_sum; // offset -// DAC calibration -CLM_T [MNG-1:0] dac_cfg_mul; // gain -CLS_T [MNG-1:0] dac_cfg_sum; // offset - -// system bus -logic bus_ACLK; -logic bus_ARESETn; -axi4_lite_if bus (.ACLK (bus_ACLK), .ARESETn (bus_ARESETn)); - -// GPIO interface -gpio_if #(.DW (24)) gpio (); -gpio_if #(.DW (24)) gpio_dummy (); +logic dac_clk_1x; +logic dac_clk_2x; +logic dac_clk_2p; +logic dac_rst; //////////////////////////////////////////////////////////////////////////////// // PLL (clock and reset) @@ -143,22 +110,17 @@ red_pitaya_pll pll ( .clk (adc_clk_in), // clock .rstn (frstn[0] ), // reset - active low // output clocks - .clk_adc (pll_adc_clk ), // ADC clock - .clk_dac_1x (pll_dac_clk_1x), // DAC clock 125MHz - .clk_dac_2x (pll_dac_clk_2x), // DAC clock 250MHz - .clk_dac_2p (pll_dac_clk_2p), // DAC clock 250MHz -45DGR - .clk_ser (pll_ser_clk ), // fast serial clock - .clk_pdm (pll_pdm_clk ), // PDM clock + .clk_adc (pll_adc_clk), // ADC clock + .clk_dac_1x (dac_clk_1x ), // DAC clock 125MHz + .clk_dac_2x (dac_clk_2x ), // DAC clock 250MHz + .clk_dac_2p (dac_clk_2p ), // DAC clock 250MHz -45DGR + .clk_ser ( ), // fast serial clock + .clk_pdm ( ), // PDM clock // status outputs .pll_locked (pll_locked) ); BUFG bufg_adc_clk (.O (adc_clk ), .I (pll_adc_clk )); -BUFG bufg_dac_clk_1x (.O (dac_clk_1x), .I (pll_dac_clk_1x)); -BUFG bufg_dac_clk_2x (.O (dac_clk_2x), .I (pll_dac_clk_2x)); -BUFG bufg_dac_clk_2p (.O (dac_clk_2p), .I (pll_dac_clk_2p)); -BUFG bufg_ser_clk (.O (ser_clk ), .I (pll_ser_clk )); -BUFG bufg_pdm_clk (.O (pdm_clk ), .I (pll_pdm_clk )); // TODO: reset is a mess logic top_rst; @@ -174,19 +136,96 @@ always_ff @(posedge dac_clk_1x, posedge top_rst) if (top_rst) dac_rst <= 1'b1; else dac_rst <= top_rst; -// PDM reset (active low) -always_ff @(posedge pdm_clk, posedge top_rst) -if (top_rst) pdm_rstn <= 1'b0; -else pdm_rstn <= ~top_rst; +//////////////////////////////////////////////////////////////////////////////// +// ADC IO +//////////////////////////////////////////////////////////////////////////////// + +// ADC AXI4-Stream interface +axi4_stream_if #(.DT (DTO)) str_adc [MNO-1:0] (.ACLK (adc_clk), .ARESETn (adc_rstn)); + +generate +for (genvar i=0; i; - dma-names = "axidma0", "axidma1"; - memory-region = <&rprx_reserverd>; - status = "disabled"; - }; -}; diff --git a/fpga/prj/logic/dts/fpga.dts b/fpga/prj/logic/dts/fpga.dts index 6239e9dbd..9d35b32b9 100644 --- a/fpga/prj/logic/dts/fpga.dts +++ b/fpga/prj/logic/dts/fpga.dts @@ -1,4 +1,3 @@ -/include/ "system.dtsi" +/include/ "redpitaya.dtsi" /include/ "led-user.dtsi" /include/ "dma.dtsi" -/include/ "uio.dtsi" diff --git a/fpga/prj/logic/dts/fpga.dtso b/fpga/prj/logic/dts/fpga.dtso index 68a8e350a..116c0fd6c 100644 --- a/fpga/prj/logic/dts/fpga.dtso +++ b/fpga/prj/logic/dts/fpga.dtso @@ -1,2 +1,71 @@ /dts-v1/; /plugin/; +/{ + fragment@1 { + target = <&axi_dma_2>; + __overlay__ { + status = "okay"; + }; + }; + fragment@2{ + target = <&amba_pl>; + __overlay__ { + id: id@40000000 { + compatible = "generic-uio"; + reg = <0x40000000 0x10000>; + }; + muxctl: muxctl@40040000 { + compatible = "generic-uio"; + reg = <0x40040000 0x10000>; + }; + calib: calib@40100000 { + compatible = "generic-uio"; + reg = <0x40100000 0x10000>; + }; + pdm: pdm@40140000 { + compatible = "generic-uio"; + reg = <0x40140000 0x10000>; + }; + pwm: pwm@40180000 { + compatible = "generic-uio"; + reg = <0x40180000 0x10000>; + }; + asg0: asg0@401c0000 { + compatible = "generic-uio"; + reg = <0x401c0000 0x40000>; + }; + asg1: asg1@40200000 { + compatible = "generic-uio"; + reg = <0x40200000 0x40000>; + }; + scope0: scope0@40240000 { + compatible = "generic-uio"; + reg = <0x40240000 0x10000>; + }; + scope1: scope1@40280000 { + compatible = "generic-uio"; + reg = <0x40280000 0x10000>; + }; + lg: lg@402c0000 { + compatible = "generic-uio"; + reg = <0x402c0000 0x40000>; + }; + la: la@40300000 { + compatible = "generic-uio"; + reg = <0x40300000 0x10000>; + }; + }; + }; + fragment@3{ + target = <&amba_pl>; + __overlay__ { + rprx_2: rprx@2 { + compatible ="redpitaya,rprx"; + dmas = <&axi_dma_2 0 + &axi_dma_2 1>; + dma-names = "axidma0", "axidma1"; + memory-region = <&rprx_reserverd>; + }; + }; + }; +}; diff --git a/fpga/prj/logic/ip/system.tcl b/fpga/prj/logic/ip/system.tcl index d1d59b6c6..44f6e0956 100644 --- a/fpga/prj/logic/ip/system.tcl +++ b/fpga/prj/logic/ip/system.tcl @@ -20,7 +20,7 @@ set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ -set scripts_vivado_version 2017.1 +set scripts_vivado_version 2017.2 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { @@ -523,7 +523,7 @@ CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ CONFIG.PCW_I2C0_I2C0_IO {MIO 50 .. 51} \ CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \ -CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {88.888893} \ +CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {111.111115} \ CONFIG.PCW_I2C_RESET_ENABLE {1} \ CONFIG.PCW_I2C_RESET_SELECT {Share reset pin} \ CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \ @@ -752,11 +752,6 @@ CONFIG.SINGLE_CHANNEL_SELECTION {TEMPERATURE} \ CONFIG.XADC_STARUP_SELECTION {independent_adc} \ ] $xadc - set_property -dict [ list \ -CONFIG.NUM_READ_OUTSTANDING {1} \ -CONFIG.NUM_WRITE_OUTSTANDING {1} \ - ] [get_bd_intf_pins /xadc/s_axi_lite] - # Create instance: xlconcat_0, and set properties set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] set_property -dict [ list \ diff --git a/fpga/prj/mercury/dts/fpga.dts b/fpga/prj/mercury/dts/fpga.dts index 40fa646fd..736430561 100644 --- a/fpga/prj/mercury/dts/fpga.dts +++ b/fpga/prj/mercury/dts/fpga.dts @@ -1,2 +1,6 @@ -/include/ "system.dtsi" +/include/ "redpitaya.dtsi" +/include/ "gpio.dtsi" /include/ "led-user.dtsi" + +// NOTE: Nodes from pl.dtsi are removed +// /delete-node/ &axi_intc_0; diff --git a/fpga/prj/mercury/dts/fpga.dtso b/fpga/prj/mercury/dts/fpga.dtso index 028ca29ea..d241c354a 100644 --- a/fpga/prj/mercury/dts/fpga.dtso +++ b/fpga/prj/mercury/dts/fpga.dtso @@ -2,6 +2,24 @@ /plugin/; /include/ "led-user.dtso" / { + // NOTE: device tree code for this node should be copied from pl.dtsi generated by Vivado DTG + fragment@irq { + target = <&amba_pl>; + #address-cells = <1>; + #size-cells = <1>; + __overlay__ { + axi_intc_0: interrupt-controller@81800000 { + #interrupt-cells = <2>; + compatible = "xlnx,xps-intc-1.00.a"; + interrupt-controller ; + interrupt-parent = <&intc>; + interrupts = <0 33 4>; + reg = <0x81800000 0x10000>; + xlnx,kind-of-intr = <0x3f>; + xlnx,num-intr-inputs = <0x6>; + }; + }; + }; fragment@uio { target = <&amba_pl>; #address-cells = <1>; @@ -30,50 +48,57 @@ gen0: gen0@40040000 { compatible = "generic-uio"; reg = <0x40040000 0x01000>, - <0x40050000 0x10000>; + <0x40050000 0x10000>; // 2**14 * sizeof(int32_t), TODO: int16_t reg-names = "regset", "buffer"; -// interrupt-parent = <&axi_intc_0>; -// interrupts = <0 1>; + interrupt-parent = <&axi_intc_0>; + interrupts = <0 1>; }; gen1: gen1@40060000 { compatible = "generic-uio"; reg = <0x40060000 0x01000>, - <0x40070000 0x10000>; + <0x40070000 0x10000>; // 2**14 * sizeof(int32_t), TODO: int16_t reg-names = "regset", "buffer"; -// interrupt-parent = <&axi_intc_0>; -// interrupts = <1 1>; + interrupt-parent = <&axi_intc_0>; + interrupts = <1 1>; }; osc0: osc0@40080000 { compatible = "generic-uio"; reg = <0x40080000 0x01000>, - <0x40090000 0x10000>; + <0x40090000 0x10000>; // 2**14 * sizeof(int16_t) * 2 (magic ring buffer) reg-names = "regset", "buffer"; -// interrupt-parent = <&axi_intc_0>; -// interrupts = <2 1>; + interrupt-parent = <&axi_intc_0>; + interrupts = <2 1>; }; osc1: osc1@400a0000 { compatible = "generic-uio"; reg = <0x400a0000 0x01000>, - <0x400b0000 0x10000>; + <0x400b0000 0x10000>; // 2**14 * sizeof(int16_t) * 2 (magic ring buffer) reg-names = "regset", "buffer"; -// interrupt-parent = <&axi_intc_0>; -// interrupts = <3 1>; + interrupt-parent = <&axi_intc_0>; + interrupts = <3 1>; }; lg: lg@400c0000 { compatible = "generic-uio"; reg = <0x400c0000 0x01000>, - <0x400d0000 0x10000>; + <0x400d0000 0x10000>; // 2**14 * sizeof(uint32_t), TODO: uint16_t reg-names = "regset", "buffer"; -// interrupt-parent = <&axi_intc_0>; -// interrupts = <4 1>; + interrupt-parent = <&axi_intc_0>; + interrupts = <4 1>; }; la: la@400e0000 { compatible = "generic-uio"; reg = <0x400e0000 0x01000>, - <0x400f0000 0x10000>; + <0x400f0000 0x10000>; // 2**14 * sizeof(uint16_t) * 2 (magic ring buffer) reg-names = "regset", "buffer"; -// interrupt-parent = <&axi_intc_0>; -// interrupts = <5 1>; + interrupt-parent = <&axi_intc_0>; + interrupts = <5 1>; + }; + ctrg: ctrg@40100000 { + compatible = "generic-uio"; + reg = <0x40100000 0x01000>; + reg-names = "regset"; + interrupt-parent = <&axi_intc_0>; + interrupts = <6 1>; }; }; }; diff --git a/fpga/prj/mercury/ip/system.tcl b/fpga/prj/mercury/ip/system.tcl index 62cd2bba0..23f33274a 100644 --- a/fpga/prj/mercury/ip/system.tcl +++ b/fpga/prj/mercury/ip/system.tcl @@ -20,7 +20,7 @@ set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ -set scripts_vivado_version 2017.1 +set scripts_vivado_version 2017.2 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { @@ -595,11 +595,6 @@ CONFIG.SINGLE_CHANNEL_SELECTION {TEMPERATURE} \ CONFIG.XADC_STARUP_SELECTION {independent_adc} \ ] $xadc - set_property -dict [ list \ -CONFIG.NUM_READ_OUTSTANDING {1} \ -CONFIG.NUM_WRITE_OUTSTANDING {1} \ - ] [get_bd_intf_pins /xadc/s_axi_lite] - # Create instance: xlconcat_0, and set properties set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] set_property -dict [ list \ diff --git a/fpga/prj/mercury/rtl/red_pitaya_ps.sv b/fpga/prj/mercury/rtl/red_pitaya_ps.sv index 9f22518a6..66628dc7f 100644 --- a/fpga/prj/mercury/rtl/red_pitaya_ps.sv +++ b/fpga/prj/mercury/rtl/red_pitaya_ps.sv @@ -27,34 +27,34 @@ module red_pitaya_ps ( // PS peripherals - inout logic [ 54-1:0] FIXED_IO_mio , - inout logic FIXED_IO_ps_clk , - inout logic FIXED_IO_ps_porb , - inout logic FIXED_IO_ps_srstb , - inout logic FIXED_IO_ddr_vrn , - inout logic FIXED_IO_ddr_vrp , + inout logic [54-1:0] FIXED_IO_mio , + inout logic FIXED_IO_ps_clk , + inout logic FIXED_IO_ps_porb , + inout logic FIXED_IO_ps_srstb, + inout logic FIXED_IO_ddr_vrn , + inout logic FIXED_IO_ddr_vrp , // DDR - inout logic [ 15-1:0] DDR_addr , - inout logic [ 3-1:0] DDR_ba , - inout logic DDR_cas_n , - inout logic DDR_ck_n , - inout logic DDR_ck_p , - inout logic DDR_cke , - inout logic DDR_cs_n , - inout logic [ 4-1:0] DDR_dm , - inout logic [ 32-1:0] DDR_dq , - inout logic [ 4-1:0] DDR_dqs_n , - inout logic [ 4-1:0] DDR_dqs_p , - inout logic DDR_odt , - inout logic DDR_ras_n , - inout logic DDR_reset_n , - inout logic DDR_we_n , + inout logic [15-1:0] DDR_addr , + inout logic [ 3-1:0] DDR_ba , + inout logic DDR_cas_n , + inout logic DDR_ck_n , + inout logic DDR_ck_p , + inout logic DDR_cke , + inout logic DDR_cs_n , + inout logic [ 4-1:0] DDR_dm , + inout logic [32-1:0] DDR_dq , + inout logic [ 4-1:0] DDR_dqs_n , + inout logic [ 4-1:0] DDR_dqs_p , + inout logic DDR_odt , + inout logic DDR_ras_n , + inout logic DDR_reset_n, + inout logic DDR_we_n , // system signals - output logic [ 4-1:0] fclk_clk_o , - output logic [ 4-1:0] fclk_rstn_o , + output logic [4-1:0] fclk_clk_o , + output logic [4-1:0] fclk_rstn_o, // XADC - input logic [ 5-1:0] vinp_i , // voltages p - input logic [ 5-1:0] vinn_i , // voltages n + input logic [5-1:0] vinp_i, // slow analog voltages p + input logic [5-1:0] vinn_i, // slow analog voltages n // GPIO gpio_if.m gpio, // interrupt @@ -94,7 +94,7 @@ assign fclk_rstn_o = fclk_rstn; BUFG fclk_buf [4-1:0] (.O(fclk_clk_o), .I(fclk_clk)); -system system_i ( +system system ( // MIO .FIXED_IO_mio (FIXED_IO_mio ), .FIXED_IO_ps_clk (FIXED_IO_ps_clk ), @@ -103,30 +103,30 @@ system system_i ( .FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn ), .FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp ), // DDR - .DDR_addr (DDR_addr ), - .DDR_ba (DDR_ba ), - .DDR_cas_n (DDR_cas_n ), - .DDR_ck_n (DDR_ck_n ), - .DDR_ck_p (DDR_ck_p ), - .DDR_cke (DDR_cke ), - .DDR_cs_n (DDR_cs_n ), - .DDR_dm (DDR_dm ), - .DDR_dq (DDR_dq ), - .DDR_dqs_n (DDR_dqs_n ), - .DDR_dqs_p (DDR_dqs_p ), - .DDR_odt (DDR_odt ), - .DDR_ras_n (DDR_ras_n ), - .DDR_reset_n (DDR_reset_n ), - .DDR_we_n (DDR_we_n ), + .DDR_addr (DDR_addr ), + .DDR_ba (DDR_ba ), + .DDR_cas_n (DDR_cas_n ), + .DDR_ck_n (DDR_ck_n ), + .DDR_ck_p (DDR_ck_p ), + .DDR_cke (DDR_cke ), + .DDR_cs_n (DDR_cs_n ), + .DDR_dm (DDR_dm ), + .DDR_dq (DDR_dq ), + .DDR_dqs_n (DDR_dqs_n ), + .DDR_dqs_p (DDR_dqs_p ), + .DDR_odt (DDR_odt ), + .DDR_ras_n (DDR_ras_n ), + .DDR_reset_n (DDR_reset_n), + .DDR_we_n (DDR_we_n ), // FCLKs - .FCLK_CLK0 (fclk_clk[0] ), - .FCLK_CLK1 (fclk_clk[1] ), - .FCLK_CLK2 (fclk_clk[2] ), - .FCLK_CLK3 (fclk_clk[3] ), - .FCLK_RESET0_N (fclk_rstn[0] ), - .FCLK_RESET1_N (fclk_rstn[1] ), - .FCLK_RESET2_N (fclk_rstn[2] ), - .FCLK_RESET3_N (fclk_rstn[3] ), + .FCLK_CLK0 (fclk_clk[0]), + .FCLK_CLK1 (fclk_clk[1]), + .FCLK_CLK2 (fclk_clk[2]), + .FCLK_CLK3 (fclk_clk[3]), + .FCLK_RESET0_N (fclk_rstn[0]), + .FCLK_RESET1_N (fclk_rstn[1]), + .FCLK_RESET2_N (fclk_rstn[2]), + .FCLK_RESET3_N (fclk_rstn[3]), // XADC .Vaux0_v_n (vinn_i[1]), .Vaux0_v_p (vinp_i[1]), .Vaux1_v_n (vinn_i[2]), .Vaux1_v_p (vinp_i[2]), @@ -194,4 +194,4 @@ system system_i ( assign axi_gp.AWREGION = '0; assign axi_gp.ARREGION = '0; -endmodule +endmodule: red_pitaya_ps diff --git a/fpga/prj/mercury/rtl/red_pitaya_top.sv b/fpga/prj/mercury/rtl/red_pitaya_top.sv index 9b515a51e..7766ef400 100644 --- a/fpga/prj/mercury/rtl/red_pitaya_top.sv +++ b/fpga/prj/mercury/rtl/red_pitaya_top.sv @@ -77,13 +77,6 @@ localparam type DTO = logic signed [16-1:0]; // acquire localparam type DTL = logic unsigned [16-1:0]; // logic (generator/analyzer) localparam type DTLG = struct packed {DTL e, o;}; -//typedef struct packed { -// DTL e; -// DTL o; -//} dtlg_t; - -//localparam type DTLG = dtlg_t; - // GPIO parameter localparam int unsigned GDW = 8+8; @@ -229,7 +222,7 @@ top_pkg::irq_t irq; // system bus sys_bus_if ps_sys (.clk (adc_clk), .rstn (adc_rstn)); -sys_bus_if sys [16-1:0] (.clk (adc_clk), .rstn (adc_rstn)); +sys_bus_if sys [32-1:0] (.clk (adc_clk), .rstn (adc_rstn)); // GPIO interface gpio_if #(.DW (24)) gpio (); @@ -243,34 +236,34 @@ axi4_stream_if #(.DT (DTL)) srx_la (.ACLK (adc_clk), .ARESETn (adc_rs //////////////////////////////////////////////////////////////////////////////// red_pitaya_ps ps ( - .FIXED_IO_mio ( FIXED_IO_mio ), - .FIXED_IO_ps_clk ( FIXED_IO_ps_clk ), - .FIXED_IO_ps_porb ( FIXED_IO_ps_porb ), - .FIXED_IO_ps_srstb ( FIXED_IO_ps_srstb ), - .FIXED_IO_ddr_vrn ( FIXED_IO_ddr_vrn ), - .FIXED_IO_ddr_vrp ( FIXED_IO_ddr_vrp ), + .FIXED_IO_mio (FIXED_IO_mio ), + .FIXED_IO_ps_clk (FIXED_IO_ps_clk ), + .FIXED_IO_ps_porb (FIXED_IO_ps_porb ), + .FIXED_IO_ps_srstb (FIXED_IO_ps_srstb), + .FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn ), + .FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp ), // DDR - .DDR_addr (DDR_addr ), - .DDR_ba (DDR_ba ), - .DDR_cas_n (DDR_cas_n ), - .DDR_ck_n (DDR_ck_n ), - .DDR_ck_p (DDR_ck_p ), - .DDR_cke (DDR_cke ), - .DDR_cs_n (DDR_cs_n ), - .DDR_dm (DDR_dm ), - .DDR_dq (DDR_dq ), - .DDR_dqs_n (DDR_dqs_n ), - .DDR_dqs_p (DDR_dqs_p ), - .DDR_odt (DDR_odt ), - .DDR_ras_n (DDR_ras_n ), - .DDR_reset_n (DDR_reset_n ), - .DDR_we_n (DDR_we_n ), + .DDR_addr (DDR_addr ), + .DDR_ba (DDR_ba ), + .DDR_cas_n (DDR_cas_n ), + .DDR_ck_n (DDR_ck_n ), + .DDR_ck_p (DDR_ck_p ), + .DDR_cke (DDR_cke ), + .DDR_cs_n (DDR_cs_n ), + .DDR_dm (DDR_dm ), + .DDR_dq (DDR_dq ), + .DDR_dqs_n (DDR_dqs_n ), + .DDR_dqs_p (DDR_dqs_p ), + .DDR_odt (DDR_odt ), + .DDR_ras_n (DDR_ras_n ), + .DDR_reset_n (DDR_reset_n), + .DDR_we_n (DDR_we_n ), // system signals - .fclk_clk_o (fclk ), - .fclk_rstn_o (frstn ), + .fclk_clk_o (fclk ), + .fclk_rstn_o (frstn ), // ADC analog inputs - .vinp_i (vinp_i ), - .vinn_i (vinn_i ), + .vinp_i (vinp_i ), + .vinn_i (vinn_i ), // GPIO .gpio (gpio), // interrupt @@ -279,27 +272,28 @@ red_pitaya_ps ps ( .srx_osc (srx_osc), .srx_la (srx_la ), // system read/write channel - .bus (ps_sys ) + .bus (ps_sys ) ); //////////////////////////////////////////////////////////////////////////////// -// system bus decoder & multiplexer (it breaks memory addresses into 16 regions) +// system bus decoder & multiplexer +// it breaks memory addresses into 32 regions of 64kB each //////////////////////////////////////////////////////////////////////////////// sys_bus_interconnect #( - .SN (16), + .SN (32), .SW (16) ) sys_bus_interconnect ( .bus_m (ps_sys), .bus_s (sys) ); -//// silence unused busses -//generate -//for (genvar i=2; i<3; i++) begin: for_sys_2 -// sys_bus_stub sys_bus_stub_2 (sys[i]); -//end: for_sys_2 -//endgenerate +// silence unused busses +generate +for (genvar i=17; i<32; i++) begin: for_sys_2 + sys_bus_stub sys_bus_stub_2 (sys[i]); +end: for_sys_2 +endgenerate //////////////////////////////////////////////////////////////////////////////// // identification @@ -316,7 +310,7 @@ id #(.GITH (GITH)) id ( // GPIO mode DTL exp_iom; -logic [3-1:0] mgmt_loop; +logic [2-1:0] mgmt_loop; mgmt #(.GW ($bits(DTL))) mgmt ( // GPIO mode @@ -559,6 +553,7 @@ for (genvar i=0; i; -// #size-cells = <1>; -// area@0 { -// compatible = "fpga-area"; -// #address-cells = <1>; -// #size-cells = <1>; -// ranges; -// -// firmware-name = "/boot/fpga/fpga2.bin"; -// }; -// }; -// }; - - fragment@1 { - target-path = "/amba_pl/dma\@80420000"; - __overlay__ { - status = "okay"; - }; - }; - fragment@2 { - target-path = "/amba_pl/dma\@80420000/dma-channel@80420000"; - __overlay__ { - status = "okay"; - }; - }; - fragment@3 { - target-path = "/amba_pl/dma\@80420000/dma-channel@80420030"; - __overlay__ { - status = "okay"; - }; - }; - fragment@4{ - target-path="/amba_pl/id@40000000"; - __overlay__ { - status = "okay"; - }; - }; - fragment@5{ - target-path="/amba_pl/muxctl@40040000"; - __overlay__ { - status = "okay"; - }; - }; - fragment@8{ - target-path="/amba_pl/calib@40100000"; - __overlay__ { - status = "okay"; - }; - }; - fragment@9{ - target-path="/amba_pl/pdm@40140000"; - __overlay__ { - status = "okay"; - }; - }; - fragment@a{ - target-path="/amba_pl/pwm@40180000"; - __overlay__ { - status = "okay"; - }; - }; - fragment@b{ - target-path="/amba_pl/asg0@401c0000"; - __overlay__ { - status = "okay"; - }; - }; - fragment@c{ - target-path="/amba_pl/asg1@40200000"; - __overlay__ { - status = "okay"; - }; - }; - fragment@d{ - target-path="/amba_pl/scope0@40240000"; - __overlay__ { - status = "okay"; - }; - }; - fragment@e{ - target-path="/amba_pl/scope1@40280000"; - __overlay__ { - status = "okay"; - }; - }; - fragment@f{ - target-path="/amba_pl/lg@402c0000"; - __overlay__ { - status = "okay"; - }; - }; - fragment@10{ - target-path="/amba_pl/la@40300000"; - __overlay__ { - status = "okay"; - }; - }; - fragment@11{ - target-path="/amba_pl/rprx@2"; - __overlay__ { - status = "okay"; - }; - }; -}; -//compile overlay -//dtc -O dtb -o amba_pl.dtbo -b 0 -@ amba_pl.dts -//preprair -//mkdir /sys/kernel/config/device-tree/overlays/amba_pl -//apply -//cat amba_pl.dtbo > /sys/kernel/config/device-tree/overlays/amba_pl/dtbo -//remove -//rmdir /sys/kernel/config/device-tree/overlays/amba_pl diff --git a/patches/devicetree/amba_pl.sh b/patches/devicetree/amba_pl.sh deleted file mode 100644 index 9f7631110..000000000 --- a/patches/devicetree/amba_pl.sh +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/bash -mkdir /sys/kernel/config/device-tree/overlays/amba_pl -cat amba_pl.dtbo > /sys/kernel/config/device-tree/overlays/amba_pl/dtbo -# wait a bit for the kernel to process the overlay, -# before attempts are made to use the new drivers -sleep 0.5s diff --git a/patches/devicetree/rmamba_pl.sh b/patches/devicetree/rmamba_pl.sh deleted file mode 100644 index fece1ff27..000000000 --- a/patches/devicetree/rmamba_pl.sh +++ /dev/null @@ -1,2 +0,0 @@ -#!/bin/bash -rmdir /sys/kernel/config/device-tree/overlays/amba_pl diff --git a/scpi-server/Makefile b/scpi-server/Makefile index e8d07b49c..57573bb1a 100644 --- a/scpi-server/Makefile +++ b/scpi-server/Makefile @@ -14,7 +14,7 @@ APP=$(notdir $(CURDIR:%/=%)) # Installation directory. It is changed when using the main Makefile++++++ INSTALL_DIR ?= . -LIBSCPI=scpi-parser/libscpi/dist/libscpi.so.2.1.0 +LIBSCPI=scpi-parser/libscpi/dist/libscpi.a SCPISRV=scpi-server ARTIFACTS= $(LIBSCPI) $(SCPISRV) @@ -28,10 +28,7 @@ $(LIBSCPI): install: mkdir -p $(INSTALL_DIR)/bin - mkdir -p $(INSTALL_DIR)/lib cp $(SCPISRV) $(INSTALL_DIR)/bin - $(MAKE) -C scpi-parser install PREFIX=$(INSTALL_DIR) - ln -sf libscpi.so.2.1.0 $(INSTALL_DIR)/lib/libscpi.so clean: $(MAKE) -C src clean diff --git a/scpi-server/src/Makefile b/scpi-server/src/Makefile index 9feb05fe6..7e7388a36 100644 --- a/scpi-server/src/Makefile +++ b/scpi-server/src/Makefile @@ -52,7 +52,7 @@ LDFLAGS= # Additional libraries which needs to be dynamically linked to the executable # -lm - System math library (used by cos(), sin(), sqrt(), ... functions) LIBPATH= -L ../scpi-parser/libscpi/dist -L ../../api/lib -LIBS= -lm -lpthread -lrp -lscpi +LIBS= -lm -lpthread -lrp -l:libscpi.a INC= -I../scpi-parser/libscpi/inc -I../../api/include diff --git a/settings.sh b/settings.sh index 6e13fb35e..b7d4d1a73 100644 --- a/settings.sh +++ b/settings.sh @@ -2,7 +2,7 @@ # setup Xilinx Vivado FPGA tools ################################################################################ -. /opt/Xilinx/Vivado/2017.1/settings64.sh +. /opt/Xilinx/Vivado/2017.2/settings64.sh ################################################################################ # setup cross compiler toolchain