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base repository: tillitis/tillitis-key1
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base: d88af31992b27d17e094b4ae28d7d9b9805b37f0
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head repository: tillitis/tillitis-key1
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compare: 221d67389510acf79b42257c7331f96c3f0f7699
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Showing with 35 additions and 43 deletions.
  1. +35 −43 hw/application_fpga/core/tk1/tb/tb_tk1.v
78 changes: 35 additions & 43 deletions hw/application_fpga/core/tk1/tb/tb_tk1.v
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Original file line number Diff line number Diff line change
@@ -60,6 +60,7 @@ module tb_tk1 ();
localparam ADDR_SPI_XFER = 8'h81;
localparam ADDR_SPI_DATA = 8'h82;

localparam APP_RAM_START = 32'h40000000;

//----------------------------------------------------------------
// Register and Wire declarations.
@@ -368,20 +369,35 @@ module tb_tk1 ();


//----------------------------------------------------------------
// check_equal()
// `check_equal()
//
// Check that two values are equal
//----------------------------------------------------------------
task check_equal(input [31:0] value, input [31:0] expected);
begin : check_equal
if (DEBUG) begin
if (value != expected) begin
$display("--- Error: Got 0x%x, expected 0x%x", value, expected);
error_ctr = error_ctr + 1;
end
end
`define check_equal(_value, _expected) \
begin \
if ((_value) != (_expected)) begin \
$display("--- Error: (%s) != (%s)\n 0x%x != 0x%x", `"_value`", `"_expected`", (_value), (_expected)); \
error_ctr = error_ctr + 1; \
end \
end // `check_equal


//----------------------------------------------------------------
// fetch_instruction()
//
// Simulate fetch of an instruction at specified address.
//----------------------------------------------------------------
task fetch_instruction(input [31:0] address);
begin : fetch_instruction
tb_cpu_addr = address;
tb_cpu_instr = 1'h1;
tb_cpu_valid = 1'h1;
#(CLK_PERIOD);
tb_cpu_addr = 32'h0;
tb_cpu_instr = 1'h0;
tb_cpu_valid = 1'h0;
end
endtask // check_equal
endtask // fetch_instruction


//----------------------------------------------------------------
@@ -456,13 +472,7 @@ module tb_tk1 ();
read_check_word(ADDR_CDI_LAST + 0, 32'h70717273);

$display("--- test3: Fetch instruction from app RAM.");
tb_cpu_addr = 32'h40000000;
tb_cpu_instr = 1'h1;
tb_cpu_valid = 1'h1;
#(1 * CLK_PERIOD);
tb_cpu_addr = 32'h0;
tb_cpu_instr = 1'h0;
tb_cpu_valid = 1'h0;
fetch_instruction(APP_RAM_START);

$display("--- test3: Try to write CDI again.");
write_word(ADDR_CDI_FIRST + 0, 32'hfffefdfc);
@@ -510,13 +520,7 @@ module tb_tk1 ();
read_check_word(ADDR_BLAKE2S, 32'hcafebabe);

$display("--- test4: Fetch instruction from app RAM.");
tb_cpu_addr = 32'h40000000;
tb_cpu_instr = 1'h1;
tb_cpu_valid = 1'h1;
#(1 * CLK_PERIOD);
tb_cpu_addr = 32'h0;
tb_cpu_instr = 1'h0;
tb_cpu_valid = 1'h0;
fetch_instruction(APP_RAM_START);

$display("--- test4: Write Blake2s entry point again.");
write_word(ADDR_BLAKE2S, 32'hdeadbeef);
@@ -552,13 +556,7 @@ module tb_tk1 ();
read_check_word(ADDR_APP_SIZE, 32'h47114711);

$display("--- test5: Fetch instruction from app RAM.");
tb_cpu_addr = 32'h40000000;
tb_cpu_instr = 1'h1;
tb_cpu_valid = 1'h1;
#(1 * CLK_PERIOD);
tb_cpu_addr = 32'h0;
tb_cpu_instr = 1'h0;
tb_cpu_valid = 1'h0;
fetch_instruction(APP_RAM_START);

$display("--- test5: Write app start address and size again.");
write_word(ADDR_APP_START, 32'hdeadbeef);
@@ -595,17 +593,11 @@ module tb_tk1 ();
"--- test6: Check value in dut ADDR_RAM_ADDR_RAND and ADDR_RAM_DATA_RAND registers.");
$display("--- test6: ram_addr_rand_reg: 0x%04x, ram_data_rand_reg: 0x%08x",
dut.ram_addr_rand, dut.ram_data_rand);
check_equal(dut.ram_addr_rand, 32'h13371337 & {15{1'b1}});
check_equal(dut.ram_data_rand, 32'h47114711);
`check_equal(dut.ram_addr_rand, 32'h13371337 & {15{1'b1}});
`check_equal(dut.ram_data_rand, 32'h47114711);

$display("--- test6: Fetch instruction from app RAM.");
tb_cpu_addr = 32'h40000000;
tb_cpu_instr = 1'h1;
tb_cpu_valid = 1'h1;
#(1 * CLK_PERIOD);
tb_cpu_addr = 32'h0;
tb_cpu_instr = 1'h0;
tb_cpu_valid = 1'h0;
fetch_instruction(APP_RAM_START);

$display("--- test6: Write to ADDR_RAM_ADDR_RAND and ADDR_RAM_DATA_RAND again.");
write_word(ADDR_RAM_ADDR_RAND, 32'hdeadbeef);
@@ -615,8 +607,8 @@ module tb_tk1 ();
"--- test6: Check value in dut ADDR_RAM_ADDR_RAND and ADDR_RAM_DATA_RAND registers.");
$display("--- test6: ram_addr_rand_reg: 0x%04x, ram_data_rand_reg: 0x%08x",
dut.ram_addr_rand, dut.ram_data_rand);
check_equal(dut.ram_addr_rand, 32'h13371337 & {15{1'b1}});
check_equal(dut.ram_data_rand, 32'h47114711);
`check_equal(dut.ram_addr_rand, 32'h13371337 & {15{1'b1}});
`check_equal(dut.ram_data_rand, 32'h47114711);

$display("--- test6: completed.");
$display("");
@@ -709,7 +701,7 @@ module tb_tk1 ();
$display("--- test9: cpu_addr: 0x%08x, cpu_instr: 0x%1x, cpu_valid: 0x%1x", tb_cpu_addr,
tb_cpu_instr, tb_cpu_valid);
$display("--- test9: force_trap: 0x%1x", tb_force_trap);
check_equal(tb_force_trap, 1);
`check_equal(tb_force_trap, 1);

$display("--- test9: restore CPU mem interface.");
tb_cpu_addr = 32'h0;