diff --git a/Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf b/Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
index 9208aeda5d2..6ca0ada751f 100644
--- a/Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
+++ b/Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
@@ -36,8 +36,8 @@
   MinPlatformPkg/MinPlatformPkg.dec
 
 [Pcd]
-  gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase                    ## CONSUMES
-  gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize                    ## CONSUMES
+  gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase          ## CONSUMES
+  gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize          ## CONSUMES
 
 [Sources]
   BiosInfo.c
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/FlashMapInclude.fdf b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/FlashMapInclude.fdf
index d9959a79d0b..7d2f4b2c0cb 100644
--- a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/FlashMapInclude.fdf
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/FlashMapInclude.fdf
@@ -34,8 +34,8 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset          = 0x00190000
 SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize            = 0x00190000  #
 SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset        = 0x00320000  # Flash addr (0xFFB20000)
 SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize          = 0x00170000  #
-SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset                  = 0x00490000  # Flash addr (0xFFC90000)
-SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize                    = 0x000B0000  #
+SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset        = 0x00490000  # Flash addr (0xFFC90000)
+SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize          = 0x000B0000  #
 SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset              = 0x00540000  # Flash addr (0xFFD40000)
 SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize                = 0x00070000  #
 SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset              = 0x005B0000  # Flash addr (0xFFDB0000)
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf
index 795cc0da75d..6397d80d389 100644
--- a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf
@@ -31,8 +31,8 @@
 # assigned with PCD values. Instead, it uses the definitions for its variety, which
 # are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS.
 #
-BaseAddress   = $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress      #The base address of the FLASH Device.
-Size          = $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdBiosSize             #The size in bytes of the FLASH Device
+BaseAddress   = $(FLASH_BASE) | gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress  #The base address of the FLASH Device.
+Size          = $(FLASH_SIZE) | gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize             #The size in bytes of the FLASH Device
 ErasePolarity = 1
 BlockSize     = $(FLASH_BLOCK_SIZE)
 NumBlocks     = $(FLASH_NUM_BLOCKS)
@@ -43,21 +43,21 @@ DEFINE SIPKG_PEI_BIN      = INF
 # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because macro expression is not supported.
 # So, PlatformSecLib uses PcdBiosAreaBaseAddress + PcdNemCodeCacheBase to get the real CodeCache base address.
 SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase = $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset)
-SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
-SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
-SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
-SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
+SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
+SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = $(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
+SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
+SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
 SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv     = 0x60
-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase    = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize    = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset  = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize    = gSiPkgTokenSpaceGuid.PcdBiosSize
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress       = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress       = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
-SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress       = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress    = gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize           = gSiPkgTokenSpaceGuid.PcdBiosSize
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase    = gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize    = gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset  = gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize    = gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress       = $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress       = $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress       = $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress    = gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize           = gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize
 ################################################################################
 #
 # Following are lists of FD Region layout which correspond to the locations of different
@@ -153,8 +153,8 @@ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTokenSpa
 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
 FV = FvPostMemory
 
-gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
-gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
+gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
+gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
 #Microcode
 FV = FvMicrocode
 
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.inf b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.inf
index 1d09b990b16..abb79c111e0 100644
--- a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.inf
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.inf
@@ -47,8 +47,8 @@
 
 [Pcd]
   gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress                     ## CONSUMES
-  gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase                          ## CONSUMES
-  gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize                          ## CONSUMES
+  gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase                ## CONSUMES
+  gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize                ## CONSUMES
   gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable
   gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPlatformFlavor
   gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPlatformType